Abstract: A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.

Abstract: A method and device are provided for producing mobile radio signals, which utilize a direct conversion receiver, at least one first and one second local oscillator and one regenerative divider for processing signals according to different mobile radio standards. For generating the intermediate frequency for transmission according to at least one of the mobile radio standards, a division by four in addition to a division by three of the oscillator frequency is also possible.

Abstract: A PLL circuit having a function of a frequency multiplier comprises a phase detector circuit receiving an input signal, for producing an error signal which includes an alternating current component having a relatively high frequency depending on the frequency of a frequency-multiplied signal, a low pass loop filter, a voltage controlled oscillator, and a comparison signal generating circuit for generating N phase comparison signals. The phase detector circuit comprises a phase splitting circuit for generating from the input signal N phase split signals having respectively different N phases and N phase detectors for comparing the phases of the N phase split signals with different phases of the N phase comparison signal respectively.

Abstract: A line locking system for use with X-ray video imaging equipment comprising: a system oscillator, a divider for frequency dividing the output of the system oscillator to obtain a signal having a frequency that is an integer multiple of the line frequency, a comparator for comparing the phase of the integer multiple signal to the phase of the line signal and means for controlling the oscillator frequency responsive to the output of the comparator.

Abstract: A frequency lock system including an oscillator providing a switching output voltage that switches at a given frequency between fixed periods in each of first and second states and a reference source providing a variable reference voltage that periodically varies from and returns to a given voltage level at a predetermined frequency less than 1/2 the given frequency. A reference lock circuit provides a reference pulse of finite width in response to occurrence of the given voltage level and an oscillator lock circuit provides a control pulse of finite width a certain period after switching of the output from its first to its second state. In addition, a reset circuit resets the oscillator to initiate a new fixed period thereof at the second state in response to temporal coincidence of the reference and control pulses.

Abstract: A phase-lock system including an oscillator providing a switching output that continuously switches between first and second states, a trigger circuit for inducing switching of the oscillator, a sensing circuit monitoring the switching output and providing an anticipating indication of an imminent switching thereof from the first to the second state, and a primary voltage source providing a variable voltage that periodically varies from and returns to a given voltage level. Also included is a detector circuit monitoring the variable voltage and detecting the presence of the given voltage level and a synchronizing circuit responsive to the sensing and detector circuits and providing an input to the trigger circuit, the synchronizing circuit being operative to cause switching of the oscillator in response to the simultaneous provision of the anticipating indication by the sensing circuit and detection of the given level by the detector circuit.

Abstract: In a digital fluorography system a television (TV) camera converts X-ray images to analog video signals that are converted to digital pixel words in an analog-to-digital converter (ADC). The sync signals for the TV camera and the sample clock signals for the ADC are derived from a novel resettable crystal controlled sync generator. A phase-locked loop provides an ac reference signal at one-half power line frequency which is equivalent to TV frame rate. The sync generator is reset to start a new frame and an ensuing sequence of crystal controlled horizontal sync pulses only in response to occurrence of ac reference signals so every frame is in registration. A digital video processor (DVP) subtracts a mask image from each image in a sequence of images that are acquired while an X-ray contrast medium is appearing in and disappearing from a blood vessel. The resulting difference images are stored in analog video signal format in an analog video disk recorder.

Abstract: In a digital fluorography system a television (TV) camera converts X-ray images to analog video signals that are converted to digital pixel words in an analog-to-digital converter (ADC). The sync signals for the TV camera and the sample clock signals for the ADC are derived from a novel resettable crystal controlled sync generator. A phase-locked loop provides an ac reference signal at one-half power line frequency which is equivalent to TV frame rate. The sync generator is reset to start a new frame and an ensuing sequence of crystal controlled horizontal sync pulses only in response to occurrence of ac reference signals so every frame is in registration. A digital video processor (DVP) subtracts a mask image from each image in a sequence of images that are acquired while an X-ray contrast medium is appearing in and disappearing from a blood vessel. The resulting difference images are stored in analog video signal format in an analog video disk recorder.

Abstract: In a cathode ray tube (CRT) display system using a horizontal line raster scan, the vertical sync signals are derived from the power line alternating current while the vertical blanking signals to blank the vertical retraces between rasters are timed to occur over an interval which starts before a vertical sync signal and ends a period of time after the vertical sync signal which is no less than the minimum time required for a vertical retrace.