Abstract: A sensitivity boosted laser dispersion spectroscopy system for sensing a sample in a sample cell or in an open path crossing the sample. The system includes a local oscillator arm and a sample arm containing the sample cell or the open path crossing the sample. A laser source is configured to generate a first light beam directed along the sample arm and a second light beam, the second light beam being frequency shifted and directed along the local oscillator arm. An intensity modulator/phase modulator/frequency shifter is disposed in the sample arm configured to generate a multi-frequency beam having known frequency spacing which is then passed through the sample cell to generate a sample arm output. A beam combiner is configured to combine the sample arm output and the second light beam from the local oscillator arm and generate a combined beam. A photodetector is configured to detect the combined beam for sensing the sample in the sample cell.

Abstract: A processing device for use with a video conferencing network is provided. The processing device includes memory configured to store data and a processor. The processor is configured to determine a first sampling phase for a portion of first video data and chrominance sub-sample the portion of first video data using the first sampling phase. The processor is also configured to encode the sub-sampled portion of first video data and decode a sub-sampled, encoded portion of second video data. The processor is further configured to determine a second sampling phase at which the portion of second video data is chrominance sub-sampled and chrominance up-sample the portion of second video data using the second sample phase.

Abstract: Provided are an apparatus and method of converting a digital image signal, which is obtained through an image sensor comprising a plurality of pixels that are arranged in a matrix, into an analog image signal in order to transmit the analog image signal to a monitor device that outputs an image complying with a national television system committee (NTSC) standard or a phase-alternating line (PAL) standard. The method includes: generating a sample frequency based on the number of horizontal pixels of the digital image signal to comply with a horizontal scan period of the NTSC standard or the PAL standard; and converting image data of the horizontal pixels of the digital image signal into the analog image signal, according to the sample frequency.

Abstract: Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.

Abstract: A signal recovery circuit includes: a data acquisition circuit configured to collect a received data signal according to a transition edge of a received signal recovery clock; and a phase adjustment circuit configured to adjust a phase relationship between the transition edge of the received signal recovery clock and the received data signal according to a data value of the received data signal to be acquired by the data acquisition circuit.

Abstract: A method of audio signal processing includes determining a difference between a first set of filter parameters of a first input frame of an active noise cancellation (ANC) filter and a second set of filter parameters of a second input frame of the ANC filter. The method further includes selectively modifying a duty cycle of adaptive ANC processing associated with the ANC filter based on the difference between the first set of filter parameters and the second set of filter parameters.

Abstract: An in-vehicle apparatus includes an FM radio tuner that receives FM broadcast waves of a reception frequency that is set; a FM radio controller; an LCD unit that is capable of changing a horizontal synchronous frequency corresponding to each horizontal line by varying a horizontal blanking period along the horizontal direction, without changing the numbers of effective pixels in horizontal display and vertical display, and an effective display period; a horizontal synchronous frequency setter that sets the horizontal synchronous frequency so that a minimum value of the differences between the reception frequency of the FM broadcast waves and multiplied frequencies that are integral multiples of the horizontal synchronous frequency is higher than or equal to a certain value; and a video processor that generates a video signal necessary to display at least one of a working screen and an operation screen in the LCD unit.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. In one aspect, a frame identifier in a physical layer header of the digitized signal is utilized to estimate a first phase associated with the frame identifier. The remaining portion of the physical layer header is utilized to estimate a second phase associated with the remaining portion. The first phase estimate and the second phase estimate are combined to generate a first combined phase estimate.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. A digitized signal representative of a wireless signal may be received. A frame identifier in a physical layer header in the signal may be identified by correlating the digitized signal to one or more known frame identifiers. The identified frame identifier may be used to estimate a phase or frequency error.

Abstract: A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

Abstract: A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to a reference signal and a feedback signal. The loop filter filters the phase difference signal to generate a filtered signal. The controllable oscillator generates the frequency signal according to the filtered signal. The first frequency divider generates the feedback signal by dividing a frequency of the frequency signal according to a dividing factor. The SDM determines the dividing factor according to a control signal.

Abstract: An apparatus, comprising: a first oscillator made from piezoelectric material to oscillate at a first frequency; a second oscillator to oscillate at a second frequency; a comparator to compare the first frequency to the second frequency; and a controller to change the first frequency in response to the comparing of the first frequency to the second frequency.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. A digitized signal representative of a wireless signal may be received. A frame identifier in a physical layer header in the signal may be identified by correlating the digitized signal to one or more known frame identifiers. The identified frame identifier may be used to estimate a phase or frequency error.

Abstract: A method and device are provided for producing mobile radio signals, which utilize a direct conversion receiver, at least one first and one second local oscillator and one regenerative divider for processing signals according to different mobile radio standards. For generating the intermediate frequency for transmission according to at least one of the mobile radio standards, a division by four in addition to a division by three of the oscillator frequency is also possible.

Abstract: A system clock generation module varies an oscillation frequency and outputs a frequency diffused clock as a system clock. A synchronizing signal measurement module measures a synchronizing signal characteristic value, which includes at least a synchronizing signal period and a synchronizing signal cycle corresponding to an input image signal, relative to a measurement clock generated from the system clock as a reference. An image signal analyzing module determines that specification of the input image signal is changed when the observed synchronizing signal characteristic value is out of a predetermined range, while determining that the specification of the input image signal is unchanged when the observed synchronizing signal characteristic value is in the predetermined range. The image signal analyzing module analyzes the input image signal according to a result of the determination. This arrangement of the present invention ensures stable analysis of the specification of the input image signal.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment incsc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by ?h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nomimal increment (nom_incsc) and a feed forwarded scaled version of ?h.

Abstract: A PLL architecture with fast phase acquisition, a stable freerun output frequency, and post-freerun fast phase recovery. The invention is particularly well suited for use in a video graphics a/d conversion circuit. An intelligent phase lock loop is optimized to determine the time difference between the closest rising edge of an PLL output signal and the rising edge of an input signal. The time difference in combination with the current PLL lock state determine an operational code used in a digital signal processing loop filter used to control a digitally controlled oscillator. The PLL also provides a stable output frequency during freerun periods, and a phase booster circuit for post-freerun fast phase recovery.

Abstract: A switch circuit is provided for at least one of a previous stage of a VHF-band frequency converter and a previous stage of a UHF-band frequency converter. Each switch circuit passes a signal when a frequency converter at a subsequent stage of the switch circuit is operating, and does not pass a signal when the frequency converter at the subsequent stage of the switch circuit is not operating.

Abstract: A voltage boost system for smoothly converging an output voltage of a voltage booster when feedback controlling the output voltage. The voltage boost system includes a voltage booster to increase an input voltage and generate a boosted output voltage. A feedback control circuit is connected to the voltage booster to compare first and second voltages, which are based on either one of an output voltage of the voltage booster and a reference voltage, with a third voltage, which is based on the other one of the output voltage and the reference voltage. The feedback control circuit generates a feedback signal based on the comparison to feedback control the voltage booster. The feedback control circuit maintains the feedback signal at a constant value when the third voltage is included between the first and second voltages.

Abstract: A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

Abstract: The demodulating device for a chrominance signal includes an oscillator with a controlled frequency, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor. The adjuster preferably includes a fine adjustment channel to output a first adjustment value that depends on the charge voltage of the memory capacitor, and a coarse adjustment channel to output a second adjustment value. The second adjustment value is modified when the charge voltage of the memory capacitor is not within a given range. The device is used, for example, in integrated SECAM decoders.

Abstract: A Time Based Correction (TBC) method for digital synchronization of video signals. The time based correction method may be used for satellite based communications to keep clocks synchronized in a multimedia system. Digital receiver clock phases are compared to measure synchronization. The method includes an initialization procedure (tbcInit) that initializes algorithm variables and sets up an initial phase; a measurement procedure (tbcGetPhase) that measures the current phase; and a tracking procedure (tbcAdjust) that makes periodic adjustments to the output clock (VO_CLOCK).

Abstract: A PLL circuit is provided with a lock/unlock detection circuit which detects the locked or unlocked state of the PLL circuit by comparing the phases of a horizontal synchronizing signal with each other and an internal synchronizing signal generating circuit which outputs the comparison signal as an internal synchronizing signal when the locked state is detected or outputs the horizontal synchronizing signal as an internal synchronizing signal when the unlocked state is detected. Another mode of a PLL circuit is provided with a skew detecting circuit which resets a frequency dividing circuit upon detecting a skew which is deviated from a normal period in an external synchronizing signal, generates a dummy pulse upon detecting that no skew occurs in the external synchronizing signal in the normal period, and generates a reference signal in combination of the dummy pulse with the external synchronizing signal. When the skew detection circuit detects a skew, the circuit also resets a phase comparator circuit.

Abstract: A PLL system includes a phase comparator, charge pump, LPF, VCO, 1/N frequency divider, CRT drive circuit, and arithmetic unit. The phase comparator compares the phase of an input horizontal sync signal with that of a comparison signal. The charge pump outputs a charge pump signal in accordance with the phase error signal output from the phase comparator. The LPF converts the charge pump signal from the charge pump into a voltage control signal. The VCO changes the oscillation frequency in accordance with the voltage control signal output from the LPF. The 1/N frequency divider performs 1/N frequency division of the frequency signal output from the voltage-controlled oscillator in accordance with a control signal. The CRT drive circuit performs deflection processing in a CRT on the basis of an output from the frequency divider and outputs, to the phase comparator, a comparison signal based on a reference signal for a display system which is generated by CRT deflection processing.

Abstract: An apparatus and method for synchronizing sampling of a video signal to a video synchronization signal of the video signal are provided. The frequency-divided output of an oscillator (or other controllable frequency source) is applied as one input to a phase detector, while the other input to the phase detector is supplied by the video synchronizing signals. The error signal voltage output of the phase detector is applied to correct the frequency, and thereby the phase, of the oscillator output through a dynamically-tuned phase-locked loop filter until the phases of the two input signals are in perfect agreement and no error voltage is produced. After a delay for this phase correction, during which time all video amplification is suspended, an output of the oscillator is then applied to sample the image without the presence of phase disparities while video amplification is restored. Full dynamic range digital acquisition then proceeds with extremely high accuracy at any desired resolution.

Abstract: A process of clock recovery during the sampling of computer-type signals, wherein the sampling clock is generated from a phase locked loop or PLL which multiplies a given frequency by an integer number, includes gauging the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the said signals in such a way as to obtain a first position-dependent value, carrying out a sampling clock phase correction and then carrying out a sampling clock frequency correction by using a processor.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A phase lock loop (PLL) circuit has an oscillation circuit operating in synchronism with a horizontal synchronizing signal. The PLL circuit also has a DC level decision circuit for deciding the DC level of a vertical synchronizing signal during a return period, and a logic circuit for automatically selecting the oscillation circuit according to the DC level decided in the DC level decision unit. Thus, even if there is an increase in the oscillation characteristics, this PLL circuit can automatically select the necessary oscillation characteristics without a need for expanding an operation frequency of a voltage controlled oscillation circuit.

Abstract: A video display apparatus displays pictures from broadcast sources of standard or high definition pictures and may also display computer generated images. To display these sources a horizontal deflection signal generator is operable at a plurality of frequencies. The deflection signal generator comprises a controlled oscillator generating a output signal. A divider divides the output signal to form a horizontal frequency signal. A phase detector receives the horizontal frequency signal and a synchronizing signal and generates an analog signal for coupling to the oscillator. A digital to analog converter generates a voltage from a digital data word and couples the voltage to the oscillator. The voltage determines a center frequency of the oscillator and the analog signal controls the oscillator to synchronize with the synchronizing signal.

Abstract: In a phase-locked loop circuit, a vertical synchronous separation circuit separates a vertical sync signal from a composite synchronizing signal to detect part of a vertical synchronizing period. A mask circuit masks the composite synchronizing signal during a predetermined period. A selector selects a reference signal or the composite synchronizing signal in accordance with the detection output from the vertical synchronous separation circuit. A phase comparator detects a phase difference between the output from the selector and the reference signal. A voltage-controlled oscillator changes an oscillation frequency upon receiving the output from the phase comparator through a low-pass filter. A counter counts the oscillation output from the voltage-controlled oscillator. A decoder circuit decodes the output from the counter to generate the reference signal, supplies it to the selector and the phase comparator, and resets the counter at a predetermined period.

Abstract: A method and apparatus for providing very small changes in the output oscillation of a controlled oscillation circuit, which may be used in a phase locked loop circuit, is accomplished by a phase-shifting controlled oscillator that includes an oscillation circuit and a selection circuit. The oscillation circuit generates a plurality of oscillations that are of approximately the same frequency and are approximately equally phase shifted from one another. The selection circuit is operably coupled to receive the plurality of oscillations and selects one of them to be the output oscillation based on a control signal. The very small change in the output oscillation occurs when the selection circuit, based on the control signal, selects another one of the oscillations to be the output oscillation. When the change happens, a single pulse is stretched by the phase difference between the “old” output oscillation and the “new” output oscillation.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A display apparatus for selecting a display mode, based on the horizontal and vertical synchronizing signals and an analog video signal supplied from a host with multiple display modes, includes a mode distinction circuit for generating first to third control signals according to a display mode received from the host, a clock signal generator for generating a pixel clock signal corresponding to the display mode in response to the first and second control signals and the horizontal synchronizing signal, a voltage controller for generating adjustment signals applied to the clock signal generator to adjust the phase and frequency of the pixel clock signal according to first/second voltages and the first/second control signals, and a switching circuit for supplying or cutting off the second control signal to the clock signal generator according to the third control signal being at a first level or a second level in response to the first voltage and the third control signal.

Abstract: An image data processing apparatus is described that prevents the period of a horizontal timing signal from being shifted. The apparatus includes a separator, a phase-locked loop, a detector, a compensator and a timing signal generator. The detector delays a reference clock signal in a shorter period than the period of the reference clock signal, in a step-like manner, to produce a plurality of delayed timing signals having step-like phase differences. The detector further contrasts the plurality of delayed timing signals with a horizontal sync signal and the reference clock signal to measure the phase difference and the period of the horizontal sync signal. The compensator sets a ratio for combining consecutive luminance data in accordance with the phase difference and the period of the reference clock signal and combines consecutive luminance data in accordance with the ratio to generate compensated luminance data.

Abstract: A vertical oscillation circuit includes a self raster discriminating circuit for selectively outputting a vertical sync signal and a vertical flyback signal; a vertical flyback pulse generator for determining the duty of the vertical flyback signal; a pulse level pull up for receiving the duty-determined pulse, thereby inverting its phase and shifting its level; a V-HOLD stage for receiving a vertical hold signal, and then outputting a pulse in accordance with a horizontal cycle; a vertical linearity stage for outputting a vertical linearity control signal; a vertical size control stage for outputting a vertical size control signal; a vertical oscillation stage for receiving a vertical hold control signal, vertical linearity control signal, and vertical size control signal respectively output from the V-HOLD stage, vertical linearity stage, and vertical size control stage, and generating a ramp pulse while controlled by the phase-inverted and potential level shifted pulse output from the pulse level pull up;

Abstract: A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected.

Abstract: A method and apparatus for controlling an output frequency of a phase locked loop is accomplished by determining a plurality of divider ratios which are based on an input frequency, parameters, and a desired output frequency. Each of the divider ratios is representative of a ratio between the output frequency and input frequency of the phase locked loop. Having determined the plurality of divider ratios, another determination is subsequently made to determine whether the plurality of divider ratios enable the phase locked loop to produce the output frequency within a given frequency tolerance, i.e., within an allowable error. The determination is based on whether changing the divider ratio from the one of the plurality of ratios to an adjacent ratio causes the output frequency to change more than the allowable error. If so, the plurality of ratios needs to be recalculated based on a change in the input frequency and/or one of the parameters.

Abstract: A circuit for detecting a data segment sync signal of data segment consisting of a plurality of symbols in a high-definition television, includes a correlator for detecting a correlation value from a received data segment signal, a segment integrator for accumulating the detected correlation value by segments and attenuating the accumulated correlation value in response to an overflow prevention signal, a maximum-value detector for detecting a maximum accumulated correlation value in the segment from the segment integrator output, an overflow prevention circuit for generating the overflow prevention signal by comparing the detected maximum accumulated correlation value with a predetermined reference value, a sync position detector for detecting a symbol position having the detected maximum accumulated correlation value, and a synchronization signal generator for generating a synchronization signal at the symbol position corresponding to the detected maximum accumulated correlation value.

Abstract: An arrangement for synchronizing a digitally generated color subcarrier signal to the color burst signal from another video signal, such as that from a video casette recorder or from a cable television signal, in a manner that allows a line locked clock to be used without causing unacceptable disturbance to the generated subcarrier signal.

Abstract: A frequency detection circuit detects the frequency of a horizontal sync signal, and generates a mode switching signal corresponding to the detected frequency. A voltage-controlled oscillator constituting a PLL circuit has a plurality of oscillation modes obtained by dividing a frequency equal to an integer multiple of the frequency of the horizontal sync signal into a plurality of frequency ranges, and oscillates signals in the respective frequency ranges in accordance with control voltages output from a filter. The oscillation modes of the voltage-controlled oscillator are switched in accordance with the mode switching signal output from the frequency detection circuit. In the voltage-controlled oscillator, since the frequency range in each oscillation mode is narrow, the oscillation gain can be suppressed low, and a deterioration in jitter characteristics can be prevented.

Abstract: A circuit for generating a clock of a predetermined frequency in folllowing-up relation to an input video signal, comprising a PLL circuit including a phase comparison circuit for comparing the phase of a synchronizing signal of the video signal with the phase of a feedback clock corresponding to the clock, and a control circuit for causing the feedback clock in the PLL circuit to be synchronized with the synchronizing signal.

Abstract: A horizontal lock detector circuit monitors charge pump control signals within a horizontal phase-lock loop to determine when the sampling pulses generated by the video system are locked in phase with the synchronization pulses of the input composite video signal. An output signal is generated by the lock detector circuit which is active when the sampling pulses are locked in phase with the input signal and inactive when the sampling pulses are not locked in phase with the input signal. The charge pump control signals are generated by a phase detector circuit within the phase-lock loop in response to a difference in phase between the sampling pulses and the input signal. Once the sampling pulses are locked in phase with the input signal, the charge pump control signals will become inactive. A current source is enabled when either of the charge pump control signals are active. The current source builds up a first level of charge on a first capacitor during the horizontal blanking period.

Abstract: A CRT display device capable of displaying a signal from the existing image signal source, in which a vertical frequency is approximately fixed and a horizontal frequency is widely distributed beyond a ratio of 3:1, on one image screen. The CRT display device includes a scan converter unit and a display unit. The scan converter unit includes an output horizontal frequency unifying circuit, a horizontal blanking period ratio converting circuit, a vertical frequency converting unit and a vertical blanking period ratio converting circuit. The display unit includes a vertical deflection circuit and a circuit for correcting a vertical S-shaped distortion. In a phase synchronous circuit, a lock-out detector is connected to an output of a three state output digital phase detector, and on the basis of an output thereof, a switch is subjected to the "ON"/"OFF" control.

Abstract: A digital phase error detector for locking to a color subcarrier signal in an analog video signal. The digital phase error detector includes a digitizer responsive to a sample clock which generates a first digital data stream from the analog video signal. Filtering circuitry filters the first digital data stream to generate a second data stream by substantially eliminating DC offset of the color subcarrier signal digitized by the digitizer. A mixer mixes the second digital data stream to generate a third digital data stream representing sum and difference frequencies of a product of the color subcarrier signal and a reference clock. An accumulator accumulates this product which represents a phase error between the color subcarrier signal and the reference clock. A voltage controlled oscillator is responsive to this phase error for generating the sample clock.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: An automatic adjustment circuit for an oscillator converts an output from a register into an analog signal by means of a D/A converter. An oscillation frequency of an oscillator is controlled by an output of the D/A converter. A first counter for counting an oscillation signal of the oscillator 1 resets itself and generates a pulse when a count reaches a predetermined value. A second counter counts a reference frequency pulse having a frequency substantially higher than the oscillation frequency of the oscillator. The second counter, on completion of counting a given preset value, changes an output level. The second counter is preset by said first counter when the first counter resets itself. Outputs from the first and the second counters are processed by an AND operation in an AND circuit. A third counter counts an output from the AND circuit, and provides a count output to the register.

Abstract: An FM signal phase-shifted by 90.degree. and an FM signal not phase-shifted are supplied to a multiplier to demodulate a stereo composite signal. A 90.degree. phase shifting circuit has a first oscillation circuit whose phase shift amount varies according to a timing at which the amount of a current flowing through a charging and discharging capacitor is changed. A multiplexer is provided to process the stereo composite signal to output left and right channel signals. The multiplexer has a second oscillation circuit for generating a signal multiplied by the stereo composite signal to extract the left and right channel signals from the composite signal. The first and second oscillation circuits each have a differential amplifier. The constant current of the constant current source of each differential amplifier is set by trimming-regulate it by a regulating circuit.