Abstract: A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.

Abstract: An electronic component has at least a first diode and a second diode that are capacitance diodes. The characteristic curve of the second diode has a fixed, known relationship to that of the first diode. For example, the first diode and the second diode can have an identical variation ratio, being the quotient of the maximum and minimum adjustable capacitances. These components are suitable for use in television tuners, for example in three-band tuners, where diodes having the same characteristic curve and coming from different components are arranged and connected in each sub-receiving unit. The integration of a plurality of diodes reduces the number of components required, and also the time and cost involved in grouping together diodes with good synchronization properties.

Abstract: A cover portion 20 which covers a spot-like light source 8 is provided on the printed circuit board (FPC) 9, thereby giving electrical insulation from the surrounding. Therefore, even if a metallic frame is disposed close to the spot-like light source 8, the spot-like light source 8 is prevented surely from shortcircuiting with the metallic frame. Since the cover portion 20 covers the surrounding of the spot-like light source 8, light leakage from the spot-light like source 8 can be minimized and light emitted from the spot-like light source 8 can be used efficiently.

Abstract: In addition to a first opening (11) forming a primary output from a waveguide cavity (10) of a microwave oscillator, a coupling aperture (12) in a reflective wall (32) provides a secondary output which does not degrade the performance or tuning characteristics of the source. Less than -20 dB of the source power may be coupled out via the aperture (12) and is used in a feed-back loop (12,21,23,24,36) with an harmonic mixer (21) and frequency discriminator (24) to stabilize the source. The mixer comprises a further waveguide section (15) separated from the source cavity (10) by the reflective wall (32). An advantageous mixer assembly comprises a circuit substrate which is mounted across the further waveguide cavity (15) and which carries an inductive probe by which the signal from the coupling aperture (12) is fed to an antiparallel pair of mixer diodes on the substrate. The whole assembly may be bolted together through holes (34).

Abstract: A phase and frequency detector circuit includes both a phase comparator such as an exclusive-OR gate possessing high phase sensitivity, and a frequency-phase comparator that is sensitive to differences in frequency. The outputs of these circuits are combined to provide a single output signal offering both frequency discrimination and sharp phase discrimination.

Abstract: A high-speed sample and hold phase detector for clock and data recovery systems is provided with a differentiating circuit coupled to a source of coded input data signals to provide bi-level differentiated output sampling pulses which are applied to a high-speed transformer. The output of the high-speed transformer is coupled to a high-speed fullwave diode bridge rectifying circuit whose output provides the error signal for the clock and data recovery circuit. The transformer is provided with a secondary winding having a center tap connected to a bi-level clock having clock signals whose rate is at twice the data rate. The D.C. error signal voltage amplitude is proportional to the phase difference between the clock signal connected to the center tap of the secondary winding of the transformer and the differentiated sampling pulses. The sampling pulses are employed to sample the clock signal which provides higher stability and enhances noise reduction.

Abstract: A phase-lock system including an oscillator providing a switching output that continuously switches between first and second states, a trigger circuit for inducing switching of the oscillator, a sensing circuit monitoring the switching output and providing an anticipating indication of an imminent switching thereof from the first to the second state, and a primary voltage source providing a variable voltage that periodically varies from and returns to a given voltage level. Also included is a detector circuit monitoring the variable voltage and detecting the presence of the given voltage level and a synchronizing circuit responsive to the sensing and detector circuits and providing an input to the trigger circuit, the synchronizing circuit being operative to cause switching of the oscillator in response to the simultaneous provision of the anticipating indication by the sensing circuit and detection of the given level by the detector circuit.

Abstract: A carrier oscillation in the microwave range is stabilized by a sequence of timing pulses produced by a crystal-controlled reference oscillator whose cadence is an aliquot fraction of the nominal carrier frequency. The pulses are used to obtain two phase-representing amplitude samples of the carrier wave from a pair of mutually phase-shifted pilot oscillations of the same frequency in each of a succession of nonconsecutive cycles thereof; a control voltage derived from these amplitude samples is fed back to the microwave oscillator via a frequency-correcting or phase-locking loop.

Abstract: A phase-locked loop circuit in which the phase offset error arising from imperfections in the balance of the phase comparator is reduced to a minimum by a special construction of the phase comparator. The quasi-static phase error of the loop is then reduced to very low values so that the loop is particularly suited for recovering the clock frequency from synchronous pulse signals having clock frequencies of several hundred MHz.