Abstract: A system for driving a microelectromechanical system (MEMS) oscillating structure includes a phase error detector configured to generate a phase error signal based on measured event times and expected event times of the MEMS oscillating structure oscillating about a rotation axis; a disturbance event detector configured to detect a disturbance event based on the phase error signal and a disturbance threshold value; and a phase frequency detector (PFD) and correction circuit configured to, in response to the detected disturbance event, monitor for a plurality of measured crossing events of the MEMS oscillating structure oscillating about the rotation axis, generate a first compensation signal based on at least a first measured crossing event and a second measured crossing event to correct a frequency of the MEMS oscillating structure, and generate a second compensation signal based on a third measured crossing event to correct a phase of the MEMS oscillating structure.

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

Abstract: A method and apparatus for modulating/demodulating an FSK signal capable of overcoming a trade-off relationship between a modulation index and a spectral efficiency are disclosed. An apparatus for modulating/demodulating a frequency deviation keying (FSK) signal includes a channel selection-modulator, a phase locked loop, and an output unit. The channel selection-modulator modulates an FSK signal by setting a frequency channel to be used. The phase locked loop generates a desired output frequency ‘fout’ compared to a reference frequency ‘fREF’ by adjusting a frequency division ratio (N+n) with respect to a frequency of the modulated FSK signal. The output unit amplifies the FSK signal having the generated output frequency ‘fout’ and radiating the amplified FSK signal through an antenna. Here, each of the frequency channels is divided into two or more tones, and different frequency channels are allocated between the tones divided into two or more tones.

Abstract: Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.

Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Abstract: Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.

Abstract: An oscillation circuit is provided. The oscillation circuit includes a first inverting circuit. The first inverting circuit comprises a first transistor of a first type and a second transistor of the first type, wherein a gate terminal of the first transistor is connected to a gate terminal of the second transistor, and a source terminal of the first transistor is connected to a drain terminal of the second transistor.

Abstract: Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal.

Abstract: Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

Abstract: A vibration actuator is capable of reducing differences in vibration phase and vibration amplitude without raising a voltage of a drive circuit when driving a contact member using a plurality of vibrators connected in series. The vibration actuator includes a vibrator device and a contact member that moves relative to the vibrator device. The vibrator device includes transformers of which primary coils are connected in series, and vibrators that are respectively connected in parallel to secondary coils of the transformers.

Abstract: A device includes a microwave generator configured to generate a microwave having a bandwidth, an output unit, a directional coupler and a measurer. The microwave generator generates a microwave a power of which is pulse-modulated to be a High level and a Low level. A set carrier pitch is set to satisfy a preset condition. The preset condition includes a condition that a value obtained by dividing a set pulse frequency by the set carrier pitch or a value obtained by dividing the set carrier pitch by the set pulse frequency is not an integer and a condition that an ON-time of the High level is equal to or larger than 50%. The microwave generator averages a first High measurement value and a first Low measurement value in a preset moving average time longer than a sum of the ON-time of the High level at a preset sampling interval.

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

Abstract: Ina power conversion system having a fixed pulse pattern modulation unit 2 that is configured to refer to tables storing therein pulse patterns that determine respective command voltage levels corresponding to phase information for each modulation ratio and to generate a gate signal g on the basis of a command modulation ratio d and a control phase ? and driving a power converter 3 on the basis of the gate signal g, the fixed pulse pattern modulation unit 2 is further configured to, when performing a pulse pattern transition, search for a proper post-transition table reference position and make a command voltage level follow a command voltage level of a post-transition pulse pattern. With this, the power conversion system that can perform the pulse pattern transition without current impulse and that can also be applied to a multi-level power converter having four levels or more can be provided.

Abstract: A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.

Abstract: A power supply control system includes a power generator for providing a signal to a load. The power generator includes a power controller controlling a power amplifier. The power generator includes an adaptive controller for varying the output signal controlling the power amplifier. The adaptive controller compares an error between a measured output and a predicted output to determine adaptive values applied to the power controller. The power generator also includes a sensor that generates an output signal that is digitized and processed. The sensor signal is mixed with a constant K. The constant K is varied to vary the processing of the sensor output signal. The value K may be commutated based on the phase, frequency, or both phase and frequency, and the bandwidth of K is determined by coupled power in the sensor output signal.

Abstract: Disclosed in the present application are a method for reducing SGLTE coupling de-sense and a mobile terminal, the method including: filtering out an LTE network frequency band in a signal transmitted by a signal transmission end of a GSM; and filtering out a network frequency band in a signal of a signal reception end accessing the GSM other than a GSM network frequency band. Employing the present application may eliminate mutual interference between a GSM signal and an LTE signal due to the GSM network frequency band and the LTE network frequency band getting too close to each other, which greatly alleviates SGLTE mobile terminal coupling de-sense situation.

Abstract: In 5G and 6G, each message element of a message is transmitted with a constant amplitude level. Disclosed herein is a more resource-efficient modulation scheme in which each message element is modulated to two of the amplitude levels, with a first amplitude level in the first half of a message element, and a second amplitude level in the second half. The information density of the message is thereby doubled, saving time and resources. The transition between the first and second amplitude levels can be abrupt, as in a square wave, or ramped, as in a linear ramp function. The changing amplitude may cause a frequency shift; however the transmitter can calculate that shift and apply a frequency correction to each message element to compensate. The changing amplitude can also deposit energy in adjacent subcarriers; however the receiver can calculate that energy and subtract it from the adjacent subcarriers before demodulating.

Abstract: The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL (500) comprising: a phase comparison module (201); a loop filter (102); a voltage controller oscillator, VCO (103); a feedback divider (104); and a jitter evaluation module (502), the phase comparison module (201) comprising a phase comparator (202) and a measurement module (204) configured to detect a metastable output in the phase comparator (202) over active clock cycles of application and feedback clock signals (105, 106) input to the phase comparison module (201) and provide an output signal (208) to the jitter evaluation module (502) indicating a metastability resolution time for the phase comparator (202), the jitter evaluation module (210) being configured to provide an output indicative of jitter based on the metastability resolution time.

Abstract: Example systems and processes control transition of an electric motor from open-loop operation to closed-loop operation by detecting zero-crossing (ZC) locations of the back-electromotive force (BEMF). The rotor angle of the electric motor is changed, e.g., by changing acceleration of the electric motor to correct a phase difference based on the detected ZC locations and an open-loop profile of the electric motor. Detected ZC locations may be used to identify ZC-detected-based commutation points, and each detected ZC location may be used to update a next commutation point. During the control process the open-loop profile is updated. Transition may occur when a set number of ZC-detection-based commutation points are sufficiently aligned with corresponding updated commutation points, or such alignment is maintained for at least one electrical cycle.

Abstract: To improve power converter ON-time generation, an example apparatus includes: a phase frequency detector to determine a phase difference between a first signal and a second signal; a first pulse generator to generate a first time signal at a second time, in which the first signal is associated with a first time delay based on the phase difference; and a second pulse generator coupled to the first pulse generator. The second pulse generator is configured to: generate a second time signal at a third time, in which the third time is after the second time; and obtain a digital word based on the phase difference at a first time, in which the first time is before the second time and the third time, and the second time signal is associated with a second time delay based on the phase difference.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.

Abstract: An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Abstract: An electronic circuit and a method of making the same includes a multiplier circuit configured to perform a multiplication of a first input signal with a second input signal. The first input signal is a binary input signal that includes a sequence of input bits. The electronic circuit further includes an oscillator circuit configured to receive a result signal of the multiplication from the multiplier and to provide output pulses having an output frequency which is dependent on the result signal of the multiplication and a digital counter circuit configured to count the output pulses. The digital counter circuit is configured to provide a plurality of counter bits and to select one of the plurality of counter bits for incrementation in dependence on a significance of the corresponding input bit of the sequence of input bits.

Abstract: System and methods implemented in a coherent receiver having a pair of Avalanche Photodiodes (APD) include adjusting one or more of a reverse bias voltage (VAPD) on a P-path (VAPDP) and on an N-path (VAPDN) responsive to an output (PIN,CM) that indicates electrical power of an AC common-mode input signal; adjusting a Transimpedance Amplifier (TIA) common-mode AC response, AdjCM_AC_Response, responsive to an output (POUT,CM) that indicates electrical power of an AC common-mode output signal; and/or adjusting one or more of VAPDP and VAPDN responsive to received signal Signal-to-Noise Ratio (SNR).

Abstract: A half rate bang—bang phase detector for high-speed Analog Clock and Data Recovery (CDR) is disclosed. In some embodiments, the half rate bang—bang phase detector includes a first set of flip flops. Each of the first set of flip flops is configured to receive an input data sampled at each of a four phases of a Voltage Controlled Oscillator (VCO) clock. The half rate bang—bang phase detector includes a first set of logic gates configured to generate a set of four exclusive—OR (XOR) outputs. The half rate bang—bang phase detector includes a second set of flip flops configured to generate a set of clean XOR outputs. The half rate bang—bang phase detector includes a second set of logic gates configured to generate a set of final outputs based on the set of clean XOR outputs.

Abstract: A memory system includes a plurality of memory devices coupled to each other through a channel and each including a test clock input pad suitable for receiving an external test clock, a clock generation circuit suitable for generating an input clock and an output clock based on a reference clock and the external test clock in response to a reset signal, a test data processing circuit suitable for parallelizing test data so as to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock, and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock.

Abstract: A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

Abstract: A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source.

Abstract: A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Abstract: A frequency synthesiser arrangement is arranged to receive a clock input signal and provide an output signal. The frequency synthesiser arrangement comprises: a frequency divider arranged to divide the output signal by a variable number N and output a feedback signal; a phase detector arranged to detect a phase difference between the feedback signal and the clock input signal; a phase alignment circuit portion arranged to determine an overlap of the clock input signal and the feedback signal; and a voltage controlled oscillator which is arranged to receive either a first input derived from the phase detector or a second input from an external reference voltage and to provide the output signal. The phase alignment circuit portion is arranged to provide a control output which determines whether the voltage controlled oscillator receives the first or second input.

Abstract: A magnetic field sensor includes a phase-locked loop to receive a measured magnetic field signal formed from sensing element output signals of a plurality of magnetic field sensing elements in response to a magnetic field. The phase-locked loop is configured to generate an angle signal having a value indicative of the angle of the magnetic field. Associated methods are also described.

Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Abstract: A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load.

Abstract: A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

Abstract: Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.

Abstract: A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.

Abstract: A method is provided for operating an electrical device (14) which has an operating mode and a sleep mode, in which method an oscillator apparatus (20) provides a first analog signal (f(t)) with a first frequency and second analog signal (f?(t)) with a second frequency, wherein the second analog signal (f?(t)) is different from the first analog signal (f(t)), a comparator apparatus (28) compares the first analog signal (f(t)) and/or second analog signal (f?(t)) with at least one reference value (Uref) or a reference value range, and an interrupt signal for transferring from the sleep mode into the operating mode is produced if a certain comparison result is detected.

Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

Abstract: A tunable voltage oscillator expands a voltage oscillator's tuning range and compensate for any frequency spread present in the voltage oscillator. The tunable voltage oscillator multiplies a frequency of a periodic signal generated by the voltage oscillator by a fractional number. This fractional number is determined by a desired frequency range and an actual frequency range of the voltage oscillator. As such, the frequency range of the output periodic signal is tuned into the desired range. The voltage oscillator can include a programmable inductor of which the inductance can be adjusted thereby to expand the frequency range by increasing the quality factor in the low frequency range.

Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may report a phase-noise compensation reference signal (PCRS) configuration to a base station to enable per-UE PCRS signaling. For example, a UE may operate in a wireless communications system using carrier frequencies greater than 6 GHz, which may be affected by phase noise. The UE may accordingly determine a PCRS configuration based on a capability to receive signals. The PCRS configuration may include a resource mapping for one or more PCRS, a number of PCRS ports used for PCRS, a multiplexing scheme for one or more PCRS ports, or the UE's phase noise estimation capability. The UE may then transmit a reporting message including the PCRS configuration to a base station. The base station may use the PCRS configuration for PCRS transmissions to the UE.

Abstract: An integrated circuit. The integrated circuit comprises an analog transmit chain, an analog receive chain, a processor coupled to the analog transmit and receive chains, and a non-transitory storage coupled to the processor and storing executable code. When executed by the processor, the executable code causes the processor to cause a portion of a radio frequency (RF) signal to be transmitted by the analog transmit chain, to determine a first direct current (DC) voltage of a baseband signal provided by the analog receive chain, to cause a DC voltage offset to be input into the analog transmit chain, to determine a second DC voltage of another baseband signal provided by the analog receive chain, to determine a DC voltage offset compensation based on the first and second DC voltages and the DC voltage offset, and to cause the DC voltage offset compensation to be used to transmit signals.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.