Signal Or Phase Comparator Patents (Class 331/25)
  • Patent number: 11953543
    Abstract: A measurement device and method for testing a device under test (DUT). The device includes an input terminal for receiving a RF signal from the DUT; at least one analog-to-digital (A/D) converter configured to generate a digital data including a plurality of sampled signals from the received RF signal; at least one filter configured to filter the digital data generated by the at least one A/D converter based on an intermediate-frequency bandwidth (IFBW) set in the at least one filter; a detector configured to analyse the filtered digital data based on a pre-set number of samples from the filtered digital data; and a controller configured to calculate a signal-to-noise ratio (SNR) value of the analysed filtered digital data, and to adjust at least one of the IFBW of the at least one filter and the number of samples of the detector based on the calculated SNR value.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: April 9, 2024
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Mert Celik, Adam Tankielun
  • Patent number: 11947031
    Abstract: A radar transceiver includes a receiver. The receiver includes a low noise amplifier a mixer, a baseband filter, an integrator, and a phase shifter. The mixer includes an input coupled to an output of the low noise amplifier. The baseband filter includes an input coupled to an output of the mixer. The integrator includes an input coupled to an output of the baseband filter. The phase shifter includes a control input and an output. The control input is coupled to an output of the integrator.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sreekiran Samala, Venkatesh Srinivasan, Vijaya B. Rentala
  • Patent number: 11936390
    Abstract: Disclosed is a low-power fractional-N phase-locked loop circuit, which comprises a phase detector, a voltage-to-current converter, a loop filter, a voltage-controlled oscillator, a frequency divider and a digital logic processor; the phase detector, the voltage-to-current converter, the loop filter, the voltage-controlled oscillator and the frequency divider are connected in sequence; a reference signal is input from the phase detector, the phase detector detects the phases of the reference signal and a feedback signal with a quantization error output by the frequency divider, compensates a quantization phase error generated by fractional frequency division, and outputs a compensated phase detection result to the voltage-to-current converter; the quantization error generated by fractional frequency division is converted into a voltage domain through a digital domain or directly coupled to a phase error signal in the phase detector to complete the compensation of the quantization error.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: March 19, 2024
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Xiang Gao, Gaofeng Jin, Fei Feng
  • Patent number: 11936868
    Abstract: An image is split into a plurality of blocks of various sizes and a subdivision level counter is associated to each of the blocks. The value of this subdivision level counter for a block is representative of the size of the block and is used to determine the quantization parameter for the block. The value is propagated for each subdivision and incremented according the type of the subdivision. When the image is split, an analysis is done according to the subdivision level counter, a maximal value of subdivision and the type of split, in order to determine the start of a new quantization group and when it is the case, the current position of the partition is propagated to the further split partitions to be stored with these partition and serve in the prediction process when decoding.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 19, 2024
    Assignee: InterDigital VC Holdings, Inc.
    Inventors: Philippe De Lagrange, Philippe Bordes, Edouard Francois
  • Patent number: 11929745
    Abstract: A clock generator includes a resistor-capacitor-based voltage-controlled oscillator (RC-based VCO) that generates an output signal with oscillation frequency controlled by an input voltage at an input node; and a temperature compensator that generates the input voltage to compensate change of the oscillation frequency associated with a change in temperature.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: March 12, 2024
    Assignee: Himax Technologies Limited
    Inventors: Yu-Shyang Huang, Sheng-Zhe Lin
  • Patent number: 11914820
    Abstract: A processing system including an amplifier configured to generate, from multiple spatial-common-mode-processed signals, a spatial common mode estimate and multiple feedback signals. The processing system includes multiple charge integrators configured to obtain resulting signals from the capacitive sensor electrodes, each of the resulting signals including a spatial common mode component and a residual noise component. The charge integrators generate multiple spatial-common-mode-processed signals by mitigating the spatial common mode component and the residual noise component in the resulting signals using the feedback signals. The processing system includes a programmable gain amplifier configured to determine the spatial common mode estimate.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: February 27, 2024
    Assignee: Synaptics Incorporated
    Inventors: Chunbo Liu, Mihai Bulea
  • Patent number: 11916559
    Abstract: A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: February 27, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Fahim Ur Rahman, Jinuk Shin
  • Patent number: 11909409
    Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Faraday Technology Corp.
    Inventor: Vinod Kumar Jain
  • Patent number: 11894850
    Abstract: The present disclosure provides a delay circuit and a semiconductor device. The delay circuit includes a delay unit and a linear voltage regulator unit; wherein, the delay unit includes an inverting unit and a power supply control unit, and the inverting unit includes an inverting unit and a power supply control unit. The inversion unit receives an input signal and delays the input signal, and the power supply control unit is used for providing a voltage to the inverting unit according to the power supply control signal; the linear voltage stabilization unit is coupled to the delay unit and outputting the power supply control signal according to a reference voltage. The voltage outputs the power control signal. The present disclosure can accurately control the delay time of the delay unit and improve the delay precision of the delay circuit.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xinxin Zhang, Jianyong Qin
  • Patent number: 11881858
    Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai Tian, Yuxia Wang
  • Patent number: 11843379
    Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: December 12, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Tien-Hsing Yao, Chun-Cheng Lee, Sheng-I Hsu
  • Patent number: 11838028
    Abstract: The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: December 5, 2023
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: SeongHwan Cho, Junseok Hong, Pangi Park
  • Patent number: 11824527
    Abstract: An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 21, 2023
    Assignee: AMS AG
    Inventors: Jeffrey Smith, Pawel Chojecki
  • Patent number: 11824548
    Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 21, 2023
    Assignee: XILINX, INC.
    Inventors: Shaojun Ma, Chi Fung Poon
  • Patent number: 11817871
    Abstract: Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: November 14, 2023
    Assignee: Anritsu Company
    Inventor: Oleksandr Chenakin
  • Patent number: 11774551
    Abstract: A method for compensating for noise in a secondary radar system is described. The method includes, using a first transceiver, transmitting, in temporally overlapping manner, a first transmission signal containing a first interfering component and a second transmission signal containing a second interfering component, and compensating for at least one of phase shifts or frequency shifts resulting from the first and second interfering components by evaluation of the first and second transmission signals.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 3, 2023
    Assignee: Symeo GmbH
    Inventors: Martin Vossiek, Peter Gulden, Michael Gottinger
  • Patent number: 11777701
    Abstract: A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: October 3, 2023
    Assignee: SOCIONEXT INC.
    Inventor: Masatoshi Tsuge
  • Patent number: 11775004
    Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Jason Lee Frankel, Chad Andrew Marquart, Ching Lung Tong, Lily Jielu Zhang
  • Patent number: 11770124
    Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: September 26, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Jose Luis Flores, Venkateswar Reddy Kowkutla, Ramakrishnan Venkatasubramanian
  • Patent number: 11757612
    Abstract: A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: David F. Heinrich, Gennadiy Rozenberg, Scott P. Faasse, Melvin K. Benedict
  • Patent number: 11754011
    Abstract: An injection control device includes: a boost controller performing a boost switching control of a boost switch to charge a boost capacitor and supplying a boost power from a battery power supply; a boost voltage monitor monitoring the boost voltage; and a boost monitor timing controller setting a section from a predetermined time after an on-edge of the boost switch to an off-edge timing in a section monitor mode as a boost monitor section. The boost controller stops boosting by stopping the boost switching control when the boost voltage is equal to or higher than a boost stop threshold value in the boost monitor section.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: September 12, 2023
    Assignee: DENSO CORPORATION
    Inventors: Masashi Inaba, Yusuke Shimizu, Hiroki Kakui
  • Patent number: 11757346
    Abstract: An embodiment circuit comprises first and second output nodes with an inductor arranged therebetween, and first and second switches coupled to opposed ends of the inductor. The switches are switchable between non-conductive and conductive states to control current flow through the inductor and produce first and second output voltages. The current intensity through the inductor is compared with at least one reference value. Switching control circuitry is coupled with the first and second switches, the first and second output nodes, and current sensing circuitry, which is configured to control the switching frequency of the first and second switches as a function of the output voltages and a comparison at the current sensing circuitry. The switching control circuitry is configured to apply FLL-FFWD processing to produce the reference values as a function of a timing signal, targeting maintaining a constant target value for the converter switching frequency.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: September 12, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Maurizio Ricci, Marco Sautto, Simone Bellisai, Eleonora Chiaramonte, Luigi Arpini, Davide Betta
  • Patent number: 11750200
    Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 5, 2023
    Assignee: ZTE CORPORATION
    Inventors: Jun Liu, Zhaobi Wei, Shan Wang, Pei Duan, Mengbi Lei
  • Patent number: 11742842
    Abstract: A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: August 29, 2023
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Yongqi Zhou, Yang Chen
  • Patent number: 11742834
    Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: August 29, 2023
    Assignee: NXP B.V.
    Inventors: Sander Derksen, Jos Verlinden, Ids Christiaan Keekstra, René Verlinden
  • Patent number: 11742866
    Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: August 29, 2023
    Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianbo Liu, Weibin Ma, Lihong Huang, Zuoxing Yang, Haifeng Guo
  • Patent number: 11733348
    Abstract: Phase noise compensation can be performed in a primary radar system, such as in transceiver hardware. A first reflected reception signal can be received, corresponding to a reflection of a first transmission signal from an object, and a first measurement signal can be generated using mixing or correlation of the first reflected reception signal and the first transmission signal. A second measurement signal can be similarly generated from a second transmission signal and a second reflected reception signal. The first and second measurement signals include respective components including complex conjugate representations of each other. The components correspond to interfering components associated with phase noise, and such respective components can cancel each other to suppress phase noise.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 22, 2023
    Assignee: Symeo GmbH
    Inventors: Martin Vossiek, Michael Gottinger, Peter Gulden
  • Patent number: 11728816
    Abstract: A PLL circuit includes: a charge pump; a voltage-controlled oscillator including an oscillation portion; and a voltage-converting circuit configured to convert a voltage from the charge pump and apply the converted voltage to the voltage-controlled oscillator. The power supply range supplied to the voltage-converting circuit is larger than the power supply range supplied to the oscillation portion of the voltage-controlled oscillator.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: August 15, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masaaki Iwane
  • Patent number: 11705907
    Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 18, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Tien-Hsing Yao, Chun-Cheng Lee, Sheng-I Hsu
  • Patent number: 11705910
    Abstract: Methods and apparatus for quickly changing line rates in PCIe analyzers without resetting the receivers. One example circuit for multi-rate reception generally includes: a receiver having a data input, a data output, and a clock input configured to receive a clock signal from a clock generator, the receiver being configured to switch between receiving data at a first data rate and at least one second data rate and to sample data according to the first data rate, wherein the first data rate is higher than the at least one second data rate; a phase detector having an input coupled to the data output of the receiver; and a filter having an input coupled to an output of the phase detector and having an output configured to effectively control a phase of the sampling by the receiver when the data is at the at least one second data rate.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: July 18, 2023
    Assignee: XILINX, INC.
    Inventor: Paolo Novellini
  • Patent number: 11705913
    Abstract: A method for controlling a phase-locked loop circuit, can include: acquiring values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to desired values of a frequency control word signal and acquiring values of a charge pump current control signal respectively corresponding to the desired values of the frequency control word signal in a calibration mode, where the frequency control word signal characterizes a ratio of a desired locked frequency to a frequency of a reference signal; and determining a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the frequency control word signal in a phase-locked mode, in order to control the phase-locked loop circuit to achieve phase lock.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 18, 2023
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Yan Ye, Cheng Liang
  • Patent number: 11671105
    Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: June 6, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Abhishek Bhat, Romesh Kumar Nandwana, Kadaba Lakshmikumar, Pavan Kumar Hanumolu
  • Patent number: 11665032
    Abstract: A method and apparatus for modulating/demodulating an FSK signal capable of overcoming a trade-off relationship between a modulation index and a spectral efficiency are disclosed. An apparatus for modulating/demodulating a frequency deviation keying (FSK) signal includes a channel selection-modulator, a phase locked loop, and an output unit. The channel selection-modulator modulates an FSK signal by setting a frequency channel to be used. The phase locked loop generates a desired output frequency ‘fout’ compared to a reference frequency ‘fREF’ by adjusting a frequency division ratio (N+n) with respect to a frequency of the modulated FSK signal. The output unit amplifies the FSK signal having the generated output frequency ‘fout’ and radiating the amplified FSK signal through an antenna. Here, each of the frequency channels is divided into two or more tones, and different frequency channels are allocated between the tones divided into two or more tones.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 30, 2023
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sang-Gug Lee, Eui-Rim Jeong, Jinho Ko, Keun-Mok Kim
  • Patent number: 11662765
    Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: May 30, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Mahalingam Nagarajan, Vaishnav Srinivas, Christophe Avoinne, Xavier Loic Leloup, Michael David Jager
  • Patent number: 11664811
    Abstract: A system for driving a microelectromechanical system (MEMS) oscillating structure includes a phase error detector configured to generate a phase error signal based on measured event times and expected event times of the MEMS oscillating structure oscillating about a rotation axis; a disturbance event detector configured to detect a disturbance event based on the phase error signal and a disturbance threshold value; and a phase frequency detector (PFD) and correction circuit configured to, in response to the detected disturbance event, monitor for a plurality of measured crossing events of the MEMS oscillating structure oscillating about the rotation axis, generate a first compensation signal based on at least a first measured crossing event and a second measured crossing event to correct a frequency of the MEMS oscillating structure, and generate a second compensation signal based on a third measured crossing event to correct a phase of the MEMS oscillating structure.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 30, 2023
    Assignee: Infineon Technologies AG
    Inventors: Philipp Stelzer, Norbert Druml, Christian Steger, Andreas Strasser
  • Patent number: 11652489
    Abstract: Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 16, 2023
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Justin L. Fortier, Benjamin Philip Walker
  • Patent number: 11644884
    Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: May 9, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Mrudula Gore
  • Patent number: 11632228
    Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungpil Lim, Kyungho Ryu, Kilhoon Lee, Hyunwook Lim
  • Patent number: 11621715
    Abstract: Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 4, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Robin Gupta, Abishek Manian
  • Patent number: 11606084
    Abstract: An oscillation circuit is provided. The oscillation circuit includes a first inverting circuit. The first inverting circuit comprises a first transistor of a first type and a second transistor of the first type, wherein a gate terminal of the first transistor is connected to a gate terminal of the second transistor, and a source terminal of the first transistor is connected to a drain terminal of the second transistor.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Shun Chen, Chih-Chiang Chang, Yung-Chow Peng
  • Patent number: 11595050
    Abstract: Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen
  • Patent number: 11595051
    Abstract: Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 28, 2023
    Assignee: MAXIO TECHNOLOGY (HANGZHOU) CO., LTD.
    Inventors: Tengxiao Jiang, Zhiyu Zhuang, Yiren Huang
  • Patent number: 11588417
    Abstract: A vibration actuator is capable of reducing differences in vibration phase and vibration amplitude without raising a voltage of a drive circuit when driving a contact member using a plurality of vibrators connected in series. The vibration actuator includes a vibrator device and a contact member that moves relative to the vibrator device. The vibrator device includes transformers of which primary coils are connected in series, and vibrators that are respectively connected in parallel to secondary coils of the transformers.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: February 21, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenichi Kataoka
  • Patent number: 11587769
    Abstract: A device includes a microwave generator configured to generate a microwave having a bandwidth, an output unit, a directional coupler and a measurer. The microwave generator generates a microwave a power of which is pulse-modulated to be a High level and a Low level. A set carrier pitch is set to satisfy a preset condition. The preset condition includes a condition that a value obtained by dividing a set pulse frequency by the set carrier pitch or a value obtained by dividing the set carrier pitch by the set pulse frequency is not an integer and a condition that an ON-time of the High level is equal to or larger than 50%. The microwave generator averages a first High measurement value and a first Low measurement value in a preset moving average time longer than a sum of the ON-time of the High level at a preset sampling interval.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 21, 2023
    Assignees: TOKYO ELECTRON LIMITED, TOKYO KEIKI INC.
    Inventors: Yohei Ishida, Kazushi Kaneko, Hajime Tamura, Koichi Murai
  • Patent number: 11568916
    Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hundae Choi, Garam Choi
  • Patent number: 11563367
    Abstract: Ina power conversion system having a fixed pulse pattern modulation unit 2 that is configured to refer to tables storing therein pulse patterns that determine respective command voltage levels corresponding to phase information for each modulation ratio and to generate a gate signal g on the basis of a command modulation ratio d and a control phase ? and driving a power converter 3 on the basis of the gate signal g, the fixed pulse pattern modulation unit 2 is further configured to, when performing a pulse pattern transition, search for a proper post-transition table reference position and make a command voltage level follow a command voltage level of a post-transition pulse pattern. With this, the power conversion system that can perform the pulse pattern transition without current impulse and that can also be applied to a multi-level power converter having four levels or more can be provided.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: January 24, 2023
    Assignee: MEIDENSHA CORPORATION
    Inventors: Ryuichi Ogawa, Masashi Takiguchi
  • Patent number: 11562796
    Abstract: A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 24, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroo Yabe
  • Patent number: 11531312
    Abstract: A power supply control system includes a power generator for providing a signal to a load. The power generator includes a power controller controlling a power amplifier. The power generator includes an adaptive controller for varying the output signal controlling the power amplifier. The adaptive controller compares an error between a measured output and a predicted output to determine adaptive values applied to the power controller. The power generator also includes a sensor that generates an output signal that is digitized and processed. The sensor signal is mixed with a constant K. The constant K is varied to vary the processing of the sensor output signal. The value K may be commutated based on the phase, frequency, or both phase and frequency, and the bandwidth of K is determined by coupled power in the sensor output signal.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 20, 2022
    Assignee: MKS Instruments, Inc.
    Inventors: David J. Coumou, Yuriy Elner, Aung Toe, Daniel M. Gill, Eldridge M. Mount, IV, Shaun Smith
  • Patent number: 11522569
    Abstract: Disclosed in the present application are a method for reducing SGLTE coupling de-sense and a mobile terminal, the method including: filtering out an LTE network frequency band in a signal transmitted by a signal transmission end of a GSM; and filtering out a network frequency band in a signal of a signal reception end accessing the GSM other than a GSM network frequency band. Employing the present application may eliminate mutual interference between a GSM signal and an LTE signal due to the GSM network frequency band and the LTE network frequency band getting too close to each other, which greatly alleviates SGLTE mobile terminal coupling de-sense situation.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 6, 2022
    Assignee: HuiZhou TCL Mobile Communication Co., Ltd.
    Inventors: Sheng Zhang, Zhihao Zheng
  • Patent number: RE49526
    Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 9, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Patrick Vandenameele, Norman Beamish