Signal Or Phase Comparator Patents (Class 331/25)
  • Patent number: 10110409
    Abstract: A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 23, 2018
    Assignee: IQ-Analog Corporation
    Inventors: Michael Kappes, Steven R. Norsworthy
  • Patent number: 10001549
    Abstract: A method for determining the functionality of a switchable reception amplifier of a radar system with a transmitting unit, a receiving unit and a voltage-controlled oscillator, wherein, before the radar system is started up, calibration is carried out in order to compensate for a frequency deviation of the frequency emitted by the oscillator. The invention provides for at least one calibration cycle to be run with at least one first signal at a first frequency and one second signal at a second frequency during calibration of the oscillator, wherein the first signal and the second signal are transmitted by the transmitting unit and are received by the receiving unit, wherein the reception amplifier is switched with a switching sequence, which results in amplitude modulation of the first and second signals, and the amplitude modulation is used to determine the functionality of the reception amplifier.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: June 19, 2018
    Assignee: Hella KGaA Hueck & Co.
    Inventor: Thomas Hesse
  • Patent number: 9979582
    Abstract: A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 22, 2018
    Assignee: IQ-Analog Corp.
    Inventors: Michael Kappes, Steven R. Norsworthy
  • Patent number: 9967086
    Abstract: A frequency modulation receiver includes a frequency modulation demodulation circuit that generates a first signal, and a phase locked loop (PLL) circuit coupled to the frequency modulation demodulation circuit to receive the first signal. The PLL circuit includes: a voltage-controlled oscillator (VCO), generating an oscillation output signal according to a filtered output signal; a phase detector, coupled to the VCO, generating a phase signal according to the oscillation output signal and the first signal; and a proportional-integral-derivative (PID) filter, coupled to the VCO and the phase detector, receiving the phase signal and generating the filtered output signal to the VCO.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 8, 2018
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yu-Che Su, Kuan-Chou Lee, Tai-Lai Tung
  • Patent number: 9927831
    Abstract: A clock calibration method of a navigation system is provided. The clock calibration method includes: entering a calibration mode; sequentially issuing, by a host, a count start signal and a count end signal separated by a time interval; counting a local oscillation frequency of a local oscillator when a navigation device receives the count start signal from the host; disabling the counting when the navigation device receives the count end signal from the host and generating a current count; generating a calibration signal according to the current count and a predetermined count corresponding to the time interval; and calibrating the local oscillation frequency of the local oscillator according to the calibration signal.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: March 27, 2018
    Assignee: PixArt Imaging Inc.
    Inventors: Kevin Len-Li Lim, Zi-Hao Tan
  • Patent number: 9929818
    Abstract: Methods and systems are described for communication of data over a communications bus at high speed and high pin efficiency, with good resilience to common mode and other noise. Pin efficiencies of 100% may be achieved even for bus widths of four or fewer wires. Information to be transmitted is encoded as words of a vector signaling code, each word comprising multiple values transmitted as a group over the communications bus. Subsets of the vector signaling code have distinct group characteristics, which are discernable on transmission and are used to facilitate decoding on reception.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: March 27, 2018
    Assignee: KANDOU BUS, S.A.
    Inventors: Brian Holden, Amin Shokrollahi
  • Patent number: 9915968
    Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Virendra Bansal, Manoj Mehrotra, Keith Alan Bowman
  • Patent number: 9887667
    Abstract: There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: February 6, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Ian Juso Dedic, David Timothy Enright
  • Patent number: 9865989
    Abstract: A method includes modulating a laser that is coupled to a fiber; modulating the laser with a member selected from the group consisting of low frequency thermal modulation or bias modulation to broaden a laser linewidth, increase an SBS threshold and reduce an IIN; and modulating the laser with a predistorting modulation selected from the group consisting of phase modulation or amplitude modulation, the predistorting modulation being of equal magnitude but opposite phase as that produced in at least one member selected from the group consisting of the laser or the fiber as a result of the low frequency thermal modulation or bias modulation.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: January 9, 2018
    Assignee: ARRIS Enterprises LLC
    Inventor: Brian Ishaug
  • Patent number: 9762253
    Abstract: A reference frequency calibration module is provided. The reference frequency calibration module includes an oscillator, a frequency divider, a phase-locked loop (PLL) and a frequency-offset calibration unit. The frequency divider couples to the oscillator. The phase-locked loop couples to the frequency divider. The frequency-offset calibration unit couples to the frequency divider and the phase-locked loop. The oscillator is configured for operatively generating an oscillating signal having an oscillating frequency. The frequency divider divides the oscillating signal having the oscillating frequency by a first division parameter to generate a first clock signal having a first reference frequency. The phase-locked loop generates a second clock signal having a second reference frequency according to the first clock signal. The frequency-offset calibration unit is configured for operatively generating the first division parameter according to the second clock signal.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: September 12, 2017
    Assignee: C-MEDIA ELECTRONICS INC.
    Inventors: Chih-Ying Huang, Po-Shu Lan
  • Patent number: 9742549
    Abstract: Apparatus and methods for asynchronous clock mapping are provided herein. In certain configurations, an upstream server of a transport network generates clock difference data indicating a time difference between a server clock signal and a client clock signal, which have an asynchronous timing relationship with respect to one another. The clock difference data is generated with high precision by using one or more time-to-digital converters (TDCs). The clock difference data is included in a transmitted data stream, and is used by a downstream server to recover client information with enhanced accuracy.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 22, 2017
    Assignee: Analog Devices Global
    Inventors: Yi Wang, Yiming Zhao, Xiaopeng Song
  • Patent number: 9685983
    Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 20, 2017
    Assignee: Maxlinear, Inc.
    Inventors: Subramanian Anantharaman Chandrasekarapuram, Anand Anandakumar, Stephane Laurent-Michel, Sheng Ye, Raja Pullela, Glenn Chang, Vamsi Paidi
  • Patent number: 9660638
    Abstract: A power switch control circuit is provided for power management in one-wire application. The circuit comprises a controllable switch coupled between an input node and an internal power node. A comparator is utilized for power loss sensing to close the switch when necessary to minimize the power loss while the input is low or floating. A watchdog circuit is incorporated within the control circuit to pull down the input node periodically to detect small leakage current when the input node is floating.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Shiau Chwun George Pwu, Chen-Hsien Hung, Matthew Ray Harrington
  • Patent number: 9593672
    Abstract: A power generating device (2, 3) for supplying power to a power system (37). The power generating device includes a first component (87) for generating a first signal representing a frequency of a voltage on the power system, a power converter (90) for generating an output voltage, a second component (82) responsive to the first signal and to a second signal representing the output voltage, the second component producing an error signal representing a phase angle difference between the first and second signals, and the error signal being an input to the power converter for controlling the power converter to maintain the phase angle difference between the output voltage and the first signal.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 14, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Robert J. Nelson, Jesper Hammelsvang, Hongtao Ma, Jakob Skjoeth
  • Patent number: 9543972
    Abstract: Circuitry for providing an oscillating output signal. This circuitry includes a transconductance circuit having a first input, a second input, an output. The transconductance also includes a first transistor, a second transistor, and chopping circuitry. The chopping circuitry is for alternatively connecting, in a first clock cycle phase, a first node to a first terminal of the first transistor and a second node to a first terminal of the second transistor and, in a second clock cycle phase, following the first clock cycle phase, the first node to the first terminal of the second transistor and the second node to a first terminal of the first transistor. An oscillator circuit is also included and coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramamurthy Venkata Ramanan, Venkiteswaran Mahadevan
  • Patent number: 9479148
    Abstract: A clamping circuit clamps a serial data signal between a first high voltage level and a first low voltage level to yield a clamped serial data signal. A first comparator circuit compares the clamped serial data signal to a second high voltage level less than the first high voltage level to yield a high output equal to one just when a voltage of the clamped serial data signal is greater than the second high voltage level. A second comparator circuit compares the clamped serial data signal to second low voltage level greater than the first low voltage level to yield a low output equal to one just when the voltage of the clamped serial data signal is greater than the second low voltage level. An edge circuit detects an edge of the serial data signal from the high output and the low output.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 25, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) PTE. LTD.
    Inventor: Jian Meng
  • Patent number: 9444468
    Abstract: Oscillator devices and corresponding methods are disclosed. In some embodiments an apparatus includes an oscillator circuit arrangement, a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement and a reference resistor circuit. The apparatus further includes a sample and hold circuit, wherein a first input of the sample and hold circuit is coupled to an output of the reference resistor circuit and a second input of the sample and hold circuit is coupled to an output of the frequency variable resistor circuit, wherein an output of the sample and hold circuit is coupled with an input of the oscillator circuit arrangement.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies AG
    Inventors: David Astrom, Andreas Fugger, Herwig Wappis
  • Patent number: 9391624
    Abstract: Embodiments include a method comprising: receiving a reference clock signal; generating, by a digitally controlled oscillator, an output signal, wherein the reference clock signal has a first frequency, and wherein the digitally controlled oscillator is configured to generate the output signal at a second frequency; based on the output signal, generating a first feedback signal, wherein the first feedback signal is representative of a phase of the output signal relative to the reference clock signal; based on the first feedback signal, generating a second feedback signal, wherein generating the second feedback signal comprises, in response to the second frequency being an integer multiple of the first frequency, modifying the first feedback signal to generate the second feedback signal; and based on the second feedback signal, generating a control signal, wherein the output signal is generated by the digitally controlled oscillator based on the control signal.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 12, 2016
    Assignee: Marvell International Ltd.
    Inventor: Olivier Burg
  • Patent number: 9385694
    Abstract: A circuit for generating a signal comprising a first transistor having a drain, a gate and a source. A second transistor having a drain, a source and a gate coupled to the gate of the first transistor to form a current mirror. A current source coupled to the source of the first transistor. A diode-connected transistor having a drain coupled to the source of the second transistor, a source and a gate that forms an output. A variable resistor having a first terminal coupled to the source of diode-connected transistor and a second terminal. A capacitor coupled to the second terminal of the variable resistor.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 5, 2016
    Assignee: CONEXANT SYSTEMS, INC.
    Inventors: Christian Larsen, Gomathi Komanduru
  • Patent number: 9319094
    Abstract: A wireless transceiver includes a transmit path configured to generate a radio frequency (RF) transmit signal for transmission via an antenna, the transmit path generating a feedforward signal having at least one adjustable phase. A receive path is configured to receive an RF receive signal via the antenna. A circulator-based duplexer includes a circulator configured to couple the transmit signal from the transmit path to the antenna and to couple the receive signal from the antenna to the receive path. A controller is configured to process feedback from the receive path and to control the at least one adjustable phase to cancel portions of the transmit signal on the receive path.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 19, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: Seunghwan Yoon, Ahmadreza Rofougaran, Alireza Tarighat Mehrabani
  • Patent number: 9214897
    Abstract: An oscillation circuit includes a temperature compensating section to which electric power is supplied from a main power supply and a backup power supply, an oscillating section, a function of which is compensated by a signal from the temperature compensating section, and a switch and a power-supply monitoring circuit configured to select, when the temperature compensating section is not operating, at least one of the main power supply and the backup power supply and control connection to the temperature compensating section.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 15, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Tsuyoshi Yoneyama
  • Patent number: 9212628
    Abstract: An abnormality detection device for an exhaust gas recirculation apparatus is provided that can perform abnormality detection with respect to an EGR valve while suppressing the influence of a size relationship between an intake pressure and an exhaust pressure. An ECU (Electronic Control Unit) executes processing for extracting a pulse from an intake pipe pressure value. The ECU executes arithmetic processing for performing Fast Fourier Transform (FFT) with respect to an output waveform of an intake pressure sensor obtained by sampling processing, and also executes extraction processing that extracts a “frequency component corresponding to a period of an exhaust pulse”. The ECU executes processing that determines, in steps, whether or not the size of the extracted pulse (amplitude size) exceeds a threshold value. If the amplitude size exceeds the threshold value, the ECU executes processing that determines that a totally closed abnormality is occurring in the EGR valve.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: December 15, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shigeki Miyashita, Shinji Sadakane, Masahiro Inoue, Atsushi Fukuda, Yutaka Hayakawa
  • Patent number: 9116184
    Abstract: A system and method are presented for verifying the operating frequency of digital control circuitry. The system and method according to the present disclosure provide for a digitally controlled system, such as an electrosurgical system, to confirm or verify its operating frequency using a single external device, and software and/or firmware.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: August 25, 2015
    Assignee: Covidien LP
    Inventor: James E. Krapohl
  • Patent number: 9093985
    Abstract: A portable control apparatus includes a driver, a baseband controller, and a crystal oscillator. The driver includes an oscillating circuit that generates a feedback signal. The baseband controller coupled to the driver receives the feedback signal, and outputs a calibrating signal to the driver according to the feedback signal. The crystal oscillator coupled to the baseband controller generates an accurate output frequency for operating the baseband controller.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 28, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Huimin Tsai, Chi Kang Liu
  • Patent number: 9077438
    Abstract: A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: July 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Tae-Wook Kang, Kwang-Jin Na
  • Publication number: 20150137895
    Abstract: Technologies are generally described for quadrature-based injection-locking of ring oscillators. In some examples, an external signal may be injected into a ring oscillator. Phase signals may be measured from within the ring oscillator and used to determine a mean quadrature error (MQE) that characterizes the difference in frequency between the external signal and the ring oscillator's natural frequency. A control signal may then be generated from the MQE and used to adjust the ring oscillator natural frequency to reduce the difference between the ring oscillator natural frequency and the external signal.
    Type: Application
    Filed: September 5, 2014
    Publication date: May 21, 2015
    Inventors: Mayank Raj, Azita Emami
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Patent number: 9019016
    Abstract: There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 28, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Eizo Ichihara
  • Patent number: 9020088
    Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Topcon Positioning Systems, Inc.
    Inventors: Mark I. Zhodzishsky, Victor A. Prasolov, Alexey S. Lebedinsky, Daniel S. Milyutin
  • Patent number: 9007131
    Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 14, 2015
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8975924
    Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 10, 2015
    Assignee: NXP B.V.
    Inventors: Louis Praamsma, Nikola Ivanisevic
  • Patent number: 8975969
    Abstract: Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Michael C. Meholensky, Vadim Olen, Adrian A. Hill, Paul L. Opsahl
  • Publication number: 20150061781
    Abstract: An electronic circuit, includes: a first oscillator configured to generate a reference signal; a plurality of phase synchronization circuits, each including a second oscillator configured to generate an output signal having a frequency corresponding to an input, and a phase comparator configured to input, to the second oscillator, a signal corresponding to a phase difference between the output signal generated by the second oscillator and the reference signal generated by the first oscillator; and a controller configured to control relative phases of the reference signals input to the phase synchronization circuits from the first oscillator, based on the signals input to the corresponding second oscillators from the phase comparators in the phase synchronization circuits.
    Type: Application
    Filed: August 4, 2014
    Publication date: March 5, 2015
    Inventor: Toshihiro SHIMURA
  • Publication number: 20150061780
    Abstract: An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase.
    Type: Application
    Filed: April 20, 2012
    Publication date: March 5, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Hubert Bode, Mathieu Lesbats
  • Publication number: 20150061779
    Abstract: Provided are a digitally controlled oscillator and an electronic device including the digitally controlled oscillator. The digitally controlled oscillator includes a digital control unit and a power control oscillation unit. The digital control unit compensates for a difference between a feedback signal of an output power and a reference power set based on an input digital control signal and outputting an output power. The power control oscillation unit receives a signal related to the output power, and generates an output clock having an oscillation frequency in response to the signal related to the output power.
    Type: Application
    Filed: July 2, 2014
    Publication date: March 5, 2015
    Inventor: Du-ho Kim
  • Patent number: 8957705
    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Wenyan Jia, Shenggao Li, Fulvio Spagna
  • Patent number: 8947167
    Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Broadcom Corporation
    Inventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
  • Publication number: 20150028957
    Abstract: A PLL device includes a variable frequency oscillator and a frequency divider section. The variable frequency oscillator varies an oscillation frequency in response to a control signal including information on a phase difference between a reference signal and a frequency division signal and oscillates an output signal obtained by multiplying a frequency of the reference signal. The frequency divider section frequency-divides the output signal to generate the frequency division signal. An injection locked frequency divider is arranged in the frequency divider section, the control signal is input to the injection locked frequency divider, and the operation frequency of the injection locked frequency divider is controlled by the control signal.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 29, 2015
    Inventors: Toshihide Suzuki, Hiroshi Matsumura
  • Patent number: 8937572
    Abstract: A signal generator of an embodiment has an oscillator to generate an oscillation signal controlled in frequency by an analog control signal; a digital phase detector; a first differentiator; and a comparator outputting digital frequency error information. The generator includes a second differentiator differentiating the frequency setting code to generate a gain value and an inverse number of the gain value; a first multiplier multiplying the digital frequency error information by the gain value, a low-pass filter removing a high frequency component in a multiplication result, and a second multiplier multiplying an output of the low-pass filter by the inverse number. The generator includes a D/A converter converting a multiplication result into analog frequency error information, and an integrator converting the analog frequency error information into analog phase error information to output the analog phase error information as the analog control signal.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuka Kobayashi, Hiroki Sakurai
  • Publication number: 20150008985
    Abstract: An oscillator comprising: an oscillator circuit element having a substrate terminal group and a capacitance section provided on an element substrate, the substrate terminal group comprising at least three substrate terminals including a first substrate terminal and a second substrate terminal, the capacitance section being connected between the first and second substrate terminals; a mount part including an external terminal group comprised of at least one external terminal and mounting thereon the oscillator circuit element; a plurality of inductance lines which are formed among the at least three substrate terminals by conductor wirings which connect between the at least three substrate terminals of the substrate terminal group and the at least one external terminal; and a switch circuit provided on the element substrate to control a connection state of the plurality of inductance lines.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takashi KURAMOCHI
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Patent number: 8928417
    Abstract: A phase frequency detector realizes a highly linear conversion from noise-shaped ?? modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: January 6, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: David Canard
  • Patent number: 8929502
    Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Endo, Keisuke Ueda, Toshiya Uozumi
  • Patent number: 8907730
    Abstract: A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Pixart Imaging Inc
    Inventors: Chih Yen Wu, Chien Jung Huang, Hsiang Sheng Liu, Ching Chih Chen
  • Patent number: 8896386
    Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 25, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Wen-Chang Lee, Ping-Ying Wang
  • Publication number: 20140340720
    Abstract: An oscillation device includes an oscillator, an oscillation detection unit that detects oscillation of the oscillator and outputs an oscillation detection signal, and a drive unit that generates a drive signal in keeping with the oscillation detection signal and outputs the drive signal to the oscillator. The drive unit includes a phase shift unit that shifts the phase to provide the drive signal as positive feedback to the oscillator. The phase shift unit includes a disturbance generating unit that outputs the periodic signal, a fluctuation unit that causes the amount of phase shift to fluctuate based on the periodic signal, a drive amplitude detection unit that detects the amplitude of the drive signal and outputs a drive amplitude signal, a product detection unit that outputs a detection signal after performing product detection on the drive amplitude signal based on the periodic signal, and an adjustment unit that adjusts the phase-shift amount based on the detection signal.
    Type: Application
    Filed: May 12, 2014
    Publication date: November 20, 2014
    Applicant: Funai Electric Co., Ltd.
    Inventors: Ryusuke HORIBE, Naoki INOUE, Manabu MURAYAMA
  • Patent number: 8890624
    Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shuo-Wei Chen, David Kuochieh Su
  • Patent number: 8884704
    Abstract: Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a VCO's output into the VCO's input in negative phase by means of a frequency-to-voltage (F/V) converter. Embodiments enable constant VCO gain over a wide input tuning range and across PVT variations. Further, embodiments can be nested within a PLL, for example, with negligible area and power consumption overhead.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Michael Youssef, Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8878614
    Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: MegaChips Corporation
    Inventors: Wenjing Yin, Anand Gopalan
  • Patent number: 8878613
    Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: November 4, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Kevin H. Wang, Saru Palakurty, Frederic Bossu