Abstract: An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.

Abstract: A system and method for monitoring personal mobility vehicles in urban environments, comprising a double magnetic coil (1), disposed at an area of personal mobility vehicle traffic, and connected to an oscillator circuit (2), a phase-locked loop (3), a signal conditioning circuit (4) and a signal processor (5); where the signal processor (5) is configured to calculate the temporal variation in voltage (V(t), V?(t)) produced in the phase-locked loop (3) and due to a variation in the oscillation frequency of the double magnetic coil (1) when at least one personal mobility vehicle passes said double magnetic coil (1); and to establish the type, speed, direction of travel and length of the personal mobility vehicle that has generated the variation in the oscillation frequency of the double magnetic coil (1).

Abstract: The present invention provides a frequency selective circuit, comprising: a voltage-controlled oscillator for outputting a frequency corresponding to the frequency adjustment window; a frequency divider for dividing the clock frequency output by the voltage-controlled oscillator, and feeding back the resulting low frequency to the frequency selection unit; a frequency selective unit for comparing a reference frequency with the resulting low frequency output by the frequency divider, and providing the frequency adjustment window which is configured based on the frequency search window to the voltage-controlled oscillator; a register group for outputting the frequency search window which is provided to the frequency selective unit. The embodiment of the present invention convert the clock frequency from a high frequency to a low frequency. The low frequency is compared with the reference frequency to ultimately find the corresponding low frequency that has the same frequency as the reference frequency.

Abstract: Additional information can be packed into each message element of a 5G/6G message by varying the amplitude of the signal within the symbol-time of the message element. For example, the difference between the amplitude at the beginning and ending of the symbol-time may encode additional bits, thereby providing higher information density in each transmission. The amplitude variation may be abrupt, such as a sudden change from the first amplitude value to the second amplitude value in the middle of the symbol-time, or it may be a gradual linear ramp spanning the symbol-time. In either case, the modulation scheme may include amplitude variation levels as well as the amplitude levels themselves, thereby providing a larger modulation space and hence shorter messages. Effects on crosstalk and frequency offset due to the amplitude variation, and their mitigation, are also disclosed.

Abstract: Disclosed are a phase shift method and a device performing same, the method comprising the steps of: shifting a phase of an input signal by a phase shifter, and up-converting, by a frequency quadrupler, a frequency of the input signal of which the phase has been shifted, by a multiplication coefficient (N). According to the phase shift method and the device performing same, it is possible to overcome a phase resolution decrease that occurs when passing through a frequency quadrupler in super high-frequency LO beamforming technology synchronized with a conventional frequency quadrupler.

Abstract: A control circuit and a method for delaying an electronic signal are provided, along with a time-to-digital converter including the control circuit. The example control circuit includes a first delay circuit having a first plurality of delay elements electrically connected in series and configured to generate a first control voltage associated with a first delay time. The control circuit further includes a second delay circuit having a second plurality of delay elements electrically connected at least in part in series. The second delay circuit is configured to generate a second control voltage associated with a second delay time. A first group of delay elements within the second plurality of delay elements exhibits the first delay time based on the first control voltage, and a second group of the second plurality of delay elements exhibits a second delay time based at least in part on the second control voltage.

Abstract: An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.

Abstract: A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

Abstract: A programmable drive-sense unit (DSU) includes a drive-sense circuit operably coupled to a load, wherein the drive-sense circuit is configured to drive and simultaneously to sense the load via a single line, and produce an analog output based on the sensing the load. The programmable DSU also includes an analog to digital circuit operably coupled to the drive-sense circuit, where the analog to digital circuit is operable to generate a digital output based on the analog output and in accordance with one or more programmable operational parameters to achieve one or more of load sensing objectives associated with the sensing of the load and data processing objectives associated with the sensing of the load.

Abstract: A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: This application is directed to controlling bandwidths of clock recovery circuit in an electronic device. The electronic device includes a clock recovery circuit and a bandwidth controller coupled to the clock recovery circuit. The clock recovery circuit is configured to receive a data signal carrying a stream of data bits according to a reference clock frequency and recover a clock signal from the data signal. The bandwidth controller is configured to control the clock recovery circuit to start with a pull-in bandwidth, settle at a target bandwidth, and apply an intermediate bandwidth between the pull-in bandwidth and target bandwidth. The intermediate bandwidth is greater than the target bandwidth and less than the pull-in bandwidth. In some implementations, the bandwidth controller controls the clock recovery circuit to apply one or more additional bandwidths to the clock signal after the pull-in bandwidth and the intermediate bandwidth and before the target bandwidth.

Abstract: Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Abstract: The present invention discloses a multiband resonance frequency tracking circuit applied to ultrasonic machining, including an output current-voltage phase difference direction detection circuit and a multiband resonance frequency tracking circuit, where a detection signal output end of the output current-voltage phase difference direction detection circuit is connected to a signal input end of the multiband resonance frequency tracking circuit. Through the foregoing technical solutions, in the present invention, a system detuning state is quickly determined by using a current-voltage phase difference direction detection signal outputted by a D flip-flop in a chip SN74HC74D, and a dead-time resistor between a 5th pin and a 7th pin in a chip EG3525 can be changed in a timely manner based on a detuning degree of a piezoelectric transducer, so as to change a system driving frequency to track a resonance frequency of the piezoelectric transducer and implement fast and accurate tracking.

Abstract: A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i?1 in the sequence.

Abstract: A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

Abstract: This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.

Abstract: The present disclosure relates to a clock distribution method and apparatus in a network. A method performed at a clock distribution apparatus comprises: receiving a first clock signal; receiving a second clock signal; calculating an offset difference between the first clock signal and the second clock signal; compensating the second clock signal, based on the offset difference; and outputting a clock signal, based on the compensated second clock signal. The offset difference between the first clock signal and the second clock signal is calculated and used to compensate the second clock signal. The switching of the clock signal will be smoother for the downstream.

Abstract: A semiconductor integrated circuit includes an oscillation circuit and first and second current control circuits. The oscillation circuit includes a first series circuit having inverters, including a first inverter, connected in series and a second series circuit having inverters, including a second inverter, connected in series. An oscillation signal is output from the first series circuit. The first current control circuit is connected between a current source and an output terminal of the first inverter and configured to control a current from the current source into the first series circuit in accordance with a first signal synchronized with a clock signal. The second current control circuit is connected between an output terminal of the second inverter and a reference voltage node and configured to control a current from the second series circuit to the reference voltage node in accordance with a second signal synchronized with the clock signal.

Abstract: A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.

Abstract: The present disclosure provides a photonics-aided vector terahertz signal communication system. The system includes an optical frequency comb generation module, a vector terahertz signal generation module, an optical fiber transmission module, a vector terahertz signal detection module, and a vector terahertz signal emission module that are sequentially connected, where the vector terahertz signal generation module includes a first binary sequence generator, a first electronic amplifier, and a first intensity modulator that are sequentially connected, the first binary sequence generator generates binary data representing to-be-transmitted data, the first intensity modulator performs, based on the binary data, amplitude modulation on an optical frequency comb entering the first intensity modulator, and an optical signal obtained after the modulation of the first intensity modulator is a vector terahertz signal carrying the to-be-transmitted data.

Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

Abstract: To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.

Abstract: A phase adjusting circuit, a delay locking circuit, and a memory are provided. The phase adjusting circuit includes a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence. The detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference is a preset value.

Abstract: A measurement device and method for testing a device under test (DUT). The device includes an input terminal for receiving a RF signal from the DUT; at least one analog-to-digital (A/D) converter configured to generate a digital data including a plurality of sampled signals from the received RF signal; at least one filter configured to filter the digital data generated by the at least one A/D converter based on an intermediate-frequency bandwidth (IFBW) set in the at least one filter; a detector configured to analyse the filtered digital data based on a pre-set number of samples from the filtered digital data; and a controller configured to calculate a signal-to-noise ratio (SNR) value of the analysed filtered digital data, and to adjust at least one of the IFBW of the at least one filter and the number of samples of the detector based on the calculated SNR value.

Abstract: A radar transceiver includes a receiver. The receiver includes a low noise amplifier a mixer, a baseband filter, an integrator, and a phase shifter. The mixer includes an input coupled to an output of the low noise amplifier. The baseband filter includes an input coupled to an output of the mixer. The integrator includes an input coupled to an output of the baseband filter. The phase shifter includes a control input and an output. The control input is coupled to an output of the integrator.

Abstract: Disclosed is a low-power fractional-N phase-locked loop circuit, which comprises a phase detector, a voltage-to-current converter, a loop filter, a voltage-controlled oscillator, a frequency divider and a digital logic processor; the phase detector, the voltage-to-current converter, the loop filter, the voltage-controlled oscillator and the frequency divider are connected in sequence; a reference signal is input from the phase detector, the phase detector detects the phases of the reference signal and a feedback signal with a quantization error output by the frequency divider, compensates a quantization phase error generated by fractional frequency division, and outputs a compensated phase detection result to the voltage-to-current converter; the quantization error generated by fractional frequency division is converted into a voltage domain through a digital domain or directly coupled to a phase error signal in the phase detector to complete the compensation of the quantization error.

Abstract: An image is split into a plurality of blocks of various sizes and a subdivision level counter is associated to each of the blocks. The value of this subdivision level counter for a block is representative of the size of the block and is used to determine the quantization parameter for the block. The value is propagated for each subdivision and incremented according the type of the subdivision. When the image is split, an analysis is done according to the subdivision level counter, a maximal value of subdivision and the type of split, in order to determine the start of a new quantization group and when it is the case, the current position of the partition is propagated to the further split partitions to be stored with these partition and serve in the prediction process when decoding.

Abstract: A clock generator includes a resistor-capacitor-based voltage-controlled oscillator (RC-based VCO) that generates an output signal with oscillation frequency controlled by an input voltage at an input node; and a temperature compensator that generates the input voltage to compensate change of the oscillation frequency associated with a change in temperature.

Abstract: A processing system including an amplifier configured to generate, from multiple spatial-common-mode-processed signals, a spatial common mode estimate and multiple feedback signals. The processing system includes multiple charge integrators configured to obtain resulting signals from the capacitive sensor electrodes, each of the resulting signals including a spatial common mode component and a residual noise component. The charge integrators generate multiple spatial-common-mode-processed signals by mitigating the spatial common mode component and the residual noise component in the resulting signals using the feedback signals. The processing system includes a programmable gain amplifier configured to determine the spatial common mode estimate.

Abstract: A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.

Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.

Abstract: The present disclosure provides a delay circuit and a semiconductor device. The delay circuit includes a delay unit and a linear voltage regulator unit; wherein, the delay unit includes an inverting unit and a power supply control unit, and the inverting unit includes an inverting unit and a power supply control unit. The inversion unit receives an input signal and delays the input signal, and the power supply control unit is used for providing a voltage to the inverting unit according to the power supply control signal; the linear voltage stabilization unit is coupled to the delay unit and outputting the power supply control signal according to a reference voltage. The voltage outputs the power control signal. The present disclosure can accurately control the delay time of the delay unit and improve the delay precision of the delay circuit.

Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.

Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

Abstract: An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.

Abstract: Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A method for compensating for noise in a secondary radar system is described. The method includes, using a first transceiver, transmitting, in temporally overlapping manner, a first transmission signal containing a first interfering component and a second transmission signal containing a second interfering component, and compensating for at least one of phase shifts or frequency shifts resulting from the first and second interfering components by evaluation of the first and second transmission signals.

Abstract: A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Abstract: A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.