Abstract: A method utilizing intentionally generated in-band frequency harmonics to compensate for frequency error and frequency drift in a voltage controlled oscillator of a receiver, thereby eliminating the frequency synthesizer and RF divider required in conventional designs. The method includes modulating the intentionally generated frequency in a predetermined manner so that a receiver can identify the intentionally generated frequency and includes the use of plural frequency harmonics for use in a curve fitting technique to correct frequency error in the voltage controlled oscillator.

Abstract: A phase locked loop ("PLL") 28 containing apparatus for automatically causing the PLL to achieve phase lock when first energized or after having lost phase lock. In addition to a phase detector 4, loop filter 13, voltage controlled oscillator ("VCO") 14 and feedback from the VCO to the phase detector 16, the PLL has a sweep circuit 30. The sweep circuit cooperates with the loop filter when the PLL is not in phase lock to automatically generate a control voltage for the VCO which control voltage increases linearly with time until the PLL achieves phase lock or until the control voltage has reached the largest voltage in the dynamic input range of the VCO. In the event that phase lock is not achieved during the period of the increasing voltage, the control voltage decreases linearly with time to drive the PLL into phase lock.

Abstract: A phase locked loop includes a controlled oscillator that is responsive to a control signal to generate an output signal, the frequency of which is a function of the control signal. A phase detector is responsive to a reference frequency input signal and to the output signal, to produce an error signal. A loop filter filters the error signal, to thereby produce the control signal. An acquisition sweep circuit is responsive to an activation signal, to sweep the control signal and thereby aid to acquire lock in the phase locked loop. Simultaneous increase in the amplitude of the reference frequency input signal is provided during sweep of the control signal. The increase in amplitude may be provided by a variable attenuation circuit that is coupled between a phase locked loop input signal and the reference frequency input signal, and that is also responsive to the activation signal.

Abstract: A system of spreading the energy of higher harmonic frequencies in digital circuits to lower the interference to bandpass receivers is disclosed. A set of passive, impedance-regulated circuits, preferably housed in a standard enclosure, comprises a power restoring unit, a modulating signal generator, an internal oscillator and an impedance spreading unit. The circuits are equivalent to passive resonators such as crystal resonators used in standard oscillators. Any existing standard oscillator that uses common crystal resonators can be transformed into a spectrum-spread oscillator by replacing the crystal resonator with the disclosed circuit, whereby a tightly controlled small frequency spreading occurs in the fundamental clock frequency. Further an active oscillator is disclosed wherein a spreading circuit spreads the frequency of the clock signal originally generated by the oscillator based on a sequence of processing the original clock signal.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A frequency-shift-keyed PLL frequency synthesizer with large frequency-muplication factor, with absolute frequency deviation independent of frequency-multiplication factor. The PLL also has fractional frequency-multiplication-factor programming capability. The PLL is inexpensive to implement, and potentially capable of fast frequency changing, due to lack of need to compensate modulator frequency deviation with possible resulting stabilization-time requirements, associated with each PLL output-frequency change. The PLL frequency synthesizer preferably employs a PLL-DRO and subharmonic mixer to achieve stable, low-noise microwave output frequencies.

Abstract: An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control.

Abstract: A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A lock detection circuit for a phase lock loop circuit having a phase lock loop circuit, generally a series circuit of a detector, a filter and a VCO with a PLL input terminal and an output terminal. A test circuit is coupled to the phase lock loop and includes a signal generator responsive to the presence of an input signal on the input terminal to inject a test signal into the phase lock loop. The signal generator is preferably a low frequency oscillator wherein the term "low" is defined to mean any frequency from a few hertz up to gigahertz and generally a few kilohertz, as long as this frequency is at least about an order of magnitude less than the frequencies to be encountered at the RF input to the PLL. The signal generated by the signal generator is compared with the signal injected into the phase lock loop which is generally injected ahead of the loop filter.

Abstract: A linear swept frequency generator includes a signal generator that generates an output signal having a frequency that varies between a first frequency and a second frequency. A delay element, such as an optical fiber having a reflector at one end, is configured to receive the output signal and to produce a delayed version of the output signal. This delayed version of the output signal is provided, along with the output signal, to a mixer that combines the signals to produce a reference signal. Finally, a feedback path between the mixer and the signal generator provides the reference signal to the signal generator so that the signal generator controls the frequency of the output signal in response to the reference signal.

Abstract: A phase lock acquisition control circuit for the local oscillator (LO) of a radar exciter. The control circuit includes a programmable logic array, a microsequencer and a counter employed as a divide-by-eight circuit which supplies a clock reference for the control circuit. The counter in turn is clocked by a crystal based oscillator also used as the reference for the exciter phase lock loop. The marker filter and zero beat detector provide frequency location information to the control circuit. The control circuit controls a ramp generator circuit which in turn can drive the phase lock loop VCO during acquisition.

Abstract: Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

Abstract: The present invention overcomes the problems discussed above by providing a linearizer apparatus for providing a linear ramp modulation for a voltage control oscillator (VCO), including voltage controlled oscillator means (VCO) having input and output terminals, and means for producing the output signal at its output terminal at the output frequency such that the output frequency corresponds to the voltage of a modulated tuning signal applied to the input terminal. A signal division means is coupled to the output of the VCO for producing a divided signal. A glass bulk acoustic delay means is coupled to the signal division means for producing a delayed signal. A first comparison signal generator means is coupled to the divided signal and the delayed signal for producing an IF signal which is proportional to the VCO output signal non-linearities. A reference oscillator means is provided for producing a reference signal.

Abstract: An automatic adjustment circuit for an oscillator converts an output from a register into an analog signal by means of a D/A converter. An oscillation frequency of an oscillator is controlled by an output of the D/A converter. A first counter for counting an oscillation signal of the oscillator 1 resets itself and generates a pulse when a count reaches a predetermined value. A second counter counts a reference frequency pulse having a frequency substantially higher than the oscillation frequency of the oscillator. The second counter, on completion of counting a given preset value, changes an output level. The second counter is preset by said first counter when the first counter resets itself. Outputs from the first and the second counters are processed by an AND operation in an AND circuit. A third counter counts an output from the AND circuit, and provides a count output to the register.

Abstract: An ultra-linear chirp generator includes a voltage controlled oscillator (VCO) having a tuning characteristic which is naturally nonlinear, a linear ramp generator which generates a linearly ramping output signal having a linear slope characteristic with respect to time, a polynomial correction waveform generator which generates a polynomial correction signal, and a summer which is responsive to and sums the linearly ramping output signal and the polynomial correction signal. The summer generates a VCO tuning signal for tuning the VCO. The tuning signal corresponds to the linearly ramping output signal predistorted with a nonlinearity opposite to the natural nonlinearity of the VCO tuning characteristic. The linear chirp generator also includes a phase locked loop which is responsive to the output signal of the VCO and which has a reference frequency which is related to the repetition rate of the output signal of the VCO.

Abstract: A control circuit for use with a phase locked loop in a digital video receiver. The digital receiver accepts a serial digital input signal which can comprise composite or component video signals. The phase locked loop comprises a phase detector, a loop filter, and a voltage controlled oscillator (VCO) and includes a divide-by-two modulus divider coupled to the output of the VCO. The VCO has an oscillation frequency control port and the divider has a frequency select port. The control circuit includes an automatic fine tuning and frequency sweeping stage which is coupled to the output of the loop filter and the oscillation frequency control port. The tuning and frequency stage provides temperature drift correction for the VCO. In addition, the tuning and frequency stage "sweeps" the oscillation frequency of the VCO to aid in "locking" the phase locked loop to the phase or frequency of the input signal. Once locked, timing signals and digital data can be extracted from the input signal.

Abstract: A signal source provides an output signal which can sweep over a broad frequency range in a well-controlled manner. The signal source includes a voltage controlled oscillator (VCO) producing the output signal and a waveform synthesizer producing a reference signal. The VCO output signal is phase locked to the reference signal. To make the VCO signal continuously sweep over a broad frequency range, the reference signal sweeps repeatedly over a narrow frequency range. During each sweep of the reference signal, the VCO frequency tracks an integer harmonic of the reference signal frequency. The frequency and phase of the reference signal for each successive sweep are abruptly reset at the beginning of each sweep selected such that the VCO signal frequency locks to another integer harmonic of the reference signal frequency and does not change.

Abstract: A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Abstract: An out of lock condition is sensed on a data transition by transition basis in clock recovery apparatus. When an out of lock condition is sensed, a range sweeping signal is generated and summed with the correction signal to sweep the frequency of the clock signal over the frequency range of the VCO. When an out of lock condition is absent, i.e., when the VCO is phase locked, simulated data transitions are generated in the frequency/phase detector. An out of lock condition is sensed by a D flip-flop. Data is coupled to the clock input of the flip-flop, the clock signal is delayed by a fraction of its nominal period and coupled to the D input of the flip-flop. The state of the Q output of the flip-flop indicates an out of lock condition.

Abstract: A multi-marker microwave sweep linearization system comprising a voltage controlled microwave oscillator utilizing an adaptive sweep control circuit is presented. The oscillator control voltage is to be adjusted as necessary to maintain a constant spacing between markers. To produce the markers, the output of the oscillator is mixed with the output at a comb generator having harmonics. The lower side bands generated as the oscillator sweeps past the comb frequencies generates a series of `chirps`, centered about each of the comb harmonics. It will be noted, that the frequency of the chirp passes through zero when the oscillator frequency is exactly equal to one of the comb harmonics. The marker is to be associated with a higher frequency in the chirp envelope to avoid phase uncertainties. This can be accomplished with a frequency-detector circuit which may comprise a retriggerable monostable multi-vibrator having a time constant equal to the period of the frequency to be detected.

Abstract: A demodulating apparatus, which includes an up/down counter which counts up and down in accordance with a phase detection signal from a phase detector, an addition/subtraction unit which adds and subtracts the value (.DELTA.F1, .DELTA.F2) of the synchronization pull-in range to the count output, a counter stoppage unit which monitors a recovered carrier synchronization detection signal INIT and freezes the count output of the up/down counter immediately when detecting a disconnection of the input signal, and a synchronization pull-in range setting unit which expands the synchronization pull-in range at the same time as this to make it .DELTA.F2. The time required until establishment of synchronization with the input signal next to be received after the disconnection of an input signal is shortened.

Abstract: An automatic sweep acquisition circuit for a phase-locked-loop using a positive feedback network coupled between a non-inverting input of an operational amplifier and an output of the operational amplifier is provided. The operational amplifier serves as a loop filter for the PLL and has a negative feedback network configured as a lead-lag integrator. The positive feedback network forms a Wein-bridge oscillator that automatically oscillates at a predetermined frequency when phase lock does not exist. A negative feedback path also supplies a portion of the phase shift required to activate the Wein bridge oscillator in order to provide sweep acquisition. When the circuit operates within the bandwidth of the PLL or within the lock-in range of the PLL the positive feedback network provides minimal feedback and thus creates no oscillation or sweeping voltage. The locked-in range of the PLL is increased to the pull-in range of the voltage controlled oscillator used in the phase-locked loop.

Abstract: A closed loop linearizer method and apparatus for providing a linear ramp modulation for a voltage controlled oscillator (VCO). A counter is connected to the VCO for calculating two frequency values of the oscillator at one or more time points during a ramp interval. The difference of the two frequency values is then compared with that of a predetermined ideal difference frequency value. A resulting correction value is then generated and used to adjust digital control values upward and downward, thereby causing the VCO to produce a linear modulation ramp output slope over time.

Abstract: A low-frequency low bandwidth Linear Frequency Modulation (LFM) waveform, nominally a 1 MHz to 10 Mz swept frequency analog sinusoid or digital square wave, is produced by direct digital synthesis. This waveform is upconverted in frequency and expanded in bandwidth, nominally to microwave frequencies with bandwidths of nominally 160-360 MHz, in a multiplying offset phase locked loop. The phase locked loop also linearly frequency modulates a X-band carrier with the microwave frequency LFM waveform to produce an output signal suitable for Synthetic Aperture Radar. The phase locked loop induces low phase error, and may be closed around the radar transmitter to remove phase errors induced by that unit.

Abstract: A method and apparatus for a sweep oscillator and a spectrum analyzer containing the sweep oscillator having a precisely determined center frequency includes a sweep circuit having a sawtooth waveform, a reference oscillator, a microprocessor controller and a modified phase-locked loop. The modified phase-locked loop further includes a control signal summer, a voltage controlled oscillator coupled to the control signal summer, a sweep oscillator output, and a sample and hold circuit including a switching circuit.

Abstract: A circuit for generating an output signal having an output frequency that varies linearly with time, and to an FM CW radar system utilizing such a circuit. The circuit includes a voltage controlled oscillator that produces an output signal at its output terminal at an output frequency that corresponds to the voltage of an input tuning signal. A comparison signal circuit receives the output signal and produces a periodic comparison signal such that when the output frequency varies by .DELTA.f, the comparison signal frequency varies by .DELTA.f/N where N is a positive integer. An update counter periodically causes the value of N to change by a predetermined integer amount. A phase detector compares the comparison signal to a periodic reference signal, and produces a correction signal that is filtered to provide the tuning signal for the VCO. The value of N is preferably changed at an update frequency that is equal to the frequency of the reference signal times an integer.

Abstract: A dual loop phase locked circuit is disclosed in which a first loop includes a phase detector, a filter, and a VCO; as a second loop includes a sweep voltage generator, a compensation circuit, and the filter of the first loop. Due to the compensation circuit, the VCO accurately tracks a signal from the sweep voltage generator, even though the filter has an electrical parameter that drifts with time and/or age and/or component selection.

Abstract: A satellite transmission capturing method for the GPS receiver whereby PLL operation is stopped until the demodulation intensity of a demodulator reaches a predetermined level. The frequency of the reproduced carrier of the demodulator is consecutively changed in increments of a frequency range wider than the PLL capture range in search for satellite transmissions. This allows the demodulation intensity to reach the predetermined level in fewer frequency changing steps than ever before. Thus the time required to capture the desired satellite transmission is reduced. Where the integral time constant of a low pass filter in the demodulator is set to a value smaller than that in effect during PLL operation until the demodulation intensity of the demodulator reaches the predetermined level, a wide band demodulation intensity curve is used in search for satellite transmissions until that level is exceeded.

Abstract: Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to tyhe accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency.

Abstract: Linearizing circuitry for an FMCW transmitter (1,2) employing a linear modulation waveform. The output signal is sampled (3,4,5) in successive intervals, small compared to the modulation period, and a cycle count (16) taken in each interval; a reference count is derived for each interval, either by way of a look-up table (21) triggered by a clock count (17) or derived by way of a clock driven processor (18). A comparison (20) is made and any error (22) is used to control (11) the phase of the modulation waveform.

Abstract: Range resolution in an FMCW radar system is achieved by providing a periodic linear frequency sweep. The present invention assures the linearity of this sweep by using a negative feedback circuit which includes means for obtaining 16 sequential instantaneous frequency versus time slope measurements during each sweep cycle, generating a set of 16 sequential error signals and a corresponding set of correction voltages, and applying these correction voltages to the sweep drive voltage used to drive the voltage controlled oscillator that generates the frequency swept output signal.

Abstract: A bandpass filter is used, which closely matches the characteristics of a closed phase lock loop (PLL) so as to provide an acquisition detector output in a PLL being swept. This detector is not activated by noise generated in the loop due to data or other perturbations. This filter includes a differentiator to exacerbate the filtered output and thus, more clearly define the condition being detected. The phase lock acquisition sweep is disabled when the detector output exceeds a predetermined absolute value. The detection scheme works equally well in approaching the lock frequency from above or below actual lock and a latch circuit ensures that the sweep approach always alternates to compensate for an erratic phase detector in the PLL.

Abstract: Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to the accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency. In a second embodiment, the DC representative phase signal is applied to an analog-to-digital converter (364) which produces an N-bit word representative of the phase difference.

Abstract: A phase-lock loop for a swept synthesized source in which hysteresis, tuning nonlinearity, and drift over time and temperature of an oscillator incorporated into the swept synthesized source are compensated. The tuning current to the oscillator is initialized to zero to eliminate hysteresis effects. Then, the pretune current is set to produce the minimum operating frequency of the oscillator. Next, the main phase-lock loop is closed, and a low-frequency synthesizer is swept to in turn sweep the oscillator over a selected frequency span. If the selected frequency span extends over other frequency bands, the oscillator is swept to the maximum frequency of the present band and held at this frequency by a track and hold circuit. The main phase-lock loop is opened, the low-frequency synthesizer is re-initialized, the main phase-lock loop is again closed, and the low-frequency synthesizer is swept again. Each frequency band is crossed in a similar manner until the selected frequency span is swept.

Abstract: A lock detector circuit (60) for demodulators of UQPSK signals I and Q has signal processing circuits for forming the signals:A=6I.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4 ;B=4(I.sup.2 -Q.sup.2).A switch (19) is provided for coupling either signal A or signal B to the output (20) of the detector circuit, depending on the value of the signal ratio Q/I. In an alternative embodiment, a summing circuit adds signal A and signal B, and directs the sum to the detector output (20). The resulting output signal is constant under lock conditions, and oscillates when the demodulator is unlocked. This output signal is directed through a comparator (49) to the sweep circuit (43) controlling demodulator VCO (42), and causes the demodulator to remain in the locked condition. The lock detector circuit is effective for any value of Q/I, and utilizes only three analog multiplier circuits.

Abstract: The invention relates to a phase-locked oscillator for communication apparatus and the like, and provides a phase lock detection circuit which can positively perform the phase lock detection. In order to accomplish this object, the output of a loop filter (2) is supplied to a first level detector (5) and also to an amplitude detector (6). The output of the amplitude detector (6) is supplied to a second level detector (7). A switching means (8) performs the switching operation in accordance with the output of the second level detector (7) to select an output from the first level detector (5) or a LOW level, and the selected one is output as a phase lock detection signal.

Abstract: A method for a phase-locked loop, which circuit includes, in a preferred embodiment, a resistor to unbalance phase detector outputs to an operational amplifier to cause the voltage output of the operational amplifier to sweep and thus cause the frequency output of a voltage controlled oscillator to sweep. Simple circuitry detects correct lock and terminates sweeping; or, if lock is not achieved, causes the output of the operational amplifier to remain at a low level until the operational amplifier is reset and then permits resweep. Very little auxiliary circuitry is required.

Abstract: A swept synthesizer signal source provides a digital synchronization signal for accurate internal synchronization of events and for external synchronization of data taking and other operations to predetermined frequencies generated by an oscillator during a sweep. The digital synchronization signal includes a predetermined number of digital pulses, regardless of the sweep time. A ramp voltage which controls the oscillator is corrected during a calibration period to sweep between predetermined limits, thereby insuring that the ramp voltage is synchronized to the digital synchronization signal. The slope of the frequency versus time sweep is also corrected to further improve accuracy. A power level correction technique insures precision power leveling regardless of the sweep range. A table of correction/frequency pairs is entered into the instrument, and an interpolation algorithm is employed to determine corrections at frequencies corresponding to each synchronization pulse.

Abstract: A swept synthesizer signal source provides a digital synchronization signal for accurate internal synchronization of events and for external synchronization of data taking and other operations to predetermined frequencies generated by an oscillator during a sweep. The digital synchronication signal includes a predetermined number of digital pulses, regardless of the sweep time. A ramp voltage which controls the oscillator is corrected during a calibration period to sweep between predetermined limits, thereby insuring that the ramp voltage is synchronized to the digital synchronication signal. The slope of the frequency versus time sweep is also corrected to further improve accuracy. A power level correction technique insures precision power leveling regardless of the sweep range. A table of correction/frequency pairs is entered into the instrument, and an interpolation algorithm is employed to determine corrections at frequencies corresponding to each synchronization pulse.

Abstract: A frequency synthesized, microwave signal generator is disclosed that provides multiple channel frequency selection capability with rapid channel change time and low levels of spurious signals and noise. The generator uses a microwave harmonic phase locked loop to lock a microwave VCO to a programmable harmonic of a VHF reference crystal oscillator to provide coarse frequency control in steps equal to that reference frequency. The phase lock loop includes an offset mixer for injecting an offset signal frequency to achieve fine frequency control. A harmonic detection and counting scheme is used to rapidly sweep the harmonic loop and obtain phase lock at the desired harmonic.

Abstract: A swept synthesizer signal source provides a digital synchronization signal for accurate internal synchronization of events and for external synchronization of data taking and other operations to predetermined frequencies generated by an oscillator during a sweep. The digital synchronization signal includes a predetermined number of digital pulses, regardless of the sweep time. A ramp voltage which controls the oscillator is corrected during a calibration period to sweep between predetermined limits, thereby insuring that the ramp voltage is synchronized to the digital synchronization signal. The slope of the frequency versus time sweep is also corrected to further improve accuracy. A power level correction technique insures precision power leveling regardless of the sweep range. A table of correction/frequency pairs is entered into the instrument, and an interpolation algorithm is employed to determine corrections at frequencies correponding to each synchronization pulse.

Abstract: Microprocessor (MPU) controlled voltage controlled oscillator (VCO) linearization circuitry locks the VCO at desired low, center and high frequencies (F.sub.1, F.sub.c and F.sub.h) and measures the magnitudes of the corresponding control voltages (V.sub.1, V.sub.c and V.sub.h). Next, the VCO is swept at a nominal clock frequency to determine the times (T.sub.1, T.sub.2 and T.sub.h) that the control voltages (V.sub.1, V.sub.c and V.sub.h) occur during the sweep cycle. The control voltage of the VCO is then swept at a first and then a second rate during a sweep cycle to assure that the center frequency (F.sub.c) of the VCO occurs at the time (T.sub.c) midpoint of the sweep cycle. As a result, each VCO frequency can be determined by MPU monitoring according to the time that the VCO frequency occurs during the sweep cycle. This circuitry is useful in spectrum analyzers for indirectly determining the otherwise unknown frequency of a received signal.

Abstract: Circuit for use in a surgical operation including a phase lock loop having a voltage controlled oscillator, and a phase comparator for comparing a phase of a voltage of a driving signal and a phase of a signal representing the vibration phase of the ultrasonic transducer to derive a phase difference therebetween which is applied to the voltage controlled oscillator as a frequency control voltage such that the driving signal is phase-locked with a resonance frequency of the ultrasonic transducer, the improvement being characterized in that during a start period, a reference signal having a frequency which is increased monotonously is applied to the phase comparator such that the frequency of the driving signal is increased until the driving signal is phase-locked with the vibration phase of the ultrasonic transducer vibrating at the resonance frequency.

Abstract: A phase lock recovery apparatus for a phase locked loop circuit having a voltage controlled oscillator. The apparatus includes a detection circuit coupled to the phase locked loop circuit for detecting a phase unlocked state occurred in the phase locked loop circuit and a sweep signal generator responsive to the detection circuit for sweeping the frequency of the voltage controlled oscillator to come within the lock range of the frequency of the input signal when the phase unlocked state is detected.

Abstract: Disclosed is a tracking bit synchronizer for use in digital data apparatus such as high density digital magnetic tape recorders. The disclosed bit synchronizer effects synchronization of data if the data rate is known within one octave. Moreover, data rates can change during operation over an octave range without bit errors or other loss of data. The bit synchronizer includes a phase locked loop which produces a clocking signal in synchronism with incoming encoded data. A data error detector uses information from a data decoder to determine if phase lock at the proper data rate has occurred. Control circuitry uses this information, along with the output voltage of the phase locked loop filter, to operate the phase locked loop in either a seek mode or a tracking mode. A squelch circuit prevents phase corrections during data signal dropouts.

Abstract: A frequency synthesizer is provided in which the output is a truly continuous sweep of frequency, not a staircase of spot frequencies. A programmable frequency divider PD is connected to the output of a voltage-controlled oscillator (VCO) to divide the VCO output by a variable integer N. At each VCO output cycle, the integer N is incremented (or decremented). The output of a phase comparator PC, which compares the divider output with a fixed reference frequency, is connected via an integrator (10) to the VCO frequency control input (2). A constant phase error produces a ramp rise of VCO frequency.

Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.2, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F).

Abstract: A linear digital frequency sweep synthesizer employs an up-down counter for producing a first signal having a plurality of pulses with time interval between pulses linearly increasing with time and a phase lock loop for producing a second signal having a plurality of pulses having a frequency sweep linearized to the linearly increasing time intervals of such first signal.