Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A method and apparatus for producing high-frequency oscillations is disclosed. A new resonator architecture minimizes via losses and supports a compact layout of active circuitry. The resonator architecture incorporates dual resonant transmission lines to reduce resonator loss and facilitate compact layout. The oscillations of two oscillators are cross-coupled in a way that compensates for the delay in the active devices of the oscillator, thus permitting accurate alignment of the active circuitry response with the oscillation waveform. The cross-coupling of the two oscillators improves phase noise performance and eliminates spurious oscillations. An active circuit architecture provides very narrow pulses for the operation of the oscillator. This architecture provides for accurate cross-coupling and pulsed-mode operation to improve manufacturing stability and phase noise performance.

Abstract: Briefly, devices and methods for tuning of quadrature oscillators which may be used, for example, in a Complementary Metal-Oxide Semiconductor (CMOS) process. Devices and methods in accordance with some exemplary embodiments of the invention may allow, for example, improved locking, tuning and performance of slave oscillators and a master oscillator within a quadrature oscillator utilizing injection-locking.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.

Abstract: According to some embodiments, unilateral coupling is provided for a quadrature voltage controlled oscillator. For example, a first voltage controlled oscillator may be provided with a 0 degree phase node and a 180 degree phase node A second voltage controlled oscillator may be provided with a 90 degree phase node and a 270 degree phase node. In addition, the first and second voltage controlled oscillators may be mutually coupled with substantially unilateral cascaded common-source common-gate amplifier coupling devices to create a quadrature voltage controlled oscillator.

Abstract: A quadrature oscillator includes a master tuned oscillator and two injection-locked slave tuned oscillators.

Abstract: The invention is directed to an arrangement for clock supply of a high bit-rate switching network structures in a digital narrowband switching system such as EWSD. A clock frequency signal (CLK2) traditionally generated with a crystal-controlled oscillator (11) as well as a corresponding frame clock signal (FMB2) are converted into low-voltage CMOS level signals and supplied to a system PLL (2) for high frequencies. This contains a discretely constructed VCO 6 with a sine oscillator that derives a higher-frequency signal from the supplied clock signal and converts this into a high-frequency clock signal (CLK92) of the output side. A feedback signal derived in this part serves as an input-side feedback signal for a phase detector (8) in low-voltage CMOS technology.

Abstract: In the particular embodiments of the invention described in the specification, a first signal generator produces a signal which changes in cycles having approximately straight line segments between maximum and minimum values at a first rate and a second signal generator produces a signal which changes in cycles having approximately straight line segments at a second rate which is an order of magnitude greater than the first rate. The maximum level of the second signal during any cycle is dependent upon the instantaneous signal level of the first signal and the minimum level of the second signal during any cycle is dependent upon a selected fraction of the instantaneous signal level of the first signal. The second signal is used to control the speed of a motor in a continuously changing random manner.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A voltage controlled oscillator is provided comprising a plurality of delay elements serially connected to form a ring and each element within the plurality of elements includes an input and output. The voltage controlled oscillator also includes a set of control elements where each control element within the set of control elements has an input connected to an input of a delay element within the set of delay elements and an output connected to an output of a different delay element within the plurality of delay elements. A control voltage is selectively applied to control elements within the set of control elements to vary the oscillating frequency and phase distribution in proportion to the control voltage.

Abstract: A system and method for synchronizing a plurality of synchronizable oscillators are disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.

Abstract: A waveform shaping circuit is provided so that the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency. An inverter which receives the clock pulses through an alternating current coupling capacitor is provided with a non-linear limiter element for limiting an amplitude of an output symmetrically on positive and negative sides thereof. A first current-limiting impedance and a second current-limiting impedance are connected between a power supply side terminal of the inverter and a power supply bus and between a grounding side terminal of the inverter and a grounding bus, respectively.

Abstract: There is a manufacturing limit on how small ceramic coaxial resonators can be produced, which leads to a limit on the frequency of resonance for these resonators. One technique to quadruple the effective frequency of a ceramic coaxial resonator is to couple four resonators into a ring configuration, each of the resonators having an electrical length of 90°. Further, each of the resonators has an amplifier coupled in parallel, these amplifiers having phase shifts approximately equal to 90° and further being controlled by a tuning voltage VTUNE. In operation, four oscillation signals are generated at the same frequency but out-of-phase by a factor of 90°. When combined, the resulting signal is an oscillation signal at four times the frequency of the original oscillation signals. At the same time, one of the oscillation signals used in the combination can be sampled and be used for feedback purposes within a PLL-FS.

Abstract: An oscillator includes four identical cells each producing a phase shift of 90 degrees. The output signal from one cell is applied to the input of the next cell, and with the cells looping back to themselves. Each cell includes a current amplifier and a parallel inductance-capacitance resonant circuit configured such that the output current from one cell is a fraction of the capacitive current of the parallel resonant circuit. This causes the 90.degree. phase shift between the input and output currents of each cell.

Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.

Abstract: A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.

Abstract: A tunable oscillator includes an input for receiving an input signal from a source of precision frequency such as a CMOS quartz crystal oscillator. The tunable oscillator converts the frequency of the input signal to a first current using a frequency to current converter. The current produced is proportional to a first capacitor, C1. The first current is replicated to produce a subsequent current using a current mirror structure. The subsequent current is then used to generate a periodic signal using a current to frequency converter. The output frequency of the current to frequency converter is inversely proportional to a second capacitor, C2. As such the output frequency of the tunable oscillator is tunable by changing the value of the capacitance ratio C1/C2. The invention is suitable for applications that require a precision tunable source of frequency such as automated test equipment (ATE) and electrical instrumentation.

Abstract: A phase-locked oscillation circuit, which minimizes phase fluctuation of an output clock signal generated by the phase-locked oscillation circuit, is provided. A wavelet filter performs a wavelet converting operation over phase fluctuations of an input reference signal and output clock signal of a phase-locked oscillator. It separates the phase fluctuation into a periodic fluctuation component and a non-periodic fluctuation component, optimizes a gain of the phase-locked oscillator on the basis of the periodic fluctuation component, and optimizes power supply filters of the phase-locked oscillator on the basis of the non-periodic fluctuation component.

Abstract: In a multiphase output oscillator a number of serially coupled oscillator circuits is organized in a loop. Each particular oscillator circuit is coupled to its serial successor in the loop, to provide adjustment of the phase of an oscillation signal of the successor oscillator circuit dependent upon a difference between the phase of the oscillation signal in the successor and the phase of an oscillation signal in the particular oscillator circuit. None of the oscillator circuits will oscillate freely: as each oscillator will adjust its successor all the way around the loop. Indirectly, each oscillator circuit thus influences all of the other oscillator circuits and ultimately over itself. The multiphase output oscillator as a whole will oscillate in a collective mode of oscillation wherein all oscillator circuits oscillate at the same frequency. Successive oscillator circuits along the loop will oscillate at respective fractions of the full oscillation period delayed from each other.

Abstract: An apparatus and method are provided for increasing the Q-value of an oscillator so that a net gain in the stability of the oscillators is obtained. In the apparatus and method, a plurality of units, which each include a passive frequency-selective circuit and an active amplifier, are cascaded and the required isolation between the passive frequency-selective circuits is maintained by the active amplifier acting as a buffer. As a result, interaction and loading is prevented between the passive frequency-selective circuits so that the net gain in the stability of the oscillator is achieved because the Q-value of the oscillator is increased.

Abstract: Briefly, in accordance with one embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator. The digital-controlled oscillator includes an edge delay oscillator being adapted to produce digital oscillator pulses in response to digital clock pulses, each of the oscillator pulses having a rising edge and a falling edge. The edge delay oscillator is further adapted to delay at least one of the oscillator pulse edges in response to a delay signal. In accordance with another embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator, the oscillator including a clock having a substantially predetermined frequency. The oscillator is adapted to produce a digital output signal comprising a series of digital output pulses.

Abstract: A cascaded magnetron device has an elongate cathode shank extending along its axis and a series of tubular anode elements placed end to end in a linear cascade surrounding the cathode shank along at least part of its length. Each adjacent pair of anode elements is separated by a conductive, annular pin down disc, and the cathode shank has a series of spaced bands of field emitting material separated by non-emitting regions, each band being located within a respective one of the anode elements and spaced inwardly from the ends of that element. Suitable power inputs and magnetic field generators are provided for generating electron emission and oscillation in the interaction zone between each emitting band and the anode element surrounding that band, and suitable extraction devices are provided for extracting power from each of the interaction zones, the arrangement producing phase-locking of the cascaded magnetron bodies.

Abstract: Directly mixing synchronous receiver having an RF input (1) and a first signal path (S1) which is coupled thereto and which incorporates a first synchronous demodulator (3) and a first low-pass filter (4), and having a carrier regeneration circuit including a first phase-locked loop (Q) incorporating in a loop configuration a first phase detector (5) which is coupled to the RF input (1), a first loop filter (6) and a first voltage-controlled tuning oscillator (8) an output of which is coupled to the first phase detector (5), on the one hand, and to the first synchronous demodulator (3) via a phase shift circuit, on the other hand, for a direct demodulation of an RF reception signal to the frequency baseband. The local mixing carrier required for the direct synchronous demodulation should be accurately in phase or in antiphase with the carrier of a desired RF reception signal to be demodulated.

Abstract: A reference signal from a reference signal source is supplied to a frequency transformer and a side band signal generator. The frequency transformer is formed mainly by up-converters and produces a frequency m times as high as the frequency f.sub.s of the reference signal. The side band signal generator outputs signals of base and harmonic frequencies f.sub.s, 2f.sub.s, 3f.sub.s, . . . and nf.sub.s (where n is less than m) and produces less phase noise than does the frequency transformer. The outputs of the frequency transformer and the side band signal generator are frequency mixed by a frequency mixer, and one frequency component in the frequency-mixed output is selected by a variable filter.

Abstract: A coherent array of Josephson oscillators is provided. Individual hysteresis-free Josephson junctions are longitudinally arranged in a line and have such a spacing as to substantially eliminate quasiparticle interactions. To provide a common frequency of operation, equal and opposite dc voltages are produced in adjacent pairs of the Josephson junctions by an arrangement of interlocking dc SQUID's (Superconductive Quantum Interference Device) connected to transversely extending biasing leads. Phase coherence for the array is provided by a rf current circulating in an inductive feedback path that loops between the ends of the array.

Abstract: A coherent array of Josephson oscillators is provided. Individual hysteresis-free Josephson junctions are longitudinally arranged in a gap of a central conductor in a line and have such a spacing as to substantially eliminate quasiparticle interactions. To provide a common frequency of operation, equal and opposite dc voltages are produced in adjacent pairs of the Josephson junctions by an arrangement of interlocking dc SQUID's (Superconductive Quantum Interference Device) connected to the longitudinal central conductor using microwave bias tees. Phase coherence for the array is provided by a rf current circulating in an inductive feedback path that loops between the ends of the array.

Abstract: An oscillator includes four identical cells each producing a phase shift of 90 degrees. The output signal from one cell is applied to the input of the next cell, and with the cells looping back to themselves. Each cell includes a current amplifier and a parallel inductance-capacitance resonant circuit configured such that the output current from one cell is a fraction of the capacitive current of the parallel resonant circuit. This causes the 90° phase shift between the input and output currents of each cell.