Frequency Dividers Patents (Class 331/51)
  • Patent number: 9287880
    Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 15, 2016
    Assignee: RAMBUS INC.
    Inventors: Marko Aleksic, Brian S. Leibowitz
  • Patent number: 9018987
    Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhirup Lahiri
  • Patent number: 8854091
    Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 7, 2014
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Farshid Aryanfar, Mohammad Hekmat, Reza Navid
  • Patent number: 8786328
    Abstract: An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Swaminathan Sankaran, Sudipto Chakraborty, Per T. Roine
  • Patent number: 8723609
    Abstract: A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 13, 2014
    Assignee: Idustrial Technology Research Institute
    Inventors: Chih-Hsiang Chang, Nai-Chen Cheng, Yu Lee, Ching-Yuan Yang
  • Patent number: 8704603
    Abstract: A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscillating frequency. In one example, the ILO is part of a quadrature divider that can lock onto a Phase-Locked Loop (PLL) output signal in a wide frequency band while achieving lower power consumption and lower phase noise than a differential latch type divider. The ILO is tuned by disabling a Voltage-Controlled Oscillator (VCO) from driving the ILO, adjusting the natural oscillating frequency, making a measurement indicative of the natural oscillating frequency, and determining whether the measurement is within a predetermined range. If the measurement is below the predetermined range, capacitances of resonators within the ILO are decreased, whereas if the measurement is above the predetermined range, capacitances of the resonators are increased.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: April 22, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Mazhareddin Taghivand, Jeongsik Yang
  • Patent number: 8698570
    Abstract: A passive frequency divider in a CMOS process. More specifically, an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. For example, one embodiment is a 20 GHz frequency divider utilizing a CMOS varactor and made in a 0.13 ?m CMOS process. In this embodiment: (i) without any dc power consumption, 600 mV differential output amplitude can be achieved for an input amplitude of 600 mV; and (ii) the input frequency ranged from 18.5 GHz to 23.5 GHz with varactor tuning. In this embodiment, the output phase noise is almost 6 dB lower than that of the input signal for all offset frequencies up to 1 MHz. Also, a resonant parametric amplifier with a low noise figure (NF) by exploiting the noise squeezing effect.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 15, 2014
    Assignee: Cornell University
    Inventors: Ehsan Afshari, Wooram Lee
  • Patent number: 8615202
    Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: December 24, 2013
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique SA—Recherche et Development
    Inventor: David Ruffieux
  • Patent number: 8204154
    Abstract: A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: June 19, 2012
    Assignee: Qualcomm Incorporated
    Inventors: ByungWook Min, Chan Hong Park
  • Patent number: 8013681
    Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: September 6, 2011
    Assignee: Harris Corporation
    Inventor: Kenneth Beghini
  • Patent number: 7961057
    Abstract: An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: June 14, 2011
    Assignee: Mediatek Singapore Pte Ltd
    Inventors: Beng Hwee Ong, Minjie Wu, Wee Liang Lien, Chang-Fu Kuo
  • Patent number: 7952438
    Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 31, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon
  • Patent number: 7941115
    Abstract: A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: May 10, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Sankaran Aniruddhan, Bo Sun, Arun Jayaraman, Gurkanwal Singh Sahota
  • Patent number: 7808295
    Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Shiro Sakiyama, Akinori Matsumoto, Takashi Morie, Shiro Dosho, Yusuke Tokunaga
  • Patent number: 7724096
    Abstract: Aspects of a method and system for signal generation via a PLL with undersampled feedback are provided. In this regard, the output of a VCO may clock a DDFS to generate a sampling frequency, and the output of the VCO may be undersampled at the sampling frequency to generate a feedback signal for controlling the VCO. Additionally, a control word for controlling the DDFS may be generated, and may be based on a phase difference between the feedback signal and a reference signal. The sampling frequency may be determined such that an aliasing product of the undersampling occurs at a frequency of the reference signal. Also, the feedback signal may be filtered to select a desired aliasing product from a plurality of aliasing products. The output of the VCO may be frequency divided before clocking the DDFS, and a divisor of the division may be programmatically controlled.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: May 25, 2010
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Rofougaran
  • Patent number: 7705686
    Abstract: An injection-locked frequency divider includes a ring oscillator, a signal injection circuit, a first adjustable load circuit and a second adjustable load circuit. The ring oscillator generates an oscillation signal according to a differential signal outputted by the signal injection circuit. According to an adjustable voltage, the first and second adjustable load circuits can respectively change equivalent impedances of the first adjustable load circuit and the second adjustable load circuit so that a free-running frequency of the oscillation signal of the ring oscillator is adjusted and an injection-locked frequency range of the injection-locked frequency divider is expanded.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: April 27, 2010
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Yun-Hsueh Chuang, Shao-Hwa Lee
  • Patent number: 7671640
    Abstract: A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-dividing function. The proposed frequency divider circuit comprises an injection-locked oscillator (ILO) circuit module and a pair of buffer-stage circuits, wherein the ILO circuit module further includes a signal-injection circuit, a cross-coupled switching circuit, and a variable-capacitance tuning circuit. The proposed circuit architecture is characterized by the circuit arrangement of a direct-injection architecture and an inductive-coupling feedback architecture by coupling the inductive elements of the buffer-stage circuits to the inductive elements of the variable-capacitance tuning circuit in the ILO circuit module.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: March 2, 2010
    Assignee: National Taiwan University
    Inventors: Wei-Yang Lee, Jean-Fu Kiang
  • Publication number: 20090295491
    Abstract: A carrier generator for generating a carrier at a frequency of interest in a wireless communications system comprises an oscillator exhibiting a first impedance, the oscillator comprising an energy storage tank configured to generate a periodic signal, the energy storage tank including at least one inductor and at least one capacitor, and an amplifier coupled with the energy storage tank, the amplifier being configured to amplify an amplitude of the periodic signal, an antenna exhibiting a second impedance smaller than the first impedance, and a network coupled between the oscillator and the antenna, the network including at least one inductor or at least one capacitor and being configured to provide a third impedance such that a resultant impedance of the second impedance and the third impedance as viewed from the oscillator toward the antenna is large enough to facilitate the oscillator to generate the carrier at the frequency of interest.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Applicant: FAVEPC, INC.
    Inventors: Chun-Liang Tsai, Shao-Chang Chang
  • Patent number: 7570124
    Abstract: A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: August 4, 2009
    Assignee: Broadcom Corporation
    Inventors: Nikolaos C. Haralabidis, Nikolaos A. Kanakaris
  • Patent number: 7557664
    Abstract: An injection-locked frequency divider (ILFD) can go beyond simple frequency division by an even number. In one embodiment, another differential pair of transistors is added to convert the injection signal into differential currents, which are mixed in the original transistor pair such as that of the conventional ILFD shown above. In another, a double-balanced ILFD structure includes multiple ILFD's which are independently tunable to allow phase differences other than quadrature.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 7, 2009
    Assignee: University of Rochester
    Inventor: Hui Wu
  • Patent number: 7538625
    Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: May 26, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael David Cesky, James David Strom
  • Patent number: 7508273
    Abstract: A divide-by-n process is effected via a scale-by-four/n process followed by a divide-by-four process. A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By incorporating a terminal divide-by-four process, quadrature output signals are easily provided. A divide-by-three quadrature divider effects the scale-by-4/n process via a selection of every third quadrature clock phase, and the quadrature output of the divide-by-four process provides the control signals to effect this every-third clock phase selection.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: March 24, 2009
    Assignee: NXP B.V.
    Inventor: William Redman-White
  • Patent number: 7495516
    Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: February 24, 2009
    Inventor: Christopher Julian Travis
  • Patent number: 7463547
    Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: December 9, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
  • Patent number: 7313369
    Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: December 25, 2007
    Assignees: Renesas Technology Corp., TTPcom Limited
    Inventors: Hirotaka Oosawa, Jiro Shinbo, Noriyuki Kurakami, Masumi Kasahara, Robert Astle Henshaw
  • Patent number: 7233211
    Abstract: A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each divider unit includes a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency. Each divider unit also includes a resistor bank coupled between a voltage source and the frequency divider unit, and a current stirring unit for supplying current to the frequency divider unit. The resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are variable depending on the input frequency.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: June 19, 2007
    Assignee: Broadcom Corporation
    Inventor: Qiang (Tom) Li
  • Patent number: 7216249
    Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: May 8, 2007
    Assignee: Rohm Co., Ltd.
    Inventors: Masayu Fujiwara, Masaki Onishi
  • Patent number: 7084712
    Abstract: A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 1, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Masayu Fujiwara
  • Patent number: 6856172
    Abstract: A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or both set and reset input ports of the set-reset flip-flop. The set-reset flip-flop and shift register are clocked by the clock signal. The output signal of the circuit may be taken at any output port of the shift register or the set-reset flip-flop. In one embodiment, the state of the shift register is represented by the set of Boolean values Q<i>, i=1, 2, . . . , N?1, and the combinational logic provides to the set input port of the set-reset flip-flop the Boolean value {Q#<M?1><Q#<M?2>. . .
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: February 15, 2005
    Assignee: Intel Corporation
    Inventor: Mel Bazes
  • Publication number: 20040263263
    Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.
    Type: Application
    Filed: February 17, 2004
    Publication date: December 30, 2004
    Applicant: Berkana Wireless, Inc.
    Inventor: Beomsup Kim
  • Patent number: 6441656
    Abstract: A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Gin S. Yee, Drew G. Doblar
  • Patent number: 6356123
    Abstract: A non-integer frequency divider that is capable of dividing an original clock frequency by a non-integer number into a desired target clock frequency. By this non-integer frequency divider, a phase-shifting circuit is first used to convert the original clock frequency into a predetermined number of phase-shifted versions of the original clock frequency with a predetermined phase difference. Then, a plurality of edge-triggered clock signal generators are used to generate a plurality of edge-triggered signals whose rising and falling edges are synchronized with the original clock frequency and its phase-shifted versions. Finally, a synthesis circuit is used to synthesize the edge-triggered signals into an output signal serving as the intended target clock frequency.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: March 12, 2002
    Assignee: Via Technologies, Inc.
    Inventors: Shan-Shan Lee, Jyhfong Lin
  • Patent number: 6285063
    Abstract: The resonant circuit has at least one resonant body of a semiconductor material anchored on the surface of a semiconductor substrate, at least one first electrode being arranged at said semiconductor material, and at least one second electrode. The first and second electrode are arranged lying opposite one another. When an AC-superimposed DC voltage is applied between the first and the second electrode, the resonant body is excited to mechanical oscillation by the DC voltage. In particular, the resonant circuit can be monoically integrated in electronic circuits.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: September 4, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Armin Splett, Dieter Emmer
  • Patent number: 6269051
    Abstract: Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: July 31, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Funaba, Yoji Nishio, Yuichi Okuda, Yoshinobu Nakagome
  • Patent number: 6236703
    Abstract: A delta-sigma modulator having a dead-zone quantizer and an error shaping digital filter clocked by a signal which is periodic at the frequency of the reference. A dead-zone quantizer provides quantization of a high resolution digital word to a low resolution digital word with three or a higher odd number of possible output levels and with an output of zero for an input near the center of the normal input range. The delta-sigma modulator is used in a fractional-N divider. The fractional-N divider is used in a fractional-N frequency synthesizer.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: May 22, 2001
    Assignee: Philsar Semiconductor Inc.
    Inventor: Thomas A. D. Riley
  • Patent number: 6091306
    Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: July 18, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Josef Fenk
  • Patent number: 6020790
    Abstract: In a method of calibration of a voltage controlled oscillator (VCO), the VCO (100) provides an output signal which is used to drive a dividing oscillator (10) such as a relaxation oscillator (RO). The RO has at least two states, one in which the RO provides an output signal which has a first frequency that is related to the VCO output signal by a first ratio (e.g. 1/N) and one in which the relaxation oscillator provides a RO output signal which has a second frequency that is related to the VCO output signal by a second ratio (e.g. 1/(N+1)). By measuring the first and second frequencies (and knowing the relationship between the first and second ratios), the VCO frequency is calculated and stored (110). Several VCO frequencies can be calculated and stored for several applied voltages. As a result the VCO can be driven to any selected frequency in the calibrated range and can be used to provide an injection frequency for a radio.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: February 1, 2000
    Assignee: Motorola, Inc.
    Inventors: Irvin R. Jackson, Paul Linsay, Thomas A. Freeburg
  • Patent number: 5818302
    Abstract: A voltage-controlled oscillator generates an oscillation signal having a frequency corresponding to a control signal. A phase comparator detects a phase difference between a reference signal and a frequency-divided signal derived from the oscillation signal and generates a phase difference signal. A control circuit, which comprises an A/D converter, a high-speed processor, and a D/A converter, generates a control voltage so as to reduce a time-dependent change in the phase difference signal to synchronize the oscillation signal with the reference signal. When the synchronization of the oscillation signal with the reference signal is completed, the control circuit secures a control voltage at the time time-dependent change in the phase difference signal becomes equal to or smaller than a phase difference stored in a flash ROM.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: October 6, 1998
    Assignee: NEC Corporation
    Inventors: Shigeru Otsuka, Kanada Nakayasu
  • Patent number: 5801589
    Abstract: A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.
    Type: Grant
    Filed: January 9, 1997
    Date of Patent: September 1, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Tajima, Kenji Itoh, Shuji Nishimura, Masayuki Doi, Akio Iida
  • Patent number: 5787135
    Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: July 28, 1998
    Assignee: LSI Logic Corporation
    Inventor: Iain Clark
  • Patent number: 5319802
    Abstract: In order to increase the sensitivity and range of a system for the exchange of data by microwaves between a fixed station, or reader, and a mobile station, or badge, the modem of the badge includes an oscillator. A single transistor works, under a first bias, as a detector of the wave transmitted by the reader and demodulates this wave, and then, under a second bias, it works as an oscillator and modulates the response transmitted by the badge. Applications to the exchange of data at a distance.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: June 7, 1994
    Assignee: Thomson Composants Microondes
    Inventors: Marc Camiade, Veronique Serru, Dominique Geffroy
  • Patent number: 5245593
    Abstract: A clock producing apparatus for a D/A converter switches the clocks in accordance with the inputted sampling frequencies. A deterioration in the S/N caused by unnecessary spectra which are caused by the inputting of different sampling frequencies is prevented.The selecting operation is effected by the selecting circuit so as to obtain the selected input sampling frequencies, and at the same time, the clock signals are prevented from being inputted to the frequency dividing circuits corresponding to the input sampling frequencies which are not selected. Therefore, unnecessary spectra are prevented from being generated.
    Type: Grant
    Filed: January 8, 1991
    Date of Patent: September 14, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kazunori Yamate
  • Patent number: 5089717
    Abstract: An integrated semiconductor device including a frequency divide-by-two circuit comprising an inverter stage and a switching transistor (T2) which is controlled by a microwave input signal (E). The divider circuit includes an oscillator stage in that the inverter stage is at least equipped with a reactive element which in combination with the inverter stage forms a negative resistant network. The switching transistor is connected in parallel with this reactive element and the transmit time .tau..sub.0 of the switch is less than the transit time .tau..sub.2 of a signal propagating through the reactive element.
    Type: Grant
    Filed: May 16, 1991
    Date of Patent: February 18, 1992
    Assignee: U.S. Philips Corporation
    Inventors: Patrice Gamand, Bertrand Gabillard
  • Patent number: 5008571
    Abstract: A frequency divider includes a power divider which receives an input signal and divides the input signal into first and second signals. A frequency doubler receives the first signal and provides a third signal having a frequency which is twice the frequency of the first signal. A hybrid junction sums the second and third signals and provides a fourth signal which corresponds to the sum of the second and third signals and which has a low frequency modulation component which is substantially equal to one-half the frequency of the input signal, as well as a high frequency carrier component. An envelope detector and a band-pass filter, connected in series, receive the fourth signal and provide an output signal corresponding to the low frequency component of the fourth signal, which low frequency component is substantially equal to one-half the frequency of the input signal.
    Type: Grant
    Filed: June 29, 1989
    Date of Patent: April 16, 1991
    Assignee: AIL Systems, Inc.
    Inventor: Ronald M. Rudish
  • Patent number: 4868514
    Abstract: This disclosure concerns digital correction of oscillator drift by providing phase alignment between two clock signals running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths of a variable delay path formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator. The product of phase comparison controls a digital delay selector to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signals. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal.
    Type: Grant
    Filed: November 17, 1987
    Date of Patent: September 19, 1989
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Azevedo, Charles A. Corchero, Donald J. Lang, Gilbert R. Woodman, Jr.
  • Patent number: 4698619
    Abstract: An alarm message generation and broadcast system having supervision including an alarm message generation circuit for generating an alarm message, an output for receiving the alarm message so that the alarm message can be broadcast in response to an alarm event; and a supervision circuit connected to the alarm message generation circuit and responsive to the alarm message for providing a trouble signal when the alarm message is not properly received by the supervision circuit.
    Type: Grant
    Filed: May 7, 1984
    Date of Patent: October 6, 1987
    Assignee: Honeywell Inc.
    Inventor: Phillip J. Loeb
  • Patent number: 4631500
    Abstract: A microwave frequency divider circuit. The frequency divider comprises a nonlinear amplifier including input and output ports for amplifying signals applied to the input port. The amplifier exhibits a nonlinear transconductance characteristic between its input and output ports. The amplifier input port is adaptable to receive a first signal having a frequency f.sub.l. The frequency divider further includes a feedback network coupled between the amplifier output and input ports to couple a second signal having a frequency f.sub.o appearing at the amplifier output port back to the input port. The first and second signals combine at the amplifier input port to modulate the nonlinear transconductance of the amplifier such that said first and second signals are mixed together and amplified. The circuit regeneratively oscillates such that the frequency f.sub.o equals a frequency f.sub.l /2. The frequency f.sub.l of the first signal is thus divided by the circuit.
    Type: Grant
    Filed: April 24, 1984
    Date of Patent: December 23, 1986
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Christen Rauscher
  • Patent number: 4434696
    Abstract: Equal-ratio scales offer a choice of semitone accuracies ranging from a thousandth cent to a millionth of a cent, any note of which may be selected as a reference for a fully chromatic just-intonation scale whose ratios are absolute and may be modulated in all 15 tonalities, i.e., to signature keys in seven sharps and seven flats.
    Type: Grant
    Filed: November 20, 1981
    Date of Patent: March 6, 1984
    Inventor: Harry Conviser
  • Patent number: 4357580
    Abstract: A signal of frequency value F.sub.IN is coupled to a discriminator and to one terminal of a voltage controlled oscillator (VCO) tuned to operate at a range of frequencies about F.sub.IN .div.N where N is a nonunity positive integer. The discriminator produces a voltage proportional to frequency F.sub.IN which is scaled and applied to a control terminal of the VCO to cause it to be tuned to approximately F.sub.IN .div.N. The signal of frequency F.sub.IN applied to the VCO causes it to be injection locked to frequency F.sub.IN .div.N.
    Type: Grant
    Filed: August 21, 1980
    Date of Patent: November 2, 1982
    Assignee: RCA Corporation
    Inventor: Daniel D. Mawhinney
  • Patent number: 4347484
    Abstract: A phase-locked loop circuit for use in locking onto a sub-harmonic of the frequency of a reference source. An oscillator operating at the sub-harmonic frequency is injection-synchronized to the primary voltage controlled oscillator of the phase-locked loop, thereby causing it to function as a divider. The injection-synchronized oscillator can be controlled by a loop control signal generated by the loop's phase detector and loop filter.
    Type: Grant
    Filed: June 2, 1980
    Date of Patent: August 31, 1982
    Assignee: General Electric Company
    Inventor: Johannes J. Vandegraaf