Ring Oscillators Patents (Class 331/57)
  • Patent number: 11308791
    Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 19, 2022
    Assignee: INTEL CORPORATION
    Inventors: Satheesh Chellappan, Srikanth Potluri
  • Patent number: 11296712
    Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: April 5, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Eitan Rosen, Oded Norman
  • Patent number: 11296693
    Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
  • Patent number: 11295198
    Abstract: To realize a reservoir computing system in which the reservoir is configured to be suitable for various learning targets, provided is a self-organizing reservoir computing system, including an input layer that outputs an input layer signal corresponding to input data; a reservoir layer that includes therein a nonlinear signal path using physical resonance phenomena and is operable to output an inherent reservoir layer signal in response to the input layer signal; and an output layer that outputs output data corresponding to the reservoir layer signal. Also provided is a self-organizing method.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Naoki Kanazawa
  • Patent number: 11274976
    Abstract: A temperature sensor supplying a measurement signal varying linearly to within 10% as a function of the temperature at least over a temperature range, including an oscillator supplied by a supply voltage and supplying a first oscillating signal, said oscillator including first MOS transistors, the voltage at each internal node of the oscillator having a dynamic range equal to the supply voltage, the measuring signal corresponding to the supply voltage.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 15, 2022
    Assignee: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Franck Badets, Maxime Cozzi
  • Patent number: 11263380
    Abstract: A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 1, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Zhen Tang, Lei Pan, Miranda Ma
  • Patent number: 11228303
    Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 11211934
    Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
  • Patent number: 11171632
    Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Domenico Tripodi, Luca Giussani, Simone Ludwig Dalla Stella
  • Patent number: 11081973
    Abstract: An inverter is presented. The inverter may be configured to receive an input voltage at an input node of the inverter, and to generate an output voltage at an output node of the inverter. The inverter may comprise a first transistor coupled between a supply node and the output node of the inverter. Further, the inverter may comprise a second transistor coupled between the output node of the inverter and a reference node. The input node of the inverter may be coupled to a back-gate of the first transistor and to a back-gate of the second transistor.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 3, 2021
    Assignee: Dialog Semiconductor B.V.
    Inventors: Marinus Wilhelmus Kruiskamp, Petrus Hendrikus Seesink
  • Patent number: 11075602
    Abstract: In one embodiment, an apparatus includes: a bias circuit having a replica circuit, the bias circuit to generate an oscillator current that is proportional to a variation of the replica circuit; an oscillator circuit coupled to the bias circuit to receive the oscillator current and generate a plurality of signals using the oscillator current; and a waveform shaper circuit coupled to the oscillator circuit to receive the plurality of signals and generate at least one clock signal from the plurality of signals.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 27, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Pio Balmelli
  • Patent number: 11070129
    Abstract: An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: July 20, 2021
    Assignee: Oregon State University
    Inventors: Soumya Bose, Matthew Johnston, Tejasvi Anand
  • Patent number: 11038497
    Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Ji-Hwan Kim
  • Patent number: 11025234
    Abstract: Methods and systems for regulating supply voltage is described. In an example, a device can receive unregulated supply. The device can be connected to a ring oscillator and an integrated circuit. The device can be configured to regulate the unregulated supply to a first voltage. The device can be further configured to provide the regulated supply to the ring oscillator, where the ring oscillator operates with the regulated supply. The device can be further configured to, in response to a change in the regulated supply from the first voltage to a second voltage, adjust the changed regulated supply to return to the first voltage to cause the ring oscillator to operate with a constant regulated supply having the first voltage.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11005456
    Abstract: Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 11, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Minoru Kozaki
  • Patent number: 10998889
    Abstract: A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 4, 2021
    Assignee: Birad-Research & Development Company Ltd.
    Inventors: Joseph Shor, Natan Vinshtok-Melnik
  • Patent number: 10979049
    Abstract: A buffer circuit includes an input terminal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit is configured to increase a transition time between logical voltage levels of an output signal generated at the output terminal relative to a transition time between logical voltage levels of an input signal received at the input terminal, and the transition time of the output signal is based on a duration of a logic inversion of the input signal.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wan-Yen Lin, Yuan-Ju Chan, Bo-Ting Chen
  • Patent number: 10964379
    Abstract: Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 30, 2021
    Assignee: Arm Limited
    Inventors: Rainer Herberholz, George McNeil Lattimore, Amit Chhabra
  • Patent number: 10917076
    Abstract: A ring oscillator includes at least one oscillator stage having a first output and a second output and a start-up circuit. The start-up circuit includes a plurality of AC coupling capacitors receiving the first output and the second output, and a plurality of switches connected to the AC coupling capacitors. The start-up circuit is configured to provide a differential start-up voltage to at least one node of the oscillator using the plurality of switches and the AC coupling capacitors.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 9, 2021
    Inventors: Vishnu Kalyanamahadevi Gopalan Jawarlal, Tamal Das, Avneesh Singh Verma, Sanjeeb Kumar Ghosh
  • Patent number: 10903823
    Abstract: An apparatus for radio-frequency (RF) oscillation signal production is disclosed. In example implementations, an apparatus includes an oscillator. The oscillator includes multiple oscillation stages that are coupled together in series into a ring. A respective oscillation stage of the multiple oscillation stages includes a transconductance amplifier and a core oscillator. The transconductance amplifier is coupled to a preceding oscillation stage. The core oscillator is coupled to the transconductance amplifier and to a succeeding oscillation stage, with the core oscillator including at least one output node configured to provide a respective output signal. In some implementations, at least one capacitor is coupled across at least the transconductance amplifier. In some aspects, at least one transistor of the transconductance amplifier is implemented with a silicon-on-insulator metal-oxide-semiconductor (SOI MOS) device that includes at least one back-gate terminal.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: January 26, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yiwu Tang, Sujiang Rong
  • Patent number: 10897244
    Abstract: Apparatus and methods are described for voltage dependent delay. An example apparatus includes an oscillator including a delay circuit that is configured to provide an oscillating output signal has a delay based on a delay of the delay circuit. The delay of the delay circuit is based on a voltage it receives. For example, the delay of the delay circuit increases for an increasing received voltage and decreases for a decreasing received voltage. As a result, the oscillating output signal provided by the oscillator is based on the received voltage. For example, a frequency of the oscillating output signal decreases for increasing received voltage and increases for decreasing received voltage. Described in another way, the frequency of the oscillating output signal is relatively low for relatively high received voltage and relatively high for relatively low received voltage.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhi Qi Huang, Wei Lu Chu, Dong Pan
  • Patent number: 10868545
    Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po Chun Lu, Shao-Yu Wang
  • Patent number: 10862467
    Abstract: A system includes an oscillator comprising a first switch, a current source, a capacitor, and a comparator, the capacitor and the comparator coupled at a node. The system includes one or more delay buffers coupled to the comparator. The system includes a first inverter coupled to the one or more delay buffers. The system includes a first buffer coupled to the one or more delay buffers. The system includes a first coupling capacitor coupled to the first inverter and the first buffer via second and third switches, respectively. The system includes a second inverter coupled to the one or more delay buffers. The system includes a second buffer coupled to the one or more delay buffers. The system includes a second coupling capacitor coupled to the second inverter and the second buffer via fourth and fifth switches, respectively. The first and second coupling capacitors are coupled to the oscillator.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abhijit Kumar Das
  • Patent number: 10839120
    Abstract: A method for communication at the speed of light over an on-chip interconnect is disclosed. The method includes dividing an on-chip interconnect into a plurality of segments. Each of the plurality of segments includes a transmission line and a tapered buffer. The tapered buffer is connected to the transmission line. An input capacitance of the tapered buffer satisfies a capacitance condition. A driver resistance of the tapered buffer satisfies a resistance condition.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 17, 2020
    Assignee: SHARIF UNIVERSITY OF TECHNOLOGY
    Inventors: Amin Rassekh, Reza Sarvari, Sina Shahhosseini
  • Patent number: 10833659
    Abstract: A voltage sampling circuit arrangement comprises: an oscillator circuit portion arranged to produce a periodic oscillator output signal at an oscillation frequency dependent on a bias current provided thereto; a sampling circuit portion arranged selectively to connect an input terminal (Vin) to an output terminal (Vout) in response to an applied switching signal (Vswitch) derived from said oscillator output signal, wherein said sampling circuit portion has a current leakage dependent on temperature; and a biasing circuit portion arranged to provide said bias current to the oscillator circuit portion wherein said bias current is dependent on temperature.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: November 10, 2020
    Assignee: Nordic Semiconductor ASA
    Inventor: Werner Luzi
  • Patent number: 10826491
    Abstract: A control circuit of a load switch including a charge pump circuit, an oscillator, and a current signal generator is provided. The charge pump circuit generates a control signal according to a clock signal. The load switch is turned on or turned off according to the control signal. The oscillator generates the clock signal according to a control current. The current signal generator provides a resistor string to receive a power voltage. The resistor string of the current signal generator generates a sensed current or a sensed voltage according to the power voltage. The current signal generator generates the control current according to a reciprocal of the sensed current or a square of the sensed voltage. A frequency of the clock signal is negatively related to the power voltage.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: November 3, 2020
    Assignee: Excelliance MOS Corporation
    Inventors: Ming-Hung Chien, Pei-Ting Yang, Ching-Tsan Lee
  • Patent number: 10812054
    Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-yeop Choo, Woo-seok Kim, Tae-ik Kim
  • Patent number: 10796058
    Abstract: A platform design including a module black-box instance is loaded into computer hardware. Using the computer hardware, synchronous boundary crossings between a static region and the module black-box instance of the platform design are identified and objects of the platform design included in the synchronous boundary crossings are marked. Using the computer hardware, unmarked objects are removed from the platform design to generate a shell circuit design. A custom circuit design is implemented based on the shell circuit design and timing constraints corresponding to objects remaining in the shell circuit design.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 6, 2020
    Assignee: Xilinx, Inc.
    Inventors: Nicholas A. Mezei, Steven Banks, Meiwei Wu, Raymond Kong
  • Patent number: 10746781
    Abstract: A ring oscillator test circuit, includes an odd number of stages, where each stage includes a load and drive transistor connected in series at a common node. The common node of each stage is electrically connected to the drive transistor gate of the following stage, and the common node of the last stage is connected to the drive transistor gate of the first stage. A first voltage input connects to the drains of all the load transistors. A second voltage input connects to the gates of all of the load transistors. A reference voltage input connects to the sources of all of the drive transistors. At least one of the common nodes connects to a test output.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 18, 2020
    Assignee: Ariel-University Research and Development Company Ltd.
    Inventor: Joseph B. Bernstein
  • Patent number: 10742224
    Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 11, 2020
    Assignee: NVIDIA Corp.
    Inventors: Xi Chen, Sanquan Song
  • Patent number: 10734977
    Abstract: In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 4, 2020
    Assignee: SILICON LABORATORIES INC.
    Inventors: Wenhuan Yu, Abdulkerim L. Coban
  • Patent number: 10680618
    Abstract: An integrated circuit system is provided. The system includes a ring oscillator including a first plurality of logic gates connected in a ring configuration. The system also includes a second plurality of logic gates used to implement a heater to generate a controlled amount of heat. The second plurality of logic gates is also used to implement a temperature sensor to measure a temperature of the ring oscillator. The system further includes one or more logic circuits coupled to the heater and the temperature sensor. The one or more logic circuits are used to control the heater to heat the ring oscillator only until the temperature of the ring oscillator is one of a plurality of predefined temperatures, during or after which the ring oscillator starts and operate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 9, 2020
    Assignee: THE BOEING COMPANY
    Inventor: Laszlo Hars
  • Patent number: 10651732
    Abstract: Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Patent number: 10651857
    Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Andreas Roithmeier, Thomas Gustedt, Herwig Dietl-Steinmaurer, Christian Wicpalek
  • Patent number: 10637452
    Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Ji-Hwan Kim
  • Patent number: 10615785
    Abstract: Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shih-Wei Chou, Ying Duan, Abhay Dixit, Harry Huy Dang, Thomas Clark Bryan
  • Patent number: 10594303
    Abstract: A temperature sensor circuit may include a ring oscillator being enabled according to an enable signal and outputting a square wave signal with a first frequency, a divider dividing the first frequency of the square wave signal from the ring oscillator to generate a pulse signal with a second frequency, a counter counting a time interval of the pulse signal outputted from the divider according to an external clock to generate a count signal, a latch temporarily storing a value of the counter signal according to the pulse signal and outputting a digital code, and a supply voltage monitor being enabled according to the pulse signal, comparing a reference voltage to one or more comparison voltages and generating a switching logic signal. The reference voltage is kept at a substantially constant level when a level of a supply voltage changes.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 17, 2020
    Assignees: SK hynix Inc., University Of Seoul Industry Cooperation Foundation
    Inventors: Joongho Choi, Hyeondeok Jeon
  • Patent number: 10554209
    Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10547273
    Abstract: A temperature sensor has a first transistor with a gate voltage tied to maintain the first transistor in an off state with leakage current flowing through the transistor, the leakage current varying with temperature. A second transistor is coupled to the first transistor and receives a gate voltage to keep the second transistor in an on state. A current mirror mirrors the leakage current and supplies a mirrored current used to control a frequency of an oscillator signal varies with the mirrored current. The temperature of the first transistor is determined based the frequency of the oscillator signal.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 28, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ravinder Reddy Rachala, Stephen V. Kosonocky
  • Patent number: 10505525
    Abstract: An oscillator circuit (100) comprises a first tank circuit (T1) comprising an inductive element (L) and a capacitive element (C) coupled in series between a first voltage rail (14) and a first drive node (12). A feedback stage (F) is coupled to a first tank output (13) of the first tank circuit (T1) and to the first drive node (12). The feedback stage (F) is arranged to generate, responsive to a first oscillating tank voltage present at the first tank output (13), a first oscillating drive signal at the first drive node (12) in-phase with a first oscillating tank current flowing in the inductive element (L) and the capacitive element (C), thereby causing the oscillator (100) to oscillate in a series resonance mode of the inductive element (L) and the capacitive element (C).
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 10, 2019
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Pietro Andreani, Luca Fanori, Thomas Mattsson
  • Patent number: 10461722
    Abstract: A ring oscillator is configured with a multiple number of logic inverting circuits in a ring shape and generates multi-phase clock signals. A period measuring unit measures a period of a reference clock inputted thereto by the multi-phase clock signals of the ring oscillator and outputs a measured period as a period data value. A frequency spreading calculation unit calculates a frequency spreading command value in accordance with a frequency spreading rate, a frequency spreading period and the period data value of the period measuring unit, which are inputted. A pulse generation unit generates a clock pulse corresponding to the frequency spreading command value in accordance with a data value determined by addition of the frequency spreading command value to the period data value.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 29, 2019
    Assignee: DENSO CORPORATION
    Inventors: Kazuhiro Nagai, Takuya Harada
  • Patent number: 10380287
    Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dirk Meyer, Zhuo Li, Charles Jay Alpert
  • Patent number: 10367494
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 30, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • Patent number: 10324128
    Abstract: Provided are a method of testing semiconductor device and a system for testing semiconductor device. The method includes measuring a minimum operating voltage of each of a plurality of sample semiconductor devices and an operating frequency of corresponding ring oscillators included in each of the plurality of sample semiconductor devices, generating a model between the operating frequencies of the ring oscillators and the minimum operating voltages of the sample semiconductor devices, measuring an operating frequency of ring oscillators included in a target semiconductor device, and determining a target minimum operating voltage of the target semiconductor device based on the operating frequency of the ring oscillators of the target semiconductor device and the model.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Oh Song Kwon
  • Patent number: 10320368
    Abstract: A ring oscillator circuit includes a plurality of first delay circuits each including X first delay elements, and a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X?1.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 11, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Koichi Hatanaka
  • Patent number: 10276257
    Abstract: A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. The semiconductor device may include a second oscillation signal generation circuit for generating a second oscillation signal. The second oscillation signal generation circuit may be provided with a test voltage. The test voltage may be generated based on a burn-in test signal.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 30, 2019
    Assignee: SK hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 10234336
    Abstract: A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged, which may reduce the impact that the noise has on the frequency of the ring oscillator output signal. In some embodiments, a regulator may supply a regulated voltage to the ring oscillator. The regulator may reduce the impact of the noise for low frequency components of the noise, while the frequency divider may reduce the impact for high frequency of the noise.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Bhavin Odedara, Jayanth Mysore Thimmaiah
  • Patent number: 10156605
    Abstract: An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: December 18, 2018
    Assignee: Semitronix Corporation
    Inventors: Weiwei Pan, Yongli Liu, Xu Ouyang, Yongjun Zheng, Zheng Shi, Lili Li
  • Patent number: 10110239
    Abstract: During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 23, 2018
    Assignee: Oracle International Corporation
    Inventors: Guanghua Shu, Frankie Y. Liu, Suwen Yang, Ziad Saleh Shehadeh, Eric Y. Chang
  • Patent number: 10075131
    Abstract: A voltage controlled oscillator (VCO) and a method of operating the VCO are disclosed. The VCO includes an inductor device, a capacitor device coupled in parallel with the inductor device through first and second nodes, and a pair of cross-coupled transistors coupled in parallel with the inductor device and the capacitor device through the first and second nodes. At least one of the pair of cross-coupled transistor includes a plurality of sub transistors coupled in parallel. The sub transistors are individually switchable to adjust current drive capability of each of the sub transistors. Each of the sub transistors includes a first gate and a second gate.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Keith A. Jenkins