Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Abstract: The invention provides a power system for monitoring a working environment of a monitored circuit and adjusting a working voltage of the monitored circuit includes: a power circuit, a voltage-controlled oscillator and a counter. The power circuit is configured to output the working voltage to the monitored circuit through a power supply path. The voltage-controlled oscillator is disposed in or around the monitored circuit and is electrically connected to the power supply path and a ground path to which the monitored circuit is electrically connected, and is configured to output an oscillation frequency in accordance with a signal variation on the power supply path and the ground path. The counter is electrically connected to the voltage-controlled oscillator and is configured to generate a counting number signal in accordance with the oscillation frequency and a synchronizing signal, thereby adjusting the working voltage outputted to the monitored circuit.

Abstract: There is provided an oscillation device includes multiple delay elements that each sequentially delay an input signal, and return at least some of the delayed signals to a preceding stage to generate an oscillation signal. The oscillation device further includes a first control terminal that inputs, to the multiple delay elements, a direct current control signal for collectively controlling direct current voltage levels of the input signal to be input in plural number to the multiple delay elements.

Abstract: In accordance with an embodiment, a method includes: producing a set of delayed replicas of a reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of a clock signal having a clock period; selecting based on edge detecting signals in the set of edge detecting signals a delayed replica in the set of delayed replicas having a distance from the clock signal edge that is shorter than the distance from the clock signal edge of any other delayed replica in the set of delayed replicas.

Abstract: In an analog-to-digital converter, primary latches respectively latch an output of a corresponding one of delay units at respective sample times of different first clocks. The primary latches include at least first and second primary latches, and secondary latches include at least first and second secondary latches respectively corresponding to the at least first and second primary latches. Each of the at least first and second secondary latches is configured to latch, at a sample time of a common second clock, an output of a corresponding one of the at least first and second primary latches. The common second clock is based on at least one of the first clocks.

Abstract: Disclosed are a method and device for detecting system failure, a computer device, and a storage medium. The method includes obtaining, when a system to be detected is powered on or off, a real-time voltage oscillation signal acquired by a voltage sensor arranged in a detection circuits of the system. The detection circuit is a circuit where a source and drain of a switching device in the system are located. A degradation trend of the system is determined according to the real-time voltage oscillation signal and a reference voltage oscillation signal corresponding to the detection circuit of the system. A failure detection for the system is performed according to the degradation trend of the system.

Abstract: A switching circuit comprises a main switch element having a gate as a control input; and a ring oscillator connected as a driver circuit to the gate to drive the main switch via the gate. The basic circuit is used to build various components which have the property that they can work at very high frequencies.

Abstract: Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.

Abstract: Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.

Abstract: A system and method for detecting the connectivity of an absence of voltage detector to the source of power to be detected has a first terminal wire connected to a first terminal and a second terminal wire also connected to the first terminal. An RF signal is placed on the first terminal and then its presence is detected on the second signal wire. This method and system can also be placed on each phase of a three phase system.

Abstract: There is provided an oscillator, having an input terminal (In) and an output terminal (Out), comprising a first signal delay circuit (104a-d), having a first voltage response characteristic, configured to provide a predetermined first propagation delay; a second signal delay circuit (104e, 108, 110), having a second voltage response characteristic that is inversely correlated to said first voltage response characteristic, operatively coupled with said first signal delay circuit and configured to provide a predetermined second propagation delay, and wherein said predetermined first propagation delay and said predetermined second propagation delay are temporally matched, so as to generate an oscillating output signal (Out) of a predetermined frequency.

Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Abstract: An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

Abstract: A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

Abstract: Methods, systems, and devices for degradation signaling for a memory device are described. In one example, a method in accordance with the described techniques may include monitoring, at a memory device, an operational characteristic of the memory device. For example, the threshold voltage of one or more transistors within the memory device may be monitored. The memory device may identify a degradation of the memory device based at least in part on the monitored operational characteristic. Based on identifying the degradation, the memory device may signal, to a host device, an indication of the degradation of the memory device.

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.

Abstract: A controlling circuit for ring oscillator is provided. A first transistor and a second transistor of a first conductive type are coupled in series and between a node and a first power source. A third transistor and a fourth transistor of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series. Gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a base station, information identifying a resource allocation for an uplink transmission of a transport block over multiple slots. The UE may transmit, to the base station, at least a portion of coded bits corresponding to the transport block based at least in part on a different uplink transmission being scheduled within the uplink transmission of the transport block over the multiple slots. Numerous other aspects are described.

Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Abstract: A crystal-free wireless device includes a frequency calibration module and a local radio frequency (RF) oscillator having a first frequency and configured to communicate with the frequency calibration module. The crystal-free wireless device also includes a relaxation ring oscillator configured to communicate with the frequency calibration module. The relaxation ring oscillator is further configured to receive a calibration signal or periodic radio frequency packets from a wireless network and provide a reference signal to the frequency calibration module. The relaxation ring oscillator is a crystal-free oscillator. The frequency calibration module is configured to generate a calibration signal that is fed back through a Frequency Locked Loop (FLL) to the local RF oscillator to calibrate the local RF oscillator. The calibrated local RF oscillator is configured to generate a clock signal.

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.

Abstract: An oscillation circuit includes: a power supply generation module and an oscillator. The power supply generation module is configured to generate a positive temperature coefficient voltage based on a positive temperature coefficient current; and the positive temperature coefficient voltage serves as a power supply of the oscillator. The oscillator includes: a first ring topological structure and a second ring topological structure. The first ring topological structure is formed by a plurality of first inverters connected end to end and configured to transmit an oscillation signal at a first transmission speed; and the second ring topological structure is formed by a plurality of second inverters connected end to end and configured to transmit the oscillation signal at a second transmission speed. The first ring topological structure is electrically connected with the second ring topological structure, and the second transmission speed is less than the first transmission speed.

Abstract: Injection locked resonator-based oscillators in accordance with various embodiments of the invention are described. An embodiment includes an injection locked resonator-based oscillator, that includes: an amplifier, a feedback circuit, a delayed locked loop (DLL), an off-chip high-frequency resonator that generates a resonance frequency, a switch connected to a power source Vdd, and a voltage-controlled oscillator (VCO), where an input to the amplifier is connected to both the high-frequency resonator and the DLL to lock a signal, where an output from the amplifier is connected to the feedback circuit that is provided back to the high-frequency resonator.

Abstract: Integrated circuit, comprising at least one ring oscillator including a succession of inverters looped back to form the ring, the at least one oscillator being intended to operate at a desired output frequency and configured so that the inverter transistors operate in or near their temperature inversion zone.

Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes.

Abstract: To realize a reservoir computing system in which the reservoir is configured to be suitable for various learning targets, provided is a self-organizing reservoir computing system, including an input layer that outputs an input layer signal corresponding to input data; a reservoir layer that includes therein a nonlinear signal path using physical resonance phenomena and is operable to output an inherent reservoir layer signal in response to the input layer signal; and an output layer that outputs output data corresponding to the reservoir layer signal. Also provided is a self-organizing method.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Abstract: A temperature sensor supplying a measurement signal varying linearly to within 10% as a function of the temperature at least over a temperature range, including an oscillator supplied by a supply voltage and supplying a first oscillating signal, said oscillator including first MOS transistors, the voltage at each internal node of the oscillator having a dynamic range equal to the supply voltage, the measuring signal corresponding to the supply voltage.

Abstract: A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: An inverter is presented. The inverter may be configured to receive an input voltage at an input node of the inverter, and to generate an output voltage at an output node of the inverter. The inverter may comprise a first transistor coupled between a supply node and the output node of the inverter. Further, the inverter may comprise a second transistor coupled between the output node of the inverter and a reference node. The input node of the inverter may be coupled to a back-gate of the first transistor and to a back-gate of the second transistor.

Abstract: In one embodiment, an apparatus includes: a bias circuit having a replica circuit, the bias circuit to generate an oscillator current that is proportional to a variation of the replica circuit; an oscillator circuit coupled to the bias circuit to receive the oscillator current and generate a plurality of signals using the oscillator current; and a waveform shaper circuit coupled to the oscillator circuit to receive the plurality of signals and generate at least one clock signal from the plurality of signals.

Abstract: An ultra-low voltage inverter includes a first inverter, a second inverter, and third inverter. The first inverter receives an input from a delay cell and generates an output for a subsequent delay cell. The second inverter is coupled to the first inverter. The third inverter is coupled to the first inverter, wherein outputs of the second and third inverters are coupled to source terminals of a p-type transistor and an n-type transistor of the first inverter, respectively. The ultra-low voltage inverter forms a delay cell, which is a building block of an ultra-low voltage ring-oscillator. A NAND gate is formed using three inverters such that outputs of two inverters are coupled to the p-type transistors of the NAND gate, while an output of the third inverter of the three inverters is coupled to an n-type transistor of the NAND gate.

Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Abstract: Methods and systems for regulating supply voltage is described. In an example, a device can receive unregulated supply. The device can be connected to a ring oscillator and an integrated circuit. The device can be configured to regulate the unregulated supply to a first voltage. The device can be further configured to provide the regulated supply to the ring oscillator, where the ring oscillator operates with the regulated supply. The device can be further configured to, in response to a change in the regulated supply from the first voltage to a second voltage, adjust the changed regulated supply to return to the first voltage to cause the ring oscillator to operate with a constant regulated supply having the first voltage.

Abstract: Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.

Abstract: A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.

Abstract: A buffer circuit includes an input terminal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit is configured to increase a transition time between logical voltage levels of an output signal generated at the output terminal relative to a transition time between logical voltage levels of an input signal received at the input terminal, and the transition time of the output signal is based on a duration of a logic inversion of the input signal.

Abstract: Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.

Abstract: A ring oscillator includes at least one oscillator stage having a first output and a second output and a start-up circuit. The start-up circuit includes a plurality of AC coupling capacitors receiving the first output and the second output, and a plurality of switches connected to the AC coupling capacitors. The start-up circuit is configured to provide a differential start-up voltage to at least one node of the oscillator using the plurality of switches and the AC coupling capacitors.

Abstract: An apparatus for radio-frequency (RF) oscillation signal production is disclosed. In example implementations, an apparatus includes an oscillator. The oscillator includes multiple oscillation stages that are coupled together in series into a ring. A respective oscillation stage of the multiple oscillation stages includes a transconductance amplifier and a core oscillator. The transconductance amplifier is coupled to a preceding oscillation stage. The core oscillator is coupled to the transconductance amplifier and to a succeeding oscillation stage, with the core oscillator including at least one output node configured to provide a respective output signal. In some implementations, at least one capacitor is coupled across at least the transconductance amplifier. In some aspects, at least one transistor of the transconductance amplifier is implemented with a silicon-on-insulator metal-oxide-semiconductor (SOI MOS) device that includes at least one back-gate terminal.

Abstract: Apparatus and methods are described for voltage dependent delay. An example apparatus includes an oscillator including a delay circuit that is configured to provide an oscillating output signal has a delay based on a delay of the delay circuit. The delay of the delay circuit is based on a voltage it receives. For example, the delay of the delay circuit increases for an increasing received voltage and decreases for a decreasing received voltage. As a result, the oscillating output signal provided by the oscillator is based on the received voltage. For example, a frequency of the oscillating output signal decreases for increasing received voltage and increases for decreasing received voltage. Described in another way, the frequency of the oscillating output signal is relatively low for relatively high received voltage and relatively high for relatively low received voltage.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A system includes an oscillator comprising a first switch, a current source, a capacitor, and a comparator, the capacitor and the comparator coupled at a node. The system includes one or more delay buffers coupled to the comparator. The system includes a first inverter coupled to the one or more delay buffers. The system includes a first buffer coupled to the one or more delay buffers. The system includes a first coupling capacitor coupled to the first inverter and the first buffer via second and third switches, respectively. The system includes a second inverter coupled to the one or more delay buffers. The system includes a second buffer coupled to the one or more delay buffers. The system includes a second coupling capacitor coupled to the second inverter and the second buffer via fourth and fifth switches, respectively. The first and second coupling capacitors are coupled to the oscillator.

Abstract: A method for communication at the speed of light over an on-chip interconnect is disclosed. The method includes dividing an on-chip interconnect into a plurality of segments. Each of the plurality of segments includes a transmission line and a tapered buffer. The tapered buffer is connected to the transmission line. An input capacitance of the tapered buffer satisfies a capacitance condition. A driver resistance of the tapered buffer satisfies a resistance condition.