Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator.

Abstract: Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals.

Abstract: The present disclosure provides a display substrate, its testing method and its manufacturing method. A first testing terminal is connected to a gate electrode of a first TFT, a second testing terminal is connected to a source electrode of the first TFT and a drain electrode of a second TFT, a third testing terminal is connected to a gate electrode of the second TFT, and a fourth testing terminal is connected to a drain electrode of the first TFT and a source electrode of the second TFT.

Abstract: Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.

Abstract: An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC.

Abstract: A random number generator is disclosed. In some embodiments, the random number generator comprises two cross-coupled inverter chains, wherein each inverter chain comprises an odd number of gates including an input NAND gate; wherein when a clock signal input into the NAND gate of both inverter chains switches from low to high, the inverter chains start toggling until a noise induced phase difference automatically collapses the toggling after a random number of cycles; and wherein a random number generated by the random number generator is based on the random number of cycles.

Abstract: Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

Abstract: A signal generator configured to generate an oscillating signal with a temperature-compensated frequency. The signal generator includes a ring oscillator, and a complementary to absolute temperature (CTAT) current generator configured to generate a CTAT current for the ring oscillator to temperature-compensate the frequency of the oscillating signal.

Abstract: A current generating circuit that includes a first current source that generates a first current having a negative temperature coefficient a second current source that generates a second current having a positive temperature coefficient. A compensation circuit generates a common current using a first transistor that receives the first current and a second transistor formed in a mirroring structure, a third transistor that receives the second current, and a fourth transistor formed in a mirroring structure. In addition, the compensation circuit provides the common current as an output current using a transistor that is formed in at least a pair of mirroring structures.

Abstract: The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

Abstract: A digital control ring oscillator (DCO) generally comprises a first delay element and at least one second delay element that is coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and include at least one cell. The cell includes a plurality of transistors arranged in at least one stack.

Abstract: A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Abstract: Controllability of an oscillator circuit is improved. The oscillator circuit has inverters in odd-numbered stages. A circuit is electrically connected to a power supply node of the inverters to which a high power supply potential is input. The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor includes an oxide semiconductor in its channel. A holding circuit including the first transistor and the capacitor has a function of holding an analog potential that is input from the outside. The potential held by the holding circuit is input to a gate of the second transistor. A power supply potential is supplied to the inverters through the second transistor, so that the delay time of the inverter can be controlled by the potential of the gate of the second transistor.

Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.

Abstract: A circuit may include a delay element, a voltage adjust line, and a controllable capacitance. The delay element may have a delay and may include an input and an output. The input may be coupled to the output. The voltage adjust line may be configured to provide an adjusting voltage to the delay element to adjust the delay of the delay element. The controllable capacitance may be coupled to the output of the delay element and may be configured such that a change of the controllable capacitance adjusts the delay of the delay element.

Abstract: A local oscillator signal generation circuit for a frequency divider circuit is disclosed. The local oscillator signal generation circuit includes a delay device adapted to delay a data signal according to a control signal, a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so that the data signal is stable when it is sampled by the data flip-flop. A local oscillator signal is derived from the output of the data flip-flop.

Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.

Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.

Abstract: An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance.

Abstract: A wireless communication device including a communication controller, a transmitter, an antenna and a receiver is provided. The wireless communication device further includes a current detector detecting a current consumption value of a power supply generator, a non-volatile memory pre-storing multiple current thresholds corresponding to multiple operating states, and an abnormal oscillation detector detecting abnormal oscillation by comparing the current consumption value acquired from the current detector and a current threshold corresponding to a present operating state of the wireless communication device out of the current threshold stored in the non-volatile memory.

Abstract: A ring oscillator includes a plurality of ring-connected delay circuits. At least one of the plurality of delay circuits has an SRAM cell and a path circuit connected in parallel to the SRAM cell. The SRAM cell outputs an output signal from a second node to the delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal to be input to a first node from the delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the other transition of the one of transitions.

Abstract: A circuit reducing phase noise of an oscillator includes a transistor, an impedance element coupled to the transistor, a inverting circuit coupled to one end of the impedance element, and an add circuit coupled to the inverting circuit and the other end of the impedance element, wherein the signals from the two ends of the impedance element is superimposed and sent out to reduce phase noise of an oscillator.

Abstract: Described is an apparatus which comprises: a ring oscillator having odd number of delay stages; and an interpolator to receive at least three phases from the ring oscillator, the interpolator to generate quadrature clock phases by interpolating the at least four phases.

Abstract: A device includes a voltage converter circuit that includes an output node, a voltage drop circuit, and a first transistor. The first transistor is electrically coupled between the output node and the voltage drop circuit.

Abstract: A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N?2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.

Abstract: A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

Abstract: A ring oscillator comprising three or more delay cells, each of which comprises a plurality of differential input leads and a differential output lead, wherein each of the plurality of differential input leads comprises one or more inverters, wherein the three or more delay cells are inter-connected forming a plurality of loop paths, wherein each loop path connects the differential output lead of each delay cell to a corresponding differential input lead of another delay cell, wherein each loop path provides an inverter strength determined by a number of inverters in a corresponding differential input lead of each delay cell, wherein the plurality of loop paths are configured to generate an oscillating signal with an operating frequency, and wherein the operating frequency is tunable by digitally adjusting one or more inverter strengths in one or more of the plurality of loop paths.

Abstract: Structures and methods are provided for fabricating a ring oscillator including a plurality of stages. An example multi-layer structure includes a first device layer, a second device layer, and an inter-level connection structure. The first device layer includes a first transistor structure associated with a first stage of a ring oscillator. The second device layer is formed on the first device layer and includes a second transistor structure associated with a second stage of the ring oscillator. Further, the first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first transistor structure and the second transistor structure.

Abstract: There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition.

Abstract: An inverter cell for a ring oscillator. The inverter cell includes a first transistor, a second transistor, a first resistor, a second resistor, and a capacitor. A voltage input terminal is connected to gates of the first transistor and the second transistor. A voltage output terminal is connected drains of the first transistor and the second transistor. The first resistor is connected to the source of the first transistor and a first voltage potential. The second resistor is connected to the source of the second transistor and a second voltage potential. The capacitor has a first end directly connected to the source of the first transistor and the first end of the first resistor and a second end directly connected to the source of the second transistor and the first end of the second resistor.

Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Abstract: Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.

Abstract: A thermal sensor system which includes a thermal sensor and a voltage control network which applies a reference voltage level and a delta voltage level to the same or different thermal sensors. The thermal sensor develops a reference current signal in response to the reference voltage level and a delta current signal in response to the delta voltage level. A current gain network adjusts gain of the delta current signal. A current compare sensor, which is responsive to the reference current signal and the delta current signal, provides a comparison metric. A controller controls the current gain network to adjust gain of the delta current signal while monitoring the comparison metric to determine a gain differential value indicative of a current ratio between the current signals. The controller determines a temperature value based on the gain differential value. A LUT may be used to retrieve the temperature.

Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Abstract: A novel digital eye width monitor (DEWM) system and method are disclosed. The DEWM system provides on-die capability to directly measure the left and right eye-width in picoseconds. The DEWM system measures the time from the phase interpolator (PI) clock position (data eye center, left edge, right edge) to a reference clock, and calculates the left and right eye width within a single-digit pico-second level of accuracy.

Abstract: A memory device and a driving circuit adopted by the memory device are disclosed. The driving circuit includes a power line, a ground line, and first and second data lines coupled between the power line and the ground line. Each data line comprises 4 driver groups. For the first data line, the first driver group contains an even-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains an odd-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. For the second data line, the first driver group contains the odd-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains the even-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. The even-stage inverter driver comprises an even number of inverters. The odd-stage inverter driver comprises an odd number of inverters.

Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.

Abstract: A system and method are provided for increasing a voltage range associated with a voltage controlled oscillator. A voltage-to-current converter is provided. Additionally, a current controlled oscillator is provided that is in communication with the voltage-to-current converter. Further, at least one circuit component is provided that is in communication with the voltage-to-current converter for increasing a voltage range with which the apparatus operates as a voltage controlled oscillator.

Abstract: A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator.

Abstract: A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.

Abstract: A ring oscillator timer circuit can include a plurality of electrical components arranged in a cascaded combination of delay stages connected in a closed loop chain. The timer circuit can begin oscillation a programmable number of gate delays after receiving a start signal. In some examples, the number of gate delays can be programmed to fractional values. In further examples, the ring oscillator timer circuit can include a counter having an input electrically coupled to an output of a reset component.

Abstract: An integrated circuit includes a ring oscillator including delay cells having a delay value and configured to generate two or more periodic waves, a first phase controller configured to compare the phase of a first selected periodic wave to the phase of a reference wave and change the delay value of the delay cells from a first delay value to a second delay value based on a first comparison signal corresponding to a phase difference between the first selected periodic wave and the reference wave, and a second phase controller configured to compare the phase of a second selected periodic wave to the phase of the reference wave and restore the delay value of the delay cells from the second delay value to the first delay value based on a second comparison signal corresponding to a phase difference between the second selected periodic wave and the reference wave.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: An integrated circuit device comprises tuning signal circuitry for generating a tuning signal for calibrating a voltage controlled oscillator (VCO). The tuning signal circuitry is arranged to receive a target voltage signal that is representative of a target voltage across at least one passive element within a resonant tank circuit of a VCO that is being calibrated, generate a VCO simulation signal representative of an average voltage difference across at least one active component of the VCO that is being calibrated, and output a tuning signal based at least partly on the received target voltage signal and the generated VCO simulation signal.

Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Abstract: A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase.

Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.

Abstract: A high-precision oscillator includes a voltage reference module which includes multiple measured Field Effect Transistors and arranged for detecting process corners for the measured Field Effect Transistors to generate a reference voltage containing process corner information of the measured Field Effect Transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency.

Abstract: A calibration system and method are disclosed that include a first bias current generator configured for generating a first bias current that is proportional to absolute temperature (PTAT) and a second bias current generator configured for generating a second bias current that is complementary to absolute temperature (CTAT). The first and second bias currents are copied, multiplied and then summed into a total output bias current, which can be used to bias an electronic circuit. A temperature coefficient is calibrated by changing a ratio of the first and second bias current contributions to the total output bias current, while maintaining the same total output bias current level for a given temperature.

Abstract: A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.