Abstract: A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

Abstract: A ring oscillator comprising three or more delay cells, each of which comprises a plurality of differential input leads and a differential output lead, wherein each of the plurality of differential input leads comprises one or more inverters, wherein the three or more delay cells are inter-connected forming a plurality of loop paths, wherein each loop path connects the differential output lead of each delay cell to a corresponding differential input lead of another delay cell, wherein each loop path provides an inverter strength determined by a number of inverters in a corresponding differential input lead of each delay cell, wherein the plurality of loop paths are configured to generate an oscillating signal with an operating frequency, and wherein the operating frequency is tunable by digitally adjusting one or more inverter strengths in one or more of the plurality of loop paths.

Abstract: Structures and methods are provided for fabricating a ring oscillator including a plurality of stages. An example multi-layer structure includes a first device layer, a second device layer, and an inter-level connection structure. The first device layer includes a first transistor structure associated with a first stage of a ring oscillator. The second device layer is formed on the first device layer and includes a second transistor structure associated with a second stage of the ring oscillator. Further, the first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first transistor structure and the second transistor structure.

Abstract: There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition.

Abstract: An inverter cell for a ring oscillator. The inverter cell includes a first transistor, a second transistor, a first resistor, a second resistor, and a capacitor. A voltage input terminal is connected to gates of the first transistor and the second transistor. A voltage output terminal is connected drains of the first transistor and the second transistor. The first resistor is connected to the source of the first transistor and a first voltage potential. The second resistor is connected to the source of the second transistor and a second voltage potential. The capacitor has a first end directly connected to the source of the first transistor and the first end of the first resistor and a second end directly connected to the source of the second transistor and the first end of the second resistor.

Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Abstract: A thermal sensor system which includes a thermal sensor and a voltage control network which applies a reference voltage level and a delta voltage level to the same or different thermal sensors. The thermal sensor develops a reference current signal in response to the reference voltage level and a delta current signal in response to the delta voltage level. A current gain network adjusts gain of the delta current signal. A current compare sensor, which is responsive to the reference current signal and the delta current signal, provides a comparison metric. A controller controls the current gain network to adjust gain of the delta current signal while monitoring the comparison metric to determine a gain differential value indicative of a current ratio between the current signals. The controller determines a temperature value based on the gain differential value. A LUT may be used to retrieve the temperature.

Abstract: Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.

Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Abstract: A novel digital eye width monitor (DEWM) system and method are disclosed. The DEWM system provides on-die capability to directly measure the left and right eye-width in picoseconds. The DEWM system measures the time from the phase interpolator (PI) clock position (data eye center, left edge, right edge) to a reference clock, and calculates the left and right eye width within a single-digit pico-second level of accuracy.

Abstract: A memory device and a driving circuit adopted by the memory device are disclosed. The driving circuit includes a power line, a ground line, and first and second data lines coupled between the power line and the ground line. Each data line comprises 4 driver groups. For the first data line, the first driver group contains an even-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains an odd-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. For the second data line, the first driver group contains the odd-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains the even-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. The even-stage inverter driver comprises an even number of inverters. The odd-stage inverter driver comprises an odd number of inverters.

Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.

Abstract: A system and method are provided for increasing a voltage range associated with a voltage controlled oscillator. A voltage-to-current converter is provided. Additionally, a current controlled oscillator is provided that is in communication with the voltage-to-current converter. Further, at least one circuit component is provided that is in communication with the voltage-to-current converter for increasing a voltage range with which the apparatus operates as a voltage controlled oscillator.

Abstract: A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator.

Abstract: A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.

Abstract: A ring oscillator timer circuit can include a plurality of electrical components arranged in a cascaded combination of delay stages connected in a closed loop chain. The timer circuit can begin oscillation a programmable number of gate delays after receiving a start signal. In some examples, the number of gate delays can be programmed to fractional values. In further examples, the ring oscillator timer circuit can include a counter having an input electrically coupled to an output of a reset component.

Abstract: An integrated circuit includes a ring oscillator including delay cells having a delay value and configured to generate two or more periodic waves, a first phase controller configured to compare the phase of a first selected periodic wave to the phase of a reference wave and change the delay value of the delay cells from a first delay value to a second delay value based on a first comparison signal corresponding to a phase difference between the first selected periodic wave and the reference wave, and a second phase controller configured to compare the phase of a second selected periodic wave to the phase of the reference wave and restore the delay value of the delay cells from the second delay value to the first delay value based on a second comparison signal corresponding to a phase difference between the second selected periodic wave and the reference wave.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: An integrated circuit device comprises tuning signal circuitry for generating a tuning signal for calibrating a voltage controlled oscillator (VCO). The tuning signal circuitry is arranged to receive a target voltage signal that is representative of a target voltage across at least one passive element within a resonant tank circuit of a VCO that is being calibrated, generate a VCO simulation signal representative of an average voltage difference across at least one active component of the VCO that is being calibrated, and output a tuning signal based at least partly on the received target voltage signal and the generated VCO simulation signal.

Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Abstract: A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase.

Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.

Abstract: A high-precision oscillator includes a voltage reference module which includes multiple measured Field Effect Transistors and arranged for detecting process corners for the measured Field Effect Transistors to generate a reference voltage containing process corner information of the measured Field Effect Transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency.

Abstract: A calibration system and method are disclosed that include a first bias current generator configured for generating a first bias current that is proportional to absolute temperature (PTAT) and a second bias current generator configured for generating a second bias current that is complementary to absolute temperature (CTAT). The first and second bias currents are copied, multiplied and then summed into a total output bias current, which can be used to bias an electronic circuit. A temperature coefficient is calibrated by changing a ratio of the first and second bias current contributions to the total output bias current, while maintaining the same total output bias current level for a given temperature.

Abstract: A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

Abstract: A ring oscillator circuit causing a pulse signal to circulate around a circle to which an even number of inverting circuits are connected in a ring, wherein one of the inverting circuits is a first starting inverting circuit, which drives a first pulse signal according to a control signal, another of the inverting circuits is a second starting inverting circuit, which drives a second pulse signal based on a leading edge of the first pulse signal, still another is a third starting inverting circuit, which drives a third pulse signal based on the leading edge of the first pulse signal after the second pulse signal is driven, and the first to third starting inverting circuits are arranged within the circle of the inverting circuits in order of the third, second, and first pulse signals in traveling directions of the pulse signals.

Abstract: A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: A temperature-compensated oscillator and a device including the same include an oscillation unit configured to generate an oscillation signal using an operating current and an operating voltage, a bias circuit configured to control the operating current so that a frequency of the oscillation signal increases as a temperature increases, and a voltage generation unit configured to generate the operating voltage that varies with the temperature.

Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

Abstract: A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Abstract: A ring oscillator has a plurality of elementary units connected in cascade and linked in order to make a chain with the respective output terminals connected to the input terminals of the successive elementary units of the chain, the elementary units being crossed by a cyclic signal during a time period of activation, each of said elementary units comprising an auxiliary recovery terminal for temporarily resetting each elementary unit during each loop of said cyclic signal, said auxiliary recovery terminal being connected to an output terminal of a successive elementary unit of the chain.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: A temperature sensor includes a signal delaying apparatus, a comparison apparatus, a multiplier and a counting apparatus. The signal delaying apparatus is configured to receive a step signal, perform a phase delay operation on the received step signal according to a temperature degree, and thereby forming a first output signal. The comparison apparatus is configured to receive the first output signal and the step signal, and accordingly output a second output signal. The multiplier is configured to receive the second output signal and a clock signal, and accordingly output a third output signal. The counting apparatus is configured to receive the third output signal, count the number of pulses of the third output signal, and generate a digital code accordingly.

Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Abstract: A ring oscillator comprising three or more delay cells, each of which comprises a plurality of differential input leads and a differential output lead, wherein each of the plurality of differential input leads comprises one or more inverters, wherein the three or more delay cells are inter-connected forming a plurality of loop paths, wherein each loop path connects the differential output lead of each delay cell to a corresponding differential input lead of another delay cell, wherein each loop path provides an inverter strength determined by a number of inverters in a corresponding differential input lead of each delay cell, wherein the plurality of loop paths are configured to generate an oscillating signal with an operating frequency, and wherein the operating frequency is tunable by digitally adjusting one or more inverter strengths in one or more of the plurality of loop paths.

Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.

Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.

Abstract: A method for compensating for strain on a MEMS device includes generating a signal indicative of a strain on the MEMS device in a first mode of operating a system including the MEMS device. The method includes compensating for the strain in a second mode of operating the system based on the signal. Generating the signal may include comparing an indicator of a resonant frequency of the MEMS device to a predetermined resonant frequency of the MEMS device. Generating the signal may include comparing a first output of a strain-sensitive device to a second output of a strain-insensitive device and generating an indicator thereof. Generating the signal may include sensing a first capacitive transduction of strain-sensitive electrodes of the MEMS device in the first mode and generating the signal based thereon. The strain-sensitive electrodes of the MEMS device may be disabled in the second mode.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: A cascaded oscillator array includes a first oscillator array and a second oscillator array. The first oscillator array includes at least three oscillator elements coupled unidirectionally in a first ring such that the first oscillator array outputs a first oscillating signal. Each of the at least three oscillator elements is coupled to receive a signal from a sensing element. The second oscillator array includes at least three oscillator elements coupled unidirectionally in a second ring such that the second oscillator array outputs a second oscillating signal. A first number of the at least three oscillator elements of the first oscillator array is the same as a second number of the at least three oscillator elements of the second oscillator. Each oscillator element of the at least three oscillator elements of the second oscillator array is coupled to receive an output signal from a single oscillator element of the at least three oscillator elements of the first oscillator.

Abstract: The present invention is to provide a frequency jitter circuit and a method for generating frequency jitter. The frequency jitter circuit, comprising: an oscillating circuit, configured to generate an oscillating frequency output signal; a decoding circuit, configured to be controlled by said oscillating frequency output signal for generating several pulse output signals; a delay circuit, through which said oscillating frequency output signal is passed for generating a frequency jitter output signal that is delayed a period of time compared to said oscillating frequency output signal. Application of the invention into switched-mode power supply might reduce EMI average noise in the switched-mode power supply, and smooth energy spectrum density.

Abstract: A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.

Abstract: To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased.

Abstract: A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ?T relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register. The content of the register represents a value of an input signal modulation symbol.

Abstract: A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current.

Abstract: A timer to provide pulses at a comparator output wherein a frequency of the pulses is dependent on temperature, wherein providing each pulse includes biasing a first input of the comparator at a voltage and operating a transistor in a subthreshold region of operation to change the voltage of the first input of a comparator at a rate dependent upon temperature. The output of the comparator changes state when the voltage of the first input crosses a voltage of a second input of the comparator.