Abstract: An integrated circuit system is provided. The system includes a ring oscillator including a first plurality of logic gates connected in a ring configuration. The system also includes a second plurality of logic gates used to implement a heater to generate a controlled amount of heat. The second plurality of logic gates is also used to implement a temperature sensor to measure a temperature of the ring oscillator. The system further includes one or more logic circuits coupled to the heater and the temperature sensor. The one or more logic circuits are used to control the heater to heat the ring oscillator only until the temperature of the ring oscillator is one of a plurality of predefined temperatures, during or after which the ring oscillator starts and operate.

Abstract: Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.

Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.

Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Abstract: Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.

Abstract: A temperature sensor circuit may include a ring oscillator being enabled according to an enable signal and outputting a square wave signal with a first frequency, a divider dividing the first frequency of the square wave signal from the ring oscillator to generate a pulse signal with a second frequency, a counter counting a time interval of the pulse signal outputted from the divider according to an external clock to generate a count signal, a latch temporarily storing a value of the counter signal according to the pulse signal and outputting a digital code, and a supply voltage monitor being enabled according to the pulse signal, comparing a reference voltage to one or more comparison voltages and generating a switching logic signal. The reference voltage is kept at a substantially constant level when a level of a supply voltage changes.

Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.

Abstract: A temperature sensor has a first transistor with a gate voltage tied to maintain the first transistor in an off state with leakage current flowing through the transistor, the leakage current varying with temperature. A second transistor is coupled to the first transistor and receives a gate voltage to keep the second transistor in an on state. A current mirror mirrors the leakage current and supplies a mirrored current used to control a frequency of an oscillator signal varies with the mirrored current. The temperature of the first transistor is determined based the frequency of the oscillator signal.

Abstract: An oscillator circuit (100) comprises a first tank circuit (T1) comprising an inductive element (L) and a capacitive element (C) coupled in series between a first voltage rail (14) and a first drive node (12). A feedback stage (F) is coupled to a first tank output (13) of the first tank circuit (T1) and to the first drive node (12). The feedback stage (F) is arranged to generate, responsive to a first oscillating tank voltage present at the first tank output (13), a first oscillating drive signal at the first drive node (12) in-phase with a first oscillating tank current flowing in the inductive element (L) and the capacitive element (C), thereby causing the oscillator (100) to oscillate in a series resonance mode of the inductive element (L) and the capacitive element (C).

Abstract: A ring oscillator is configured with a multiple number of logic inverting circuits in a ring shape and generates multi-phase clock signals. A period measuring unit measures a period of a reference clock inputted thereto by the multi-phase clock signals of the ring oscillator and outputs a measured period as a period data value. A frequency spreading calculation unit calculates a frequency spreading command value in accordance with a frequency spreading rate, a frequency spreading period and the period data value of the period measuring unit, which are inputted. A pulse generation unit generates a clock pulse corresponding to the frequency spreading command value in accordance with a data value determined by addition of the frequency spreading command value to the period data value.

Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.

Abstract: Provided are a method of testing semiconductor device and a system for testing semiconductor device. The method includes measuring a minimum operating voltage of each of a plurality of sample semiconductor devices and an operating frequency of corresponding ring oscillators included in each of the plurality of sample semiconductor devices, generating a model between the operating frequencies of the ring oscillators and the minimum operating voltages of the sample semiconductor devices, measuring an operating frequency of ring oscillators included in a target semiconductor device, and determining a target minimum operating voltage of the target semiconductor device based on the operating frequency of the ring oscillators of the target semiconductor device and the model.

Abstract: A ring oscillator circuit includes a plurality of first delay circuits each including X first delay elements, and a second delay circuit including a plurality of second delay elements different in delay amount from each other arranged in parallel to each other so as to be alternatively loaded, the plurality of first delay circuits and the second delay circuit are configured to be connected to each other in a ring-like manner, and X is an integer fulfilling X?1.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. The semiconductor device may include a second oscillation signal generation circuit for generating a second oscillation signal. The second oscillation signal generation circuit may be provided with a test voltage. The test voltage may be generated based on a burn-in test signal.

Abstract: A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged, which may reduce the impact that the noise has on the frequency of the ring oscillator output signal. In some embodiments, a regulator may supply a regulated voltage to the ring oscillator. The regulator may reduce the impact of the noise for low frequency components of the noise, while the frequency divider may reduce the impact for high frequency of the noise.

Abstract: An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.

Abstract: During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator.

Abstract: A voltage controlled oscillator (VCO) and a method of operating the VCO are disclosed. The VCO includes an inductor device, a capacitor device coupled in parallel with the inductor device through first and second nodes, and a pair of cross-coupled transistors coupled in parallel with the inductor device and the capacitor device through the first and second nodes. At least one of the pair of cross-coupled transistor includes a plurality of sub transistors coupled in parallel. The sub transistors are individually switchable to adjust current drive capability of each of the sub transistors. Each of the sub transistors includes a first gate and a second gate.

Abstract: To provide a highly accurate temperature sensor circuit. The temperature sensor circuit includes a first constant current circuit; a first diode in which a first voltage reflecting the temperature of an object to be detected is generated between an anode and a cathode in accordance with a first current supplied from the first constant current circuit; a second constant current circuit; a second diode which includes an oxide semiconductor and in which a second voltage is generated between an anode and a cathode in accordance with a second current supplied from the second constant current circuit; and an amplifier circuit which amplifies a difference between the first voltage and the second voltage.

Abstract: A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.

Abstract: A wireless sensor system is described which can be used to measure temperature and/or pressure within an electromagnetically shielded environment. The sensor system includes an embedded processor which intermittently transmits data from the sensors. In electromagnetically shielded environments, the processor transmits the data when the electromagnetically shielding components are moved into a non-shielding configuration.

Abstract: A temperature-compensated oscillator and a device including the same include an oscillation unit configured to generate an oscillation signal using an operating current and an operating voltage, a bias circuit configured to control the operating current so that a frequency of the oscillation signal increases as a temperature increases, and a voltage generation unit configured to generate the operating voltage that varies with the temperature.

Abstract: A device includes configurable parallel connected ring oscillators and a finite state machine coupled to the ring oscillators. The finite state machine is configured to cause each of the ring oscillators to operate in an accumulate entropy state for a first period of time and a break phase lock state for a second period of time. When operating in the accumulate entropy state, all of the ring oscillators are in the same configuration. When operating in the break phase lock state, each ring oscillator is in a different configuration than the other ring oscillators.

Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator.

Abstract: Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals.

Abstract: The present disclosure provides a display substrate, its testing method and its manufacturing method. A first testing terminal is connected to a gate electrode of a first TFT, a second testing terminal is connected to a source electrode of the first TFT and a drain electrode of a second TFT, a third testing terminal is connected to a gate electrode of the second TFT, and a fourth testing terminal is connected to a drain electrode of the first TFT and a source electrode of the second TFT.

Abstract: Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.

Abstract: An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC.

Abstract: A random number generator is disclosed. In some embodiments, the random number generator comprises two cross-coupled inverter chains, wherein each inverter chain comprises an odd number of gates including an input NAND gate; wherein when a clock signal input into the NAND gate of both inverter chains switches from low to high, the inverter chains start toggling until a noise induced phase difference automatically collapses the toggling after a random number of cycles; and wherein a random number generated by the random number generator is based on the random number of cycles.

Abstract: Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

Abstract: A signal generator configured to generate an oscillating signal with a temperature-compensated frequency. The signal generator includes a ring oscillator, and a complementary to absolute temperature (CTAT) current generator configured to generate a CTAT current for the ring oscillator to temperature-compensate the frequency of the oscillating signal.

Abstract: A current generating circuit that includes a first current source that generates a first current having a negative temperature coefficient a second current source that generates a second current having a positive temperature coefficient. A compensation circuit generates a common current using a first transistor that receives the first current and a second transistor formed in a mirroring structure, a third transistor that receives the second current, and a fourth transistor formed in a mirroring structure. In addition, the compensation circuit provides the common current as an output current using a transistor that is formed in at least a pair of mirroring structures.

Abstract: The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

Abstract: A digital control ring oscillator (DCO) generally comprises a first delay element and at least one second delay element that is coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and include at least one cell. The cell includes a plurality of transistors arranged in at least one stack.

Abstract: Controllability of an oscillator circuit is improved. The oscillator circuit has inverters in odd-numbered stages. A circuit is electrically connected to a power supply node of the inverters to which a high power supply potential is input. The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor includes an oxide semiconductor in its channel. A holding circuit including the first transistor and the capacitor has a function of holding an analog potential that is input from the outside. The potential held by the holding circuit is input to a gate of the second transistor. A power supply potential is supplied to the inverters through the second transistor, so that the delay time of the inverter can be controlled by the potential of the gate of the second transistor.

Abstract: A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.

Abstract: A circuit may include a delay element, a voltage adjust line, and a controllable capacitance. The delay element may have a delay and may include an input and an output. The input may be coupled to the output. The voltage adjust line may be configured to provide an adjusting voltage to the delay element to adjust the delay of the delay element. The controllable capacitance may be coupled to the output of the delay element and may be configured such that a change of the controllable capacitance adjusts the delay of the delay element.

Abstract: A local oscillator signal generation circuit for a frequency divider circuit is disclosed. The local oscillator signal generation circuit includes a delay device adapted to delay a data signal according to a control signal, a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so that the data signal is stable when it is sampled by the data flip-flop. A local oscillator signal is derived from the output of the data flip-flop.

Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.

Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.

Abstract: An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance.

Abstract: A wireless communication device including a communication controller, a transmitter, an antenna and a receiver is provided. The wireless communication device further includes a current detector detecting a current consumption value of a power supply generator, a non-volatile memory pre-storing multiple current thresholds corresponding to multiple operating states, and an abnormal oscillation detector detecting abnormal oscillation by comparing the current consumption value acquired from the current detector and a current threshold corresponding to a present operating state of the wireless communication device out of the current threshold stored in the non-volatile memory.

Abstract: A ring oscillator includes a plurality of ring-connected delay circuits. At least one of the plurality of delay circuits has an SRAM cell and a path circuit connected in parallel to the SRAM cell. The SRAM cell outputs an output signal from a second node to the delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal to be input to a first node from the delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the other transition of the one of transitions.

Abstract: A circuit reducing phase noise of an oscillator includes a transistor, an impedance element coupled to the transistor, a inverting circuit coupled to one end of the impedance element, and an add circuit coupled to the inverting circuit and the other end of the impedance element, wherein the signals from the two ends of the impedance element is superimposed and sent out to reduce phase noise of an oscillator.

Abstract: A device includes a voltage converter circuit that includes an output node, a voltage drop circuit, and a first transistor. The first transistor is electrically coupled between the output node and the voltage drop circuit.

Abstract: A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N?2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.

Abstract: Described is an apparatus which comprises: a ring oscillator having odd number of delay stages; and an interpolator to receive at least three phases from the ring oscillator, the interpolator to generate quadrature clock phases by interpolating the at least four phases.