Abstract: A first situation indicating that the system is in a power-on situation or an un-mute situation, or a second situation indicating that the system is in a power-off situation or in a mute situation, is detected. When the first situation is detected, a differential PWM signal including a plurality of pulses each having a gradually increased or reduced width and the subsequent pulse train of 50% duty cycle pulses is generated and, if the output of an audio processor is in a stable situation, sent to the amplifier via a multiplexer. When the second situation is detected, the differential PWM signal including a plurality of pulses each having a gradually reduced width and the subsequent pulse train of no signal is generated and, at the same time, the generated pulses are sent to the amplifier via the multiplexer.

Abstract: The invention provides a method and a modulation circuit for pulse width modulation with feedback, wherein a pulse width modulated signal is provided on the basis of an input signal and a reference signal that is periodic and has a reference frequency. The pulse width modulated signal is provided in that an output signal is switched from a first voltage level to a second voltage level in dependence on a comparison between the input signal and the reference signal at least once in every cycle of the reference signal, and in that at least once at a fixed moment in time in every cycle the pulse width modulated signal is switched from the second voltage level to the first voltage level. Furthermore, a periodic correction signal is added for compensation of the switching from the second voltage level to the first voltage level in the pulse width modulated signal.

Abstract: There is disclosed a method and apparatus for generating, in an envelope tracking modulator of a mobile radio transmission apparatus, a pulse width modulated, PWM, signal representing a time-varying signal, the method comprising, for each time cycle: a) generating a rising ramp from a first voltage level to a second voltage level; b) generating a falling ramp from the second voltage level to the first voltage level; c) detecting a rising slope of the time-varying signal crossing the falling ramp and responsive thereto if the PWM signal is at the first voltage level, transitioning the PWM signal to the second voltage signal; d) detecting a falling slope of the time-varying signal crossing the rising ramp, and responsive thereto if the PWM signal is at the second voltage level, transitioning the PWM signal to the first voltage signal.

Abstract: Switch-modulation of a radio-frequency power amplifier by-representing the input signal by the I-signal (1) and Q-signal (9) of the complex components (I+j?Q), and pulse width modulating the I-signal and the Q-signal separately to create a modulated I-signal pulse sequence (3a) and a modulated Q-signal pulse sequence (3b). Further, the pulses corresponding to negative sample values are time-shifted relative the pulses corresponding to positive sample values, and each pulse of the I-signal pulse sequence is delayed by introducing a delaying time shift.

Abstract: A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.

Abstract: A low noise oscillator includes a resonator 102 that is excited with a pulsed signal (i.e., an impulse of energy) to replace energy lost to parasitic resistive losses once every Nth period (where N=1, 2, 3 . . . ). The resonating signal is monitored by a level detector and when the signal falls below a predetermined threshold, the pulse generator outputs a pulse or adjusts pulse width, pulse amplitude (or both) of a pulsed signal to create the necessary impulse for application to the resonator to recoup losses resulting from resonator operation. A phase shifting circuit may be provided to ensure the pulses are time aligned with the resonating signal to reduce noise.

Abstract: Systems and method to compress digital video based on human factors expressed as a desirability score are provided. A particular method includes passing a digital input signal through a pulse-width modulator and passing an output of the pulse-width modulator through a power switching device. An output of the power switching device has a plurality of pulses. The method includes receiving the output of the power switching device at a first input of a comparator and receiving a reference voltage at a second input of the comparator. The method includes determining a net signal based on an output of the comparator and determining a timing error signal based on the net signal and the digital input signal. The method also includes adjusting the digital input signal to compensate for harmonic distortion based at least in part on the timing error signal.

Abstract: A signal converter for generating switch drive signals for a multi-level converter comprises an input for a first pulse-width-modulation signal and a second pulse-width-modulation signal and an input for a polarity signal indicating a first polarity or a second polarity. The signal converter comprises four outputs for four switch drive signals for driving four switches of the multi-level converter. Also, the signal converter comprises a logic circuit for driving the switch drive signals in dependence on the polarity signal. The logic is configured to drive the switch drive signals in dependence on the polarity signal.

Abstract: A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.

Abstract: The present invention relates in general to transferring the envelope information of a polar modulated signal to a varying pulsewidth signal, while the phase modulation is direct transferred to the phase modulation of this PWM signal. Accordingly, the resultant signal is a PWM-PPM-signal. Such a signal can efficiently amplified by use of switching amplifying stages. By the present invention four pre-distorted baseband signals are applied basically to 4 linear RF mixers and a two adders, which are, the only needed external RF building blocks to build the modulator according to the invention. That is, the basic idea of the invention resides in the way of modulation of the four baseband signals and the way of combining of the RF modulated signals.

Abstract: The invention provides a novel method of transmit beamforming, which allows compact analog implementation of complex digital algorithms without compromising their features. It is aimed to support envelope shaping, apodization, and phase rotation per channel and per firing. Each of three embodiments represents a complete transmit channel driven by pulse-width modulated (PWM) waveforms stored in a conventional sequence memory. PWM signals controls the transmit pulse envelope (shape) by changing the duty cycle of the carrier. Beamformation data are loaded prior to a firing via serial interface. Under the direction of a controller, the circuitry allows high precision (beyond sampling rate) phase rotation of the carrier. It also provides transmit apodization (aperture weighting), which maintains an optimal trade-off among low sidelobe level and widening of the mainlobe. Implementing such an IC, the manufacturing cost of a high-end ultrasound system can be reduced.

Abstract: A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. An algorithm produces a specific sequence of pulses of varying width such that the voltage or current delivered to the load from the system plant closely resembles a critical damped step response. The specific pulse width modulation sequence controls a plant that provides a near critical damped step response in one embodiment without a feed-forward or feedback loop physically embodied in the control system thereby reducing the parts cost or control semiconductor production yield cost while enhancing noise immunity and long term reliability of the control system.

Abstract: An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.

Abstract: A dual mode modulator is proposed for driving a power output stage having a serial connection of high-side power FET and low-side power FET. The dual mode modulator includes a PWM modulator operating under a PWM-frequency and a PFM modulator for controlling the power output stage. To improve the dynamic load regulation of the dual mode modulator, a dynamic frequency booster can be added to the dual mode modulator to boost up the PWM-frequency from its normal operating frequency during a PFM-to-PWM mode transition period. Secondly, a dynamic slew rate booster can be added to boost up an error amplifier slew rate of the PWM modulator from its normal operating slew rate during the mode transition period. Thirdly, a dynamic turn-off logic circuit can be added to turn off the low-side power FET during the mode transition period.

Abstract: An arrangement for pulse-width modulating an analog or digital input signal is provided. The non-linear distortion generated in the pulse-width modulator is precompensated by applying a signal with reversed error to the pulse-width modulator. The signal with reversed error is generated by a further pulse-width modulator that receives the input signal and whose output signal is subtracted from twice the input signal. The arrangement may e.g. be used to drive class D audio amplifiers.

Abstract: A pulse width modulation device which a step form control signal generated by a control signal generating device and a triangular wavecarrier signal generated by a carrier generating device are compared by a digital comparator and the comparison signal is supplied to an edge detection device. Also, a top/bottom signal generated by a top/bottom signal generating device is supplied to the edge detection device. The edge detection device includes an edge detection function that generates an edge detection signal by detecting change of the comparison signal. The edge detection function is inhibited by the edge detection signal; and inhibition is cancelled by the top/bottom signal so that the edge detection signal is output. A PWM signal is output from the pulse generating device in accordance with the comparison signal, edge detection signal, and top/bottom signal.

Abstract: A method and apparatus to generate a pulse width modulated signal from a sampled digital signal by chaotic modulation. The method includes generating predetermined chaotic intervals having random interval values using a chaotic interval generator, and generating the pulse width modulated signal from a reference signal and the sampled digital signal during each of the chaotic intervals. Thus, electromagnetic interference (EMI) that affects an audio amplifier can be remarkably reduced.

Abstract: A pulse width modulator (PWM) includes a driver and a two-way integrator. The driver is coupled to output a first and a subsequent period of a PWM signal. Both the first and the subsequent periods include the PWM signal changing between first and second states. The two-way integrator is coupled to integrate an input current and coupled to generate a duty ratio signal in response to integrating the input current. The driver determines a duty factor of both the first and the subsequent periods by setting the PWM signal to the second state in response to the duty ratio signal. The two-way integrator includes a capacitor that integrates the input current during the first period by charging the capacitor and integrates the input current during the subsequent period by discharging the capacitor.

Abstract: A communications device includes a supply terminal which is able to be connected to a two-position-controlled power supply; a pulse width recording device, which is coupled to the supply terminal and which records a pulse width of current pulses that flow through the supply terminal, and a signal processing device which assigns a first logical level to a first recorded pulse width and a second logical level to a second recorded pulse width.

Abstract: Pulse-width modulation (PWM) finds wide use in many applications including motor control, communication systems, music synthesizers, power supplies, class-D and digital amplifiers, among others. The Fourier series expansion of each period of a pulse waveform includes an additive term that is a function of the pulse width in that period. As the pulse width is varied, this additive term varies, which can be problematic in many applications. In an embodiment, a single-pulse per period pulse width modulated waveform comprising a zero d.c. term in each period regardless of pulse width is generated. In various realizations these waveforms may be generated by electronic circuitry without the use of capacitive coupling or may be generated by algorithms. Further aspects include “through-zero” pulse width modulation and zero-centered asymmetric triangle waveforms and use in instrumentation for measurement of a phase angle of an exogenous system or phenomena.

Abstract: An apparatus comprising a signal generator for generating a polar representation of a signal. The apparatus comprises further a first filtering unit configured to filter a low frequency part of the amplitude component of said signal and a second filtering unit configured to filter a high frequency-part of the amplitude component of said signal. In addition, the apparatus includes a pulse width modulating unit configured to modulate the filtered high frequency part of the amplitude component of said signal together with the phase component of said signal. Finally the apparatus includes a DC-DC converter configured to convert the filtered low frequency part of the amplitude component of said signal. Said DC-DC converter supplies a switching mode power amplifier for amplifying the pulse width modulated signal.

Abstract: A PWM control method increases/decreases a duty ratio of a PWM signal with a predetermined resolution so to control the duty ratio of the PWM signal in the case of a PWM control. The resolution of the duty ratio of the PWM signal is increased to make a high period in the duty ratio of the PWM signal longer than a rise time of the PWM signal if the high period is shorter than the rise time. The resolution of the duty ratio of the PWM signal is increased to make a low period in the duty ratio of the PWM signal longer than a fall time of the PWM signal if the low period is shorter than the fall time.

Abstract: The PWM signal generator of the present invention generates a first pulse waveform in which a first on-time ?T1 calculated by a first on-time calculator (401) is used as an on-duration, and a second pulse waveform in which a second on-time ?T2, calculated by a second on-time calculator (402) when a preset delay time has elapsed from the start of the calculation of the first on-time ?T1, is used as an on-duration. Also, a PWM signal generator (413) generates a PWM signal on the basis of a composite pulse in which the generated first pulse waveform and second pulse waveform are combined, and the first on-time calculator (401) calculates the first on-time ?T1 at the end of the composite pulse waveform.

Abstract: There is described a method and an apparatus for pulse width modulation with a predefined switching period having an adjustable ratio of the switch-on duration to the switch-off duration, in which a quantized signal is converted into a pulse-width-modulated signal and is generated in the form of a discrete pulse sequence of switch-on operations and switch-off operations with the predefined switching period, the switching edge for the switch-on duration and/or the switch-off duration being determined on the basis of the ratio of the switch-on duration to the switch-off duration.

Abstract: Dead time compensated complementary pulse width modulation (PWM) signals are derived from a PWM generator by first applying time period compensation to the PWM generator signal based upon the direction of current flow in an inductive load being controlled by the PWM generator. Dead time is then applied to the compensated PWM generator signal for producing complementary dead time compensated PWM signals for controlling power switching circuits driving the inductive load.

Abstract: Systems and methods for minimizing startup transients in digital audio controllers that may result in audible artifacts in the output of an audio amplification system. One embodiment comprises a digital PWM amplifier that includes a mechanism for controlling the amount of dead time in the audio output signal. When the amplifier starts up, the PWM signals provided to the output stage are simultaneously deasserted (i.e., there is dead time) for most of each switch period. The amount of dead time is gradually reduced over a series of switch periods until a nominal operating amount of dead time in each switch period is reached. Thus, the PWM signals are slowly ramped up from having a very large percentage of dead time (e.g., nearly 100%) to having a very small percentage of dead time (e.g., 1-2% to prevent shoot-through.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.

Abstract: A system is provided for use in an audio signal processor to reduce the order of the loop to remove sound artifacts from an audio signal that includes an input for receiving an audio input signal a control loop of order greater than one configured to process the audio input signal and to output a Pulse Width Modulated audio output signal, a circuit for performing a gradual reduction of the order of the control loop such that prior to entering a shut down state the order is reduced to a single order and a circuit to disconnect a Driver Circuit from the Pulse Width modulated signal operated by a timing device designed to switch at the moment of zero average output value.

Abstract: A power amplifier including a loop filter, a frequency generator, a quantizer, and an output stage module is provided. The frequency generator outputs a signal with a reference frequency to the loop filter, and includes a logic circuit, a current array, and a dummy load. The dummy load representing a load circuit in the loop filter is coupled to the current array. An equivalent impedance of the dummy load is proportioned to an equivalent impedance of the load circuit. The current array outputs the signal and a dummy signal to the loop filter and the dummy load, respectively, according to a logic signal. By using the frequency generator to modulate the frequency automatically, an impact on the power amplifier caused by passive devices therein due to process variationscan be reduced.

Abstract: The rising edge of a pulse width modulated output signal occurs after an input ramp signal starts to rise. The ramp signal starts to rise after the rising edge of a periodic set signal and before the falling edge of a periodic set signal. A feedback control signal intersects a substantially linear region of the ramp signal to generate a reset signal using a PWM comparator. The periodic set signal and reset signal are input to a latching circuit to generate the pulse width modulated output signal. The minimum pulse width can approach zero while having adequate overdrive to the PWM comparator. Having the rising edge of the reset signal rise before the falling edge of the set signal can allow a zero percent duty cycle without the need for a ramp offset voltage.

Abstract: A system for controlling the delay applied to one branch of a pulse width modulation amplifier. The delay typically incorporated whether input signal level is low and diminished when the input signal level increases. The system may be implemented using a switch, a level detector and a timer, which in conjunction determine whether the delay unit is included in the branch or bypassed. The system may also use a programmable delay that can adjust the period of delay applied or be programmed to operate as a pass-through where delay is no longer beneficial for providing high signal quality.

Abstract: Embodiments of the present method and system permit an effective method for determining the optimum selection of pulse width modulation polarity and type including determining machine parameters, inputting the machine parameters into a predicted duty cycle module, determining the optimum polarity of the pulse width modulation for a predicted duty cycle based on a pulse width modulation generation algorithm, and determining the optimum type of the pulse width modulation for a predicted duty cycle based on the pulse width modulation generation algorithm.

Abstract: Digital pulse width modulation with variable period and error distribution that improves the tradeoff between resolution and clock speed in pulse width modulation circuits so that a higher resolution can be achieved with a lower clock speed. A preferred method includes, for a signal sample S and each value of P in a range Pmin to Pmax of pulse periods P, determining a pulse width V=round(P*S), where round(P*S) is the closest integer value of P*S, and the magnitude of the error |E|=|S?V/P|, for the value of V (Vopt) and P (Popt) associated with the lowest value of the magnitude of the error |E|, providing an output pulse of a pulse width Vopt during the pulse period Popt, and successively repeating a) and b). Other aspects of the invention may include error distribution, error squelching to prevent idle-tone, idle-noise artifacts, 2-samples-per-pulse and non-uniform sampling and pulsing. Other features are disclosed.

Abstract: Otherwise conventional pulse-width modulators (PWMs) generate signals that can be converted into other forms by reshapers, and thereby overcome many of the problems of conventional PWMs in applications that demand high performance, such as switched-mode amplifiers and radio-frequency transmitters in modern communication systems. With a suitable reshaper, a conventional PWM differential signal can be converted into a signal more typical of linear amplification with nonlinear components (LINC) and still retain low-frequency information, such as the information needed for linearization of a switched-mode amplifier. Apparatus and methods of transforming signals are disclosed.

Abstract: A pulse width modulation (PWM) circuit comprises a first integrator (g m1) with a first feedback capacitor (C1), a second integrator (gml) with a second feedback capacitor (C2) and a comparator (A0) having a first input (V1) connected to the output of the first integrator (gm1) and a second input (V2) connected to the output of the second integrator (gm2). A connection path comprising a resistor (R2) is established from the output of the first integrator (gm1) to an input of the second integrator (gm2). The first and second feedback capacitors (C1, C2) have capacities with a non-linear factor X(V) and a circuit with an inversely non-linear factor X?1(V) is arranged in the connection path between the output of the first integrator (gm1) and said input of the second integrator (gm2). The PWM circuit may form path of a Class-D amplifier.

Abstract: A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.

Abstract: A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.

Abstract: The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.

Abstract: The invention relates to pulse width modulator system (PWMS) comprising a modulator system input (MI),a modulator output (MO), an amplitude distribution filter (ADF) ,and a pulse width modulator (PMOD), wherein said amplitude distribution filter (ADF) establishes an intermediate output signal (OS) by modifying the level of the amplitude distribution of an input signal (IS) within at least one predetermined amplitude range of said input signal (IS), said input signal (IS) being received from said modulator system input (MI), and wherein said pulse width modulator (PMOD) provides a modulator output signal (MOS) on said modulator output(MO) on the basis of said intermediate output signal (OS).

Abstract: In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

Abstract: In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.

Abstract: A pulse step modulator employs a plurality of series connected unit step power amplifier modules. Each module is turned on by a turn-on signal to provide a unit step voltage of a given value. An output circuit is connected to the modules for providing an output voltage to a load and wherein the output voltage is a multiple of the unit step voltages in dependence upon the number of modules that are turned on. The modules are sequentially turned on in a given order and are turned off in the reverse order. An encoder provides turn-on signals with each turn-on signal being applied to a selected one of the modules. The number of turn-on signals provided varies as a function of the magnitude of a time varying input signal. A controller alternately turns enables or disables (in a swapping manner) one of a pair of associated modules as the magnitude of the input signal increases and decreases.

Abstract: The present invention relates to the application of a free-tunning clock signal in a pulse-width modulator (PWM) Specifically there is disclosed an integrated circuit comprising a pulse-width modulator (2) for converting an input signal (6) into a pulse-width-modulated signal (8), the pulse-width modulator (2) being clocked by a clock signal (4) generated by a clock generator (3) which generates a free-running clock signal In a preferred embodiment of the invention, the clock generator (3) is provided in the same integrated circuit (1), such as a chip, as the digital pulse-width modulator (2).

Abstract: A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.

Abstract: Methods and systems for modulating an input electrical signal are disclosed and may comprise modulating input signals utilizing a digital Class-D modulator and generating a digital output signal that is proportional to the input signals. The digital Class-D modulator may be comprised of four stages. To avoid integrator saturation, the output of at least one integrator stage may be limited by utilizing limiters in integrator feedback loops. The digital Class-D modulator utilizes a pulse width modulation technique. For increased signal to noise ratio (SNR) at a desired output power, the magnitude of a triangular waveform oscillator voltage may be greater than the magnitude of an integrated input signal. The digital output signal may be fed back to an input of at least one of the four stages in the digital Class-D modulator. The triangular waveform oscillator frequency may be adjusted to match desired output frequency.

Abstract: To suppress an unbalance of a dwell period in a changeover of phases in which switching is dwelled in an inverter controller. A PWM operation unit 5 includes a modulation-wave generating unit 11 that generates a modulation wave as a voltage command value to an inverter main circuit 2, a carrier-wave generating unit 12 that generates a carrier wave used as a reference for a switching command, and a comparing unit 13 that compares the modulation wave generated by the modulation-wave generating unit 11 and the carrier wave generated by the carrier-wave generating unit 12. During an operation in a two-phase modulation mode in which switching of any one of three phases configuring the inverter main circuit 2 is dwelled, the PWM operation unit 5 controls the carrier-wave generating unit 12 to set a carrier wave frequency to an integral multiple of a modulation wave frequency.

Abstract: A pulse width modulation (PWM) structure enabling regulated duty cycle includes a DC power supply unit, a signal generating unit, a voltage-dividing resistor unit, a reference voltage unit, and a comparing unit. When the DC power supply unit supplies a voltage signal to the voltage-dividing resistor unit, the latter receives the voltage signal and sets voltage levels before sending the voltage signal to the signal generating unit, so that a waveform signal generated by the signal generating unit regulates its voltage levels according to the received voltage signal before sending the waveform signal to the comparing unit. The comparing unit receives and compares the signals from the signal generating unit and the reference voltage unit, and outputs a comparison signal for driving a fan motor to operate, so that the finally output signal is substantially linear and smooth.

Abstract: A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures.

Abstract: Synchronously stackable double-edge modulated pulse width modulation generators are disclosed. An example pulse width modulation generator includes a ramp generator to generate first and second ramp signals that interact to form a virtual ramp signal; and a comparator module coupled to the ramp generator configured to produce a pulse width modulated signal based on a comparison between the virtual ramp signal and an input signal.