Abstract: A digital transceiver is provided. The digital transceiver includes a clock generator configured to generate a first clock signal having a first frequency of a fixed value and a transmitter driven by the first clock signal of the first frequency to transmit data. Additionally, the digital transceiver includes an inverter coupled to the clock generator to generate an inverted first clock signal of the first frequency. Further, it includes a frequency detector configured to compare the first frequency with a second frequency of a feedback signal in a loop of feedback to determine a frequency control word F. Furthermore, it includes a digitally-controlled oscillator driven by the frequency control word F in the loop of feedback to output a second clock signal with a time-average frequency substantially synchronous to the first frequency with a boundary spread and a receiver driven by the second clock signal to receive the data.

Abstract: Certain aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may tune a first voltage controlled oscillator (VCO) to an offset frequency from a particular frequency, wherein the offset frequency differs from the particular frequency by an offset, wherein the offset is based at least in part on at least one parameter, and wherein the UE is configured to operate in an at least one carrier mode associated with at least one time division duplexed carrier; and communicate, while the first VCO is tuned to the offset frequency, a communication associated with a second VCO, wherein the second is tuned to the particular frequency. Numerous other aspects are provided.

Abstract: An example apparatus includes a first detector configured to generate a first digitized stream of pulses and a second detector configured to generate a second digitized stream of pulses; a first packet decoder configured to decode a first valid over-the-air packet from the first digitized stream of pulses and generate a first time-stamped tag data packet; a second packet decoder configured to decode a second valid over-the-air packet from the second digitized stream of pulses; an arbiter configured to receive at least one of first and second time-stamped tag data packets and to select a time-stamped tag data packet from the at least one of the first and second time-stamped tag data packets; and a packet formatter to formulate a network data packet based on the selected time-stamped tag data packet.

Abstract: Provided is a multi-source signal generator including a voltage-controlled oscillator configured to generate a first source signal having a first frequency to deliver the first source signal to a first output port, a Single Pole Double Throw (SPDT) switch configured to select the first source signal or an external source signal, a first power amplifier configured to amplify power of the first source signal selected by the SPDT switch, and a multi-source converting unit configured to multiply a frequency of the amplified first source signal or divide power of the amplified first source signal to generate multi-source signals, wherein the frequency of the first source signal and frequencies of the multi-source signals are included in a millimeter wave band or sub-terahertz (THz) band.

Abstract: A distributed antenna and backhaul system provide network connectivity for a small cell deployment. Rather than building new structures, and installing additional fiber and cable, embodiments described herein disclose using high-bandwidth, millimeter-wave communications and existing power line infrastructure. Above ground backhaul connections via power lines and line-of-sight millimeter-wave band signals as well as underground backhaul connections via buried electrical conduits can provide connectivity to the distributed base stations. An overhead millimeter-wave system can also be used to provide backhaul connectivity. Modules can be placed onto existing infrastructure, such as streetlights and utility poles, and the modules can contain base stations and antennas to transmit the millimeter-waves to and from other modules.

Abstract: A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is “frozen” to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.

Abstract: Methods and systems are described for generating a first filtered signal by passing signal energy in a first radio frequency (RF) spectral band associated with a signaling bandwidth of an ultra-wideband (UWB) RF signaling system, generating a second filtered signal by passing signal energy in a second RF spectral band associated with the signaling bandwidth of the UWB RF signaling system, generating a plurality of digitized streams of pulses by identifying RF pulses in a respective filtered signal above a respective predetermined threshold, generating at least one time-stamped tag data packet, based on decoding a valid over-the-air packet corresponding to a plurality of RF pulses received according to a known burst pattern, selecting a time-stamped tag data packet from the at least one received time-stamped tag data packet, formulating a network data packet based on the selected time-stamped tag data packet, and outputting the network data packet.

Abstract: A body-coupled communication device (201) adapted to receive signals via a body transmission channel (160), the first device comprising couplers (102) arranged to receive a body-coupled signal, a synchronization-indicator (272) to storing a level of synchronization between the first device and a second device, and a band-pass filter (250) arranged to filter the received body-coupled signal depending on the synchronization level, the band-pass filter being arranged to allow passage of frequencies in a frequency-interval around a tunable filter frequency, wherein the frequency-interval is narrow if the synchronization-level is high and wherein the frequency-interval is broad if the synchronization-level is low.

Abstract: A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.

Abstract: A compensation apparatus compensates a quadrature-demodulated signal output from a quadrature demodulator 5 that performs quadrature demodulation by using a signal of a carrier frequency fc, by removing an image component caused by the quadrature demodulator 5 from the quadrature-demodulated signal. The compensation apparatus includes a signal generator 10 that generates a reference signal having a predetermined bandwidth in a reception band, and provides the reference signal to an input side of the quadrature demodulator 5. The reference signal includes a frequency band that is biased to either a higher-frequency side or a lower-frequency side with respect to the carrier frequency.

Abstract: A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Abstract: A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2), the phase information dynamic range is divided by a factor (e.g., by 2), and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator performs gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source.

Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract: A jitter generation apparatus for applying a phase modulation to a PLL is controlled by a control unit so as to output a signal with the desired jitter based on a parameters. When a switching unit is switched to a first state, the control unit controls first and second level control units so that the desired jitter in which an amplitude of a first modulation signal matches the parameter is added to an output signal from a voltage controlled oscillator unit, and passes through a quadrature modulator. When the switching unit is switched to the second state, the control unit controls the first and second level control units so that a quadrature modulation is applied to a local signal, which is input to the quadrature modulator without adding any jitter to an output signal from the voltage controlled oscillator unit, and a quadrature-modulated local signal is output.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: A method for automatically tuning a frequency modulator in a mobile device is described. A frequency band is automatically scanned using a frequency modulation (FM) receiver. The FM receiver is integrated as a part of the mobile device. Quality associated with channels of the frequency band is analyzed to identify at least one available channel at a first frequency. The first frequency is assigned to an FM modulator. The FM modulator is integrated as a part of the mobile device. A determination is made whether a command to scan for a second frequency is received. If the command to scan for the second frequency is not received, a signal on the first frequency is transmitted by the FM modulator.

Abstract: A two-point phase modulator and a method of calibrating conversion gain of the same are provided. The two-point phase modulator locks an output frequency signal by charging and pumping charge in a phase-locked loop (PLL) circuit at the beginning of operation, opens a loop of the PLL circuit for a period of time, and applies a step signal, thus calibrating conversion gain of a modulation signal that controls the output frequency signal. Thus, the conversion gain may be accurately calibrated by the calibration operation at one time.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band.

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract: A system and method for providing, among other things, wideband phase modulation is described. Several embodiments include a scaling network for scaling an input modulation signal in accordance with a scaling parameter and thereby generating a scaled modulation signal that is applied to a voltage-controlled oscillator of a phase-locked loop. A sensing network may also be included for detecting changes in one or more parameters characterizing the voltage-controlled oscillator. A calibration adjustment network may additionally be included for adjusting the scaling parameter in accordance with the changes in the one or more parameters.

Abstract: A charge pump-based frequency modulator is provided. The charge pump-based frequency modulator comprises an analog phase correction path comprising a varactor and a charge pump. The varactor is coupled to an output of the charge pump-based frequency modulator. The charge pump is coupled to a node between the varactor and the output and receives a signal containing the modulated data.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.

Abstract: A modulation circuit is provided that generates an output signal obtained by modulating an input signal with a local signal and includes a local input section that receives the local signal and generates the local signal and an inverted local signal obtained by inverting the local signal, a signal input section that receives the input signal and generates the input signal and an inverted input signal obtained by inverting the input signal, a first multiplying section that outputs from a terminal that receives the input signal a first multiplied signal obtained by multiplying the local signal with the input signal, a second multiplying section that outputs from a terminal that receives the inverted input signal a second multiplied signal obtained by multiplying the inverted local signal with the inverted input signal, an output section that adds the first multiplied signal to the second multiplied signal and generates the output signal, and a transmission line that sends to the output section the first multipl

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: A frequency modulator includes a tuning circuit configured to determine a nominal gain characteristic of a digitally controlled oscillator (DCO) in a first mode, and to determine an actual gain characteristic of the DCO in a second mode using the nominal gain characteristic. The frequency modulator also comprises a modulation circuit comprising the DCO coupled to the tuning circuit, configured to modulate a frequency of a DCO output signal with a modulation signal input, and to scale the modulated DCO output signal based on the actual gain characteristic in the second mode to provide gain compensation and frequency modulation of the DCO. The tuning circuit may include a select switch to couple a minimal and maximal tuning word to the DCO in the first mode and an actual operating point word in the second mode to the DCO to determine the nominal gain characteristic.

Abstract: A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a +90° or +re/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +re (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator.

Abstract: A two-point phase modulator and a method of calibrating conversion gain of the same are provided. The two-point phase modulator locks an output frequency signal by charging and pumping charge in a phase-locked loop (PLL) circuit at the beginning of operation, opens a loop of the PLL circuit for a period of time, and applies a step signal, thus calibrating conversion gain of a modulation signal that controls the output frequency signal. Thus, the conversion gain may be accurately calibrated by the calibration operation at one time.

Abstract: An apparatus for providing a two point phase/frequency modulation system is disclosed herein. The apparatus includes a first network configured to introduce an offset to center a signal applied to a VCO. The apparatus further includes a second network configured to set a gain of the VCO. A phase tracking network is configured to dynamically adjust the offset and the gain.

Abstract: The modulator according to the invention is based on the modulation of a PLL, with the bandwidth of the PLL being variable. The modulator also has a means (14, 15) for determination of a signal (?r(kTs); FDEV) which is characteristic of the modulation shift of the modulated signal. Furthermore, the modulator contains a comparison means (16) for comparison of this signal with a signal (?(kTs+?); FDEVNOM) which is characteristic of the nominal modulation shift, as well as a means (18) for variation of the bandwidth as a function of the output signal from the comparison means (16).

Abstract: A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events. The synchronization circuit may have an arming input to enable the synchronization circuit to signal a next event. Another clock output divider may be included to generate a timing reference output, and the other clock divider also reset in response to a detected event.

Abstract: Architectures for compensating the frequency drift of an oscillator based frequency synthesizer circuit due to the change of temperature are disclosed. By applying a digitally controlled frequency word which represents the frequency difference between an output signal of a crystal oscillator and a temperature-compensated signal obtained from the output of a frequency synthesizer, the generated frequency signal is controlled so as to be temperature compensated over a wide temperature range. In one embodiment, a frequency locked loop is provided to perform functions to compensate for possible drifts in the reference signal. The frequency locked loop receives a digital frequency corrected control word based on at least a first parameter and a second parameter, wherein the first parameter is a combination of a fixed frequency control word and an automatic frequency correction word, and the second parameter is derived from an external source.

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract: An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a modulation signal, a phase error signal and an oscillator control word. The data alignment device is configured to output a modulation setting word based on the modulation signal, output a time interval magnitude based on the phase error signal and a reference interval, and output an oscillator modulation word based on the oscillator control word. The identification device is configured to adapt and output the gradient factor based on the modulation setting word, the time interval magnitude and the oscillator modulation word.

Abstract: A radio frequency modulator based on direct frequency/phase modulation of output signal of a controllable oscillator (724) that is a part of a phase locked loop (PLL) provides a direct modulator that is able to operate over a wide frequency range with a flat frequency response. A modulation signal is digitally processed (721, 730) before injection to a high-pass path of a direct modulator. Applicability of digital signal processing is based on the fact that the modulation signal is a base band signal. Therefore, the modulation signal (702) occupies such a band in the frequency domain so that a sufficient ratio of a sampling rate to an upper edge frequency of the modulation signal can be achieved. Digital processing is used for compensating an effect of non-flat high-pass PLL transfer function and/or to perform pre-distortion of the input signal of a controlled oscillator to compensate an effect of non-linearity of a controlled oscillator.

Abstract: A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.

Abstract: A multimode-based phase modulating apparatus capable of reducing the degradation of modulation precision and suppressing the unnecessary power consumption. This apparatus has a switch for switching the modulation modes of a PLL circuit between a single-point modulation and a double-point modulation. In a case of a narrow modulation bandwidth, the switch is turned off to cease a second digital baseband signal, thereby causing the PLL circuit to perform the single-point modulation in which only a first digital baseband signal from a frequency division rate generating part is used for the modulation. Contrarily, in a case of a wide modulation bandwidth, the switch is turned on, thereby performing the double-point modulation using both the first digital baseband signal and the second digital baseband signal.

Abstract: A method and apparatus for spread spectrum clock generation is provided. Modulation of the clock signal may be accomplished with an N/N?1 clock divider. The N/N?1 clock divider is configured to divide the clock signal by N or N?1, depending on the carry output signal of an accumulator circuit. The accumulator circuit is configured to provide the carry output signal in response to a modulating waveform signal. The modulating waveform signal may be a triangle wave, a sinusoidal wave, another waveform appropriate for spread-spectrum clock generation, and the like.

Abstract: A polar modulator has a low AM-AM and AM-PM distortion comprises a phase locked loop. The phase locked loop is designed for outputting a high-frequency signal with a frequency derived from a phase modulation signal at an actuating input of the phase locked loop. A filter device, for suppressing a DC signal component, is coupled to an output of the phase locked loop. Furthermore, provision is made of a controllable voltage source with a control input suitable for feeding in an amplitude modulation signal. A push-pull amplifier is connected by an input to the filter device. It comprises two feedback amplifier transistors connected in series, which are connected to a voltage output of the controllable voltage source for supply purposes. Control terminals of the amplifier transistors are connected to the input and, via a load, to an output of the push-pull amplifier.

Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.

Abstract: A direct division modulator is provided. The direct division modulator includes a symbol mapper converting the input data from a binary bitstream to a desired frequency deviation, such as where the frequency deviation data encodes the information from the bitstream. A converter generates a divide value using the desired frequency deviation information, and a summer adds an average value to the divide value. A converter quantizes the divide value and shapes quantization noise associated with the quantized divide value. A divider modulates a reference signal with the quantized divide value and generates an output signal.