Abstract: A DC frequency modulation circuit for modulating audio signals wherein the high frequencies of the audio signals are modulated by a first phase locked loop and the low frequencies of the audio signals, along with the DC signals, are filtered by a low pass filter, applied through an A/D converter, and modulated by a direct digital frequency synthesizer. The two modulated signals are then mixed by a second phase locked loop.

Abstract: A transceiver (10) includes a dual port phase and magnitude balanced synthesizer modulator (60). The modulator (60) couples a modulation input to a voltage controlled oscillator (40) and to a reference oscillator (42) that are coupled together in a phase locked loop (44). The modulator 60 includes a magnitude balancing circuit (64) that divides a modulation input representing data or the like into a first modulation input signal applied to the reference oscillator (42) and a second modulation input signal for the voltage controlled oscillator (40). A phase balancing circuit (68) induces a negative phase shift in the second modulation input signal that is coupled to the voltage controlled oscillator (40) in order to compensate for the phase lag of the reference oscillator loop (44).

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal all a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage, An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A dual port frequency modulator and method for eliminating the undesired affects caused by high port/low port phase differences in a standard dual port frequency modulator. The frequency modulator includes an inverse filter stage coupled to the input of a modulator stage including a first high port processing path for processing high frequency components of a modulation signal and a second low port processing path for processing low frequency components of a modulation signal. The outputs of the high and low paths are coupled to separate ports of a voltage controlled oscillator. The impulse response of the inverse filter is designed to be the inverse of the impulse response of the modulator stage. The filter functions to counter-act the adverse effects caused by the delay difference in the high and low processing paths of the modulator stage such that the overall response of the dual port frequency modulator is significantly improved.

Abstract: For digital transitions from one binary logic level to another by frequency or phase shift of an electric carrier wave the modulation sidebands are reduced by performing each transition by means of several phase steps at small intervals. Equal phase steps at varying intervals are preferred over equal intervals between varying phase steps although both procedures can provide a low-bandwidth transition. This procedure is readily incorporated at low cost in frequency synthesizers. The use of a higher-frequency master oscillator (16) followed by a fixed-ratio frequency divider (17) ahead of a variable-ratio frequency divider (18) makes it easy to shift phase or frequency digitally by small quick steps. Another variable-ratio frequency divider (13) is desirable but not essential in the final PLL between a ultimately controlled oscillator (10) and a loop filter (12) connected to a phase discriminator (11).

Abstract: A PLL circuit modulatable by a modulation signal having a direct current component has a voltage-controlled main oscillator, a loop divider, a phase comparator and a loop filter. The reference frequency signal for the phase comparator is derived from the modulation signal by a first compensation filter, a voltage-controlled reference oscillator and a reference divider being connected downstream of said first compensation filter. The voltage-controlled main oscillator is controlled by the modulation signal via a second compensation filter followed by a downstream data lowpass.

Abstract: The invention relates to a method, in which a phase modulated or frequency modulated signal can be directly generated with a PLL frequency synthesizer. With an interpolating synthesizer it is possible to create a very dense output frequency (f.sub.x) raster, so that the pulses received in the phase comparator (63) both from the reference signal (f.sub.o) branch and from the voltage controlled oscillator VCO (65) are lengthened in lengthening means (62, 69; 67, 68; k.sub.1, L+.DELTA.L; k.sub.2, L) by a desired amount. The numbers k.sub.1 and k.sub.2 are proportional to the amount of lengthening. When these integers now further are changed proportionally to the modulating signal, the change of the integers causes a change of the time difference of the pulses received by the phase comparator (63). This change of the time difference further causes a change in the output signal (f.sub.x) of the voltage controlled oscillator.

Abstract: A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, 190, 220, 264, or 290) includes a phase locking oscillator (70, 90, 128, 180, 192, 222, 266, or 292) and a D.C. modulator (72, 92, 130, 156, 182, 194, 224, 268, or 294). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C.

Abstract: A fundamental or subharmonic optically injection locked oscillator is coupled to a phase locked loop circuit. The injection locked oscillator has two single stage HEMT amplifiers with parallel feedback from the drain of a second transistor to a gate of a first transistor. A feedback resonant network controls the oscillator frequency. A microwave/millimeter wave source modulates a laser diode and the signal from the laser diode is then transmitted via an optical fiber to a PIN photodetector diode. The signal from the photodetector diode is injected into the oscillator at an nth subharmonic of the oscillator frequency. The feedback network may consist of a microstrip gap resonator with two tuning varactors at the ends of the resonator. The phase locked loop includes a balanced mixer used as a phase detector to compare the nth harmonic of the signal from the photodetector diode to the sampled output of the oscillator.

Abstract: Biomedical information is directly digitally telemetered from the patient through a frequency modulated transmitter to a remote receiver and computer station. A phase-lock-loop circuit in the digital transmitter compensates for DC data bias by averaging and generating a scaled measure of the DC content of the digital data fed into the phase-lock-loop circuit. The average signal is then provided as a control signal to a first voltage controlled crystal oscillator, the output of which is then used as a reference frequency for the phase-lock-loop circuit. Frequency modulation of the digital data is provided by coupling the digital data directly into the voltage control input of the voltage controlled oscillator which generates the output frequency. Further control of the phase-lock-loop circuit in the transmitter is achieved by prepositioning the operating frequency of the voltage controlled oscillator by means of a microcontroller.

Abstract: A method of providing DC coupled frequency modulation without center frequency offset of a RF carrier frequency generated in a phase-locked loop circuit. The circuit is automatically calibrated to generate a feedback signal for cancelling DC offsets at the input of the coupling integrator with a digital-to-analog converter and resistor network driven by a digital counter. After removing frequency modulation, the coupling integrator's output will ramp while the offsets remain uncancelled. Incrementing or decrementing the digital counter in response to the integrator's output will adjust the feedback signal until the offsets are cancelled and the integrator ceases to ramp. The counter value is stored in a memory to allow subsequent presetting of the feedback signal to the calibrated magnitude. Holding the feedback signal constant thereafter during DC coupled frequency modulation keeps the RF carrier at center frequency.

Abstract: A digitally compensated modulation system for frequency synthesizers has a single modulation input line with flat frequency response to zero hertz. The above is accomplished while eliminating circuit components and adjustments by integrating reference oscillator temperature compensation, modulation compensation for changes in the voltage controlled oscillator modulation sensitivity and modulation compensation for changes in the reference oscillator modulation sensitivity. Signals requiring modulation enter a microprocessor and are summed together with a microprocessor generated signal and a temperature compensation input to create a composite modulation signal. The composite modulation signal is then multiplied by appropriate constants and sent to the synthesizer.

Abstract: A circuit configuration includes a controllable oscillator issuing an output signal. A phase detector is acted upon by a reference signal and by the output signal of the oscillator. A first charge pump is controllable by the phase detector and has an input connected to the phase detector and an output. A loop filter is connected between the first charge pump and the oscillator for triggering the oscillator. A second charge pump is connected parallel to the output of the first charge pump.

Abstract: A D.C. modulated phase locked oscillator (220 or 264) is usable separately to provide an output that is both phase locked and D.C. modulated or is usable in a radio frequency receiver (200). The D.C. modulated phase locked oscillator (220or 264) includes a phase locking oscillator (222 or 266) and a D.C. modulator (224 or 268). Both a forward path (14) and a feedback path (16) are D.C. modulated. In one embodiment. D.C. modulation of the feedback path (16) includes using a modulation oscillator (64) and two flip-flops (228 and 164) to develop quadrature square waves, and using a quadrature phase shift keying (QPSK) mixer (234) to subtract a frequency of one of the square waves from the frequency in the feedback path (16). In another embodiment, D.C.

Abstract: A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, or 190) and a radio frequency receiver (200) that utilizes the D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, or 190) both include a phase locking oscillator (70, 90, 128, 180, or 192) and a D.C. modulator (72, 92, 130, 156, 182, or 194). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C.

Abstract: A fractional-N type frequency synthesizer has a voltage controlled oscillator controlled in a phase-locked loop by a divide by N divider and a phase comparator responsive to the divided frequency and to a reference frequency Fr. An accumulator is responsive to the desired fractional part of the N and is clocked by Fr to produce carry signals for producing the required periodic variations in N. A second accumulator produces periodic equal and opposite further variations in N to reduce the magnitude of the error waveform which would be given to the phase-detector output by the variations in n caused by the first accumulator. A digital to analog converter and a differentiating circuit produce a jitter correction signal for reducing residual jitter. A coherent detector detects for the presence of any residual jitter at the control input of the VCO and resulting from the fractional-N control circuit.

Abstract: A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

Abstract: A frequency synthesizer for providing a modulated output signal includes a phase comparator, a loop filter, and a voltage controlled oscillator (VCO). The phase comparator receives a reference input signal and a signal related to the VCO output, and generates a control current. A modulation circuit receives a modulation signal and provides both a modulation current and a modulation voltage. The modulation current is summed with the control current at one input of the loop filter, while the modulation voltage is applied to a second input of the loop filter. The VCO is controlled by the output of the loop filter to produce the modulated output signal.

Abstract: In a phase-locked loop type synthesizer comprising a phase-locked loop which comprises a phase comparator, a loop filter, a voltage controlled oscillator having a gain Kv, and a circuit for feeding back an output from the voltage controlled oscillator to the phase comparator through a frequency divider having a frequency division ratio N and which is supplied with first and second modulation signals at first and second sections through first and second adders, first and second gain control circuits are provided on input lines of the first and the second modulation signals, respectively. The first gain control circuit has a first gain adjusted to be in inverse proportion to the frequency division ratio N while the second gain control circuit has a second gain adjusted to be in inverse proportion to the gain Kv. Preferably, the first adder is connected between the phase comparator and the loop filter while the second adder is connected between the loop filter and the voltage controlled oscillator.

Abstract: A transmitter includes a phase-locked loop (PLL) circuit whose output is frequency modulated with a modulation signal. The modulated signal is amplified by an amplifier which is turned on only during a signal transmission of the transmitter. At a time when the amplifier is turned, the output frequency of PLL circuit fluctuates. To depress this frequency fluctuation, the transmitter includes a frequency fluctuation depressing (FFD) circuit. Upon the turning-on of the amplifier, FFD circuit applies a voltage change to the modulation signal so that the frequency fluctuation is depressed.