Abstract: A modulation method and a modulation apparatus in a phase-locked loop (PLL) provided. The modulation apparatus comprises a modulator, a crystal oscillator, a controllable R-divisor frequency divider, a controllable N-divisor frequency divider and a voltage-controlled oscillator (VCO). The crystal oscillator generates a fixed frequency oscillating signal. The controllable R-divisor frequency divider receives the oscillating signal from the crystal oscillator and divides the frequency by R. The VCO generates a frequency signal based on a voltage-controlled signal provided by the PLL and feedbacks the frequency signal to the controllable N-divisor frequency divider. The controller N-divisor frequency divider receives a feedback frequency from the VCO and divides the frequency by N.

Abstract: The present invention relates generally to the field of frequency modulation, and in particular to dual port frequency modulators. The present invention provides a frequency modulator comprising a phase lock loop circuit (108) for receiving and modulating a carrier signal according to the low frequency component of a modulating signal, the phase lock loop circuit comprising a voltage controlled oscillator (118) for outputting a modulated carrier signal and a loop filter (116) for outputting a steering voltage to the VCO, the VCO having a tank circuit (120) comprising a voltage controlled capacitance (VAR1). The frequency modulator also comprises an external voltage controlled capacitance (122) which is arranged to modulate its capacitance according to a high frequency component of the modulating signal, the second voltage controlled capacitance being coupled to the tank circuit.

Abstract: An apparatus and method for synchronizing sampling frequencies of a receiver and a transmitter of a multi-carrier communication system is provided. The receiver includes an estimator for estimating a frequency offset by employing an additional angle rotation of a received signal in frequency domain. The apparatus includes a compensation loop filter for generating a first output in response to a frequency offset compensation, an adder for adding the estimated frequency offset and the first output to generate a second output, and a loop filter for generating frequency offset compensation according to the second output. The method repeatedly applies the apparatus to generate frequency offset compensation, and then feeds it back to an oscillator to compensate the sampling frequency of the receiver. The apparatus and method can also be applied to a communication system with a carrier frequency offset.

Abstract: Provided is a transmission modulation apparatus, using polar modulation of two-point modulation scheme, capable of completing a timing adjustment of a BB phase modulation signal and BB amplitude modulation signal in a short time. A phase modulation section (10) that performs two-point modulation with a PLL circuit is provided with a switch (17) to make the PLL circuit open loop, and when a first delay section (5) corrects the deviation in synchronization between the BB phase modulation signal and BB amplitude modulation signal, the switch (17) is turned off to make the PLL circuit open loop.

Abstract: A method and apparatus improves the stability and noise performance of frequency synthesis and synchronization circuits. A cancellation circuit provides an error signal that is a measure of integrated quantization error in a delta-sigma modulator that controls the ratiometric division factor in a fractional-N phase-lock loop (PLL). The error signal is fed to the loop filter of the phase-lock loop as a correction signal via a differentiator (high-pass filter). The high pass filter removes substantially all in-band components from the cancellation signal, which reduces the linearity requirement on the cancellation signal path. The cancellation signal can be tapped from an internal numerical integrator of the delta-sigma modulator that is then converted to an analog signal, that is then filtered and combined with the phase comparator output in the loop filter.

Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.

Abstract: A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: A phase modulation apparatus is provided whereby excellent RF phase modulation signals can be obtained even when the modulation sensitivity of a voltage controlled oscillator varies. Phase modulation apparatus 100 has: phase detector 105 that performs phase detection with respect to an RF phase modulation signal outputted from VCO 101; comparator 106 that compares the phase of the detected signal with the phase of a baseband phase modulation signal and outputs the difference between the signals; variable gain amplifier 107 that controls the gain of the baseband phase modulation signal based on the output of comparator 106 and supplies the gain-controlled baseband phase modulation signal to VCO 101.

Abstract: A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M?1 and K2=K1+1 when K1<0, makes M1=M and K2=K1 when 0?K1<1, and makes M1=M+1 and K2=K1?1 when 1?K1.

Abstract: A transmission arrangement includes a step-up frequency mixer that converts a modulation signal to a transmission frequency. The step-up frequency mixer is arranged within a phase locked loop that further comprises a frequency divider that is likewise supplied with the modulation data, combined with channel pre-selection data, for the purposes of compensation. This arrangement prevents low-frequency components of the modulation signal from being eliminated by the phase locked loop. In addition, noise components and undesirable interference frequency components that are produced in the mixer are suppressed by the phase locked loop.

Abstract: First and second calibration signals (308, 309) are sent to a frequency divider (102) and an adder (116) of a PLL section (100A), demodulated in a demodulator (111), filtered through a low pass filter (113) and a high pass filter (114) and thereafter sent to a modulation signal control circuit (115). The modulation signal control circuit (115) generates control information (318) in comparison with the phase and amplitude of the first and second calibration signals (308 and 309) and sends the control information (318) to a modulation control signal generator (106). Modulation control signal generator (106) holds the control information (318) and controls the values of the first modulation signal and second modulation signal sent to the frequency divider (102) and adder (116) on the based on the control information (318) held in modulation operation.

Abstract: A PLL circuit is tuned to a first frequency by using a first digital modulation signal and subsequently tuned to a second frequency by using a second digital modulation signal. A differential signal, that is a function of the change in voltage of a VCO control signal generated by the modulation signals, is compared with a comparison signal, that is characteristic of the analog modulation amplitude. Based on the comparison the analog modulation amplitude is changed to minimize or substantially eliminate a deviation between the signals.

Abstract: A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

Abstract: A two-point modulator includes a PLL circuit and a simplified digital pre-filtering system. The two-point modulator includes a first circuit path for impressing an analog modulation signal into a first point in the PLL circuit, and a second circuit path for impressing a digital modulation signal into a second point in the PLL circuit. The second circuit path actuates a frequency divider in the feedback path in the PLL circuit and contains a digital filter which has a square-wave pulse response.

Abstract: A system for direct modulation is disclosed. Embodiments of the direct modulator for shift-keying modulation include impressing baseband data on a radio frequency (RF) signal at an oscillator by controlling a digital divider using a sigma-delta modulator.

Abstract: A variable frequency synthesizer comprising a sigma-delta modulator is provided. Such synthesizers provide an exact average frequency whereas the instantaneous frequencies varies. The sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade. At least one input value of an accumulator (51, 52, 53, 54) being part of the sigma-delta modulator has a second component which is equal to an overflow signal (of1, of2, of3, of4) multiplied by a factor. This feedback reduces the-maximum fluctuation of the instantaneous frequencies. Phase jitter generated by non-linearities of the phase detector, the charge pump and the VCO is therefore reduced.

Abstract: A method includes identifying a setting for a capacitor bank associated with a voltage-controlled oscillator in a closed-loop phase-locked-loop. The setting represents a combination of one or more capacitors in the capacitor bank. The method also includes estimating a gain introduced by the closed-loop phase-locked-loop when the oscillator operates using the identified setting. The method further includes estimating a response of a loop filter in the phase-locked-loop and identifying one or more coefficients for a digital filter using the identified gain and the identified loop filter response. The digital filter is operable to filter an input signal. In addition, the method includes modulating the filtered input signal using the phase-locked-loop to produce an output signal.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: A fractional-N frequency synthesizer using the first order Delta-Sigma frequency discriminator which is composed of only a dual modulus frequency divider and a D flip-flop is used to replace the function of phase detector is disclosed. The invented structure is characterized by generating the feedback error signal indirectly from the output bit stream of said discriminator in such a way that the quantization noise contained in the bit stream is maximally canceled by comparing it with another bit stream generated by an accumulator digitally performing the first order Delta-Sigma modulation to the required fractional number, so that there is almost no discrete fractional spurs in the output spectrum of the synthesizer. Most other circuit of the synthesizer could be formed digitally so that high integration level and low noise performance could be achieved. Narrow or wideband phase or frequency modulation could also be conveniently added digitally with good accuracy.

Abstract: In the case of a trimming method for a PLL circuit operating based on the principle of a two-point modulation, the PLL circuit is locked without any modulation being impressed and then an analog and a digital modulation signal are impressed into the locked PLL circuit. A signal that is characteristic of the PLL control error is tapped from the PLL circuit, and the modulation swing in the analog modulation signal is changed such that the characteristic signal has the same value as before the analog and digital modulation signals were impressed.

Abstract: A method includes identifying a setting for a capacitor bank associated with a voltage-controlled oscillator in a closed-loop phase-locked-loop. The setting represents a combination of one or more capacitors in the capacitor bank. The method also includes estimating a gain introduced by the closed-loop phase-locked-loop when the oscillator operates using the identified setting. The method further includes estimating a response of a loop filter in the phase-locked-loop and identifying one or more coefficients for a digital filter using the identified gain and the identified loop filter response. The digital filter is operable to filter an input signal. In addition, the method includes modulating the filtered input signal using the phase-locked-loop to produce an output signal.

Abstract: A phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, and a frequency translation module. The difference detector is operably coupled to determine a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The loop filter is operably coupled to generate a control signal from the difference signal. The controlled oscillation module is operably coupled to produce, in accordance with an adjustable operating parameter, an output oscillation based on the controlled signal. The adjustable operating parameter is set based on desired operating conditions of the phase locked loop such that false locking of the phase locked loop is substantially avoided. The frequency translation module is operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.

Abstract: An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test.

Abstract: A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract: A system is provided for compensating for tuning gain variations in a phase lock loop. Compensation is performed by a calibration system that estimates the tuning gain of the oscillator and then adjusts the charge pump current value by a ratio of the nominal tuning gain to the measured tun gain. The tuning gain measurement is performed by measuring the change in the voltage controlled oscillator's tuning control voltage when the phase lock loop is locked to two different frequencies, which are separated by a fixed, predetermined amount. The two frequencies may be above or below the final output frequency of the VCO, or the second frequency may be the final frequency in order to reduce calibration time and settling time.

Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

Abstract: There is provided a method of synchronizing a phase-locked loop (PLL) which is capable of reducing an area occupied by the PLL in a chip of the semiconductor device and shortening a lock-up time even when a band of an oscillation frequency is wide and a changeable range of a multiplying factor is wide.

Abstract: Phase-locked loop methods and structures are provided for generating modulated communication signals with nonconstant envelopes. These methods and structures realize the improved communication performance of nonconstant-envelope modulations with the upconversion advantages of phase-locked loops. The structures include transmitters in which a phase-locked loop is augmented with first and second feedforward paths that substantially restore phase and amplitude information to a transmit signal that is generated by a voltage-controlled oscillator of the phase-locked loop. The first feedforward path is configured to realize a path transfer function of s/Kv wherein the voltage-controlled oscillator has a transfer function of Kv/s. The second feedforward path extracts an envelope-correction signal from the modulated intermediate-frequency signal and a variable-gain output amplifier amplifies the transmit signal with a gain that responds to the envelope-correction signal.

Abstract: A method and apparatus are disclosed for tuning a voltage controlled oscillator (VCO) having two point modulation used in a phase lock loop modulation system. A loop correction voltage applied to a first modulation input of the VCO when a first modulation signal, e.g., +1, is applied to a second modulation input of the VCO is compared to a loop correction voltage applied to the first modulation input when a second modulation signal, e.g., −1, is applied to the second modulation input of the VCO. The comparison produces a correction signal used to adjust the signal level of at least one of the signals, e.g., the second modulation input signal, applied to the two modulation inputs of the VCO.

Abstract: PLL frequency synthesizers and their calibration techniques are described. The PLL frequency synthesizers are used to generate digital modulation of a carrier signal. A digital frequency divider in the feedback path of the loop has its division ratio controlled by a digital &Dgr;-&Sgr; modulator. The modulation of the carrier is achieved by applying a modulation signal to the input of the &Dgr;-&Sgr; modulator and to the input of the voltage-controlled oscillator of the PLL. The high frequency path and low frequency path of the modulation signal must be adjusted with respect to one another in order to obtain a good modulation. As the low frequency path can be accurately set, the calibration is performed only on the high frequency path. Digital calibration techniques for the high frequency path are described.

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract: A frequency modulator having variable carrier frequency is provided. A VCO frequency-modulates an oscillator input signal using an oscillation frequency set by a set signal as the carrier frequency. A phase/frequency detector outputs phase and frequency differences between a VCO output signal and a reference signal. A filter receives a phase/frequency detector output and generates the set signal. An amplifier generates a pair of output signals whose voltage levels change in opposite directions. A compensation circuit changes the voltage levels of the output signal pair and provides resulting signals to the VCO as the oscillator input signal.

Abstract: A method for radiofrequency (RF) transmission of digital information includes generating an RF signal using a voltage-controlled oscillator (VCO), stabilizing the RF signal from the VCO by providing an error signal from a phase-locked loop (PLL) to an input of the VCO, and combining the digital information with the error signal of the PLL input to the VCO, thereby causing variations in frequency of the RF signal from the VCO that represent the digital information. Apparatus for RF transmission of digital information includes a VCO, the VCO arranged to generate an RF signal, a PLL, the frequency input of the PLL coupled to the RF signal output of the VCO, an encoder, the encoder arranged to convert the digital information into a form where it has a data rate faster than a response time of the PLL, and a coupler, the coupler coupling both the error signal output of the PLL and the encoded digital information to an input of the VCO.

Abstract: A frequency modulator having variable carrier frequency is provided. A VCO frequency-modulates an oscillator input signal using an oscillation frequency set by a set signal as the carrier frequency. A phase/frequency detector outputs phase and frequency differences between a VCO output signal and a reference signal. A filter receives a phase/frequency detector output and generates the set signal. An amplifier generates a pair of output signals whose voltage levels change in opposite directions. A compensation circuit changes the voltage levels of the output signal pair and provides resulting signals to the VCO as the oscillator input signal.

Abstract: A frequency modulator (50, 150) for modulating a carrier signal according to a modulation data signal to provide a modulated output signal (RFout), comprises a reference signal generator (54, 154) coupled to receive the modulation data signal for performing a low frequency modulation process and for generating a reference signal modulated according to the modulation data signal, and a main synthesizer (52, 152) coupled to receive the modulated reference signal and the modulation data signal for performing a high frequency modulation process and for providing the modulated output signal at an output. Preferably, the modulated reference signal has a first modulation gain (Kr) and the modulated output signal has a modulation gain (KV) which is substantially proportional to the first modulation gain (Kr).

Abstract: A frequency synthesizer with a digital frequency lock loop (FLL) having a fast frequency lock time uses a frequency counter circuit in the feedback loop to count the output signal frequency and produce frequency count data. A modulation control circuit provides modulation data and a corresponding modulation control signal for modulating the FLL signal source. A microprocessor processes the frequency count data along with the modulation data to provide a frequency control signal for controlling the nominal, or center, frequency of the FLL signal source. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more consistently notwithstanding the presence of modulation within the feedback loop signal.

Abstract: This device includes a frequency synthesizer (12) comprising two phase-locked loops (L1 and L2). The one comprises a low-pass filter (68) and the other a high-pass filter (49). The loop with the low-pass filter fixes the basic frequency of the synthesizer and the other corrects the phase noise. With this arrangement it is easy to apply a modulation frequency to the terminal (11) that is not disturbed by said loops if this modulation frequency is found to be higher than the cut-off frequency of the low-pass filter.

Abstract: The signal source of the reference frequency of a PLL 20 is composed of a VCO 24. A VCO 14 is provided. A first audio signal (L+R) is supplied to the VCO 24 so as to control its oscillation frequency f24. A second audio signal (L−R) is supplied to the VCO 14, so that an FM signal SSUB is formed whose occupied frequency band is outside the band of the first audio signal (L+R). This FM signal SSUB is supplied to an adder 26, hereby added to a phase comparison output that is supplied to a VCO 21 from a low-pass filter, and then supplied to the VCO 21.

Abstract: A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tuning port for controlling the frequency of the signal 110 output by the VCO, a variable divider 20 and a multi-accumulator sequence generator 21 for controlling the variable divider, a reference signal generator 50, a phase detector 30 and a low pass filter 40. These elements are arranged to form a Phase Locked Loop arrangement, the directly modulated output signal of which is taken from the output of the VCO, wherein in-band modulation is performed by varying the variable divider and out-of-band modulation is performed by directly applying the modulating signal to the VCO tuning port.

Abstract: The present invention relates to a frequency modulated system, and a method for operating same, including a phase locked loop frequency synthesizer circuit which synthesizes a carrier frequency through the use of an electronically controlled oscillator. The circuit, which has a certain loop bandwidth, includes a reference frequency source and a bypassed correcting integrator. A modulating signal simultaneously modulates the oscillator, the reference frequency source and the bypassed correcting integrator such that the carrier frequency is frequency modulated with a certain frequency deviation. The magnitude of the modulation of the oscillator, the reference frequency source and the correcting integrator are controlled over a frequency range by frequency blending the reference frequency source and the bypassed correcting integrator such that low distortion modulation over a wide frequency range is achieved.

Abstract: In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (100) architecture is implemented. The frequency of the FMPLL (100) is controlled using a current controlled oscillator (ICO) (126). The ICO (126) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (126) associated with the FMPLL (100) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO 126. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced.

Abstract: The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direct modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints.

Abstract: A frequency modulation (FM) radio transmitter, such as a cellular telephone, includes an automatic deviation control system to automatically compensate for varying sensitivity of the FM transmitter. The FM transmitter includes a phase lock loop including a controlled oscillator that produces a frequency modulated input signal on an output channel frequency in response to a control input that is applied thereto. A scaler is responsive to the input signal and to at least one scaling content, to scale the input signal based upon the at least one scaling constant and to provide the scaled input signal to the phase lock loop to produce the frequency modulated input signal on the channel frequency. An automatic deviation control system measures the control signal that is applied to the controlled oscillator when tuned to one of the plurality of output channel frequencies and updates at least one of the scaling constants based upon the measured control input, to thereby provide automatic deviation control.

Abstract: The present invention, generally speaking, provides an RF modulator that allows precise, stable phase shifts to be obtained. The modulator uses a PLL structure including an auxiliary feedforward path used to inject a baseband modulation signal into the PLL at a point past a loop filter of the PLL. A phase demodulator recovers phase information from the output signal of the PLL. The recovered phase information is compared to the phase information of the baseband modulation signal. A resulting error signal is used to control injection of the baseband modulation signal into the PLL, to automatically achieve the correct "dosage." A precise, adaptive, phase-stable modulator results. The adaptation of the modulator compensates for variability of the VCO and other components of the PLL.

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal at a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage. An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form.

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and the divided signal, and thereby produce a first error signal. A sigma-delta modulator is responsive to a modulation input to produce the divider control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide a three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Abstract: Signal processing apparatus (410) includes a phase-locked oscillator (200, 236, 310, 330, 390), having a closed loop with both forward (204) and feedback (206) paths, that is a part of a larger closed loop (438). The larger loop (438) is phase locked to the phase-locked oscillator (200, 236, 310, 330, 390) by a signal derived from the larger closed loop (438) that modulates the feedback path (206), and by an output frequency of the phase-locked oscillator (200, 236, 310, 330, 390) that is delivered to the larger loop (438). Modulating the feedback path (206) either adds pulses to the feedback path (206) or removes pulses, thereby causing irregularities in the flow of pulses. A low-pass filter (210) in the feedback path (206) obviates these irregularities, thereby also obviating incidental frequency modulation (IFM) in the output of the phase-locked oscillator (200, 236, 310, 330, 390).