Abstract: Disclosed is a method and apparatus for flexibly converting an electrical parallel digital data signal to a serial optical digital data signal for transmission along a fiber optic cable and then subsequent conversion back to a parallel electrical digital data signal. An input conditioner circuit is used to set a ratio between a transmission link clock rate and a sample clock rate such that the ratio determines the number of bits being transmitted for a sample word thus enhancing the flexibility of the device to different sampling rates. Each individual sample word is a frame of data which includes a single frame bit set up in a 4-bit frame pattern. A first frame bit is a sync acquisition bit comprised of an alternating sequence of "0"s and "1"s, a second and fourth parity bit computed from the parity of the previous two words of data, and a third channel identification bit. An output conditioner circuit receives the serial stream of data bits to convert it back to a parallel data format.

Abstract: The run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words.

Abstract: A serial-to-parallel converter circuit includes a reduced number of gate circuits necessary to configure the circuit. In the converter, each of the register blocks is constituted with an R-S flip-flop circuit including two NAND gates and an NAND gate to select the flip-flop circuit. A decoder selects one of the register blocks according to an accumulation value of serial clocks received by a counter, thereby setting data received via a data input terminal to the selected register block.

Abstract: A ratio latch included in each slave latch is formed of a tri-state inverter and a weak inverter. During a period when a parallel input signal is supplied to the ratio latch in each master latch in response to a trigger clock signal, the tri-state inverter attains a high impedance state in response to an inverted trigger clock signal.

Abstract: A serial interface circuit for performing operations in a plurality of modes is disclosed, which includes an input terminal supplied with a serial data, a first shift register fetching and shifting data at the input terminal in synchronism with a clock signal, a selector for selecting the input terminal in a first mode and an output of the first shift register in a second mode, a second shift register fetching and shifting data at an output of the selector, a set of first output terminals, a set of second output terminals, and an output control circuit outputting first data derived in parallel from the first shift register and second data derived in parallel from the second shift register to the first and second output terminals in the second mode and one of the first and second data to one of the first and second output terminals in the first mode. The respective operations in the first and second modes are thus performed. The output control is favorably incorporated with a bit order reversing function.

Abstract: A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

Abstract: An encoding circuit converts successive bits of the original data to successive bits of coded data at a coding rate equal to m/n, where m and n are each an integer satisfying m<n, in accordance with a rule of a run-length-limited coding system and contains an encoder which inputs parallel m bits of the original data, and outputs parallel n bits of coded data corresponding to the input. Successive bits of data which are to be encoded are cyclically divided into a plurality of groups, and the data in the plurality of groups are input in a plurality of shift registers, respectively. Each of the plurality of shift registers simultaneously supplied a part of the m bits of the input to the encoder, synchronizing with a clock. The n bits of the output of the encoder is received in parallel in another shift register, and are serially output from the shift register, synchronizing with a second clock.

Abstract: A serializer/deserializer encoder-decoder for a disk drive achieves increased storage capacity through the use of partial response maximum likelihood class IV (PRML-IV) coding. Reduction of hardware requirements is realized by the integration of similar read and write mode functions into common circuit elements in order to reduce duplication. To this end, a data word selector selectively receives or sends data words in the write/read mode, respectively, from a data sequencer. Dependent upon the mode the data words are either provided to an encoder or received from a decoder for translation to/from code words. The encoder-decoder sends or receives the code words to a code word selector which in turn connects with the serializer-deserializer for coupling with the write or read channel.

Abstract: High-speed sampling apparatus includes a first source of sampling pulses exhibiting a first sampling frequency and a first sampling circuit coupled to receive an input signal and responsive to the sampling pulses to produce first signal samples. A second source of sampling pulses exhibiting a second sampling frequency is provided; and a second sampling circuit is coupled to the first sampling circuit to receive predetermined ones of the first signal samples and is responsive to the sampling pulses at the second sampling frequency to sample the predetermined first signal samples so as to produce therefrom second signal samples.

Abstract: A drive device with a data latch circuit which is formed of a plurality of latches, which successively latch serial drive data and output them in parallel, and a shift register having a plurality of first flip-flops which provide, responsive to clock pulses, latch signals for causing the latch to latch the serial data in succession. In one aspect of the invention, the shift register also outputs an end signal when output of the latch signals is completed, and a gate circuit which blocks input of the serial data to the data latch circuit responsive to the end signal.

Abstract: A serial-parallel converting circuit comprises a four-stage shift register circuit receiving a serial data so as to shift the received serial data through the shift register in response to each clock signal, and an output register circuit coupled in parallel to respective stages of the shift register circuit so as to fetch the content of the shift register circuit in response to a frequency-divided clock supplied from a frequency dividing circuit. The frequency dividing circuit receives the clock signal through an inverter and is composed of only two D-type flipflops and one inverter. Each of the D-type flipflops has a clock input connected to receive the clock signal in common, and the D-type flipflops are connected in series to form a shifter register. A Q output of a second flipflop is connected through the inverter to a data input of a first flipflop, so that the Q output of the last flipflop generates the frequency-divided signal.

Abstract: Current switching apparatus including at least one current switching tree comprised of cascaded sets of switching circuits, with an input set operable with sampling clock pulses supplied at a fixed frequency and the remaining cascaded sets operable at different frequencies, and further including a sample skipping circuit interconnected between successive sets for reducing the effective sampling frequency of the switching tree while maintaining the fixed frequency at which the input set operates. The sample skipping circuit includes a dump circuit selectively energized to dump selected samples produced by the input set. When the apparatus is formed of plural switching trees of different phases, a sampling clock generator having an adjustable delay circuit is used to delay sampling clock pulses by adjustable amounts so as to establish predetermined phases of sampling clock pulses of the same frequency and different phases for use in each switching tree.

Abstract: A partial word to full word parallel data shifter comprises 2N-1 multiplexer for selectively receiving data from the incoming current data word of width up to N, or from remainder bits of previously received data. The multiplexers output their data to 2N-1 latches, N of which output a full parallel data word and N-1 of which can recirculate up to N-1 remainder bits back to the multiplexers. If the number of remainder bits plus the number of data bits for the currently received word is less than N, the bits in the first N latches are not output but rather recirculate to the multiplexers where they are aligned for generating a full N bit output word with the most significant bit(s) of the next incoming parallel data.

Abstract: In a cell delineation circuit, an input signal is converted into parallel signals, and a plurality of parallel signals (i.e. series of parallel signals) which are shifted one bit by one bit from each other are formed from those parallel signals. CRC (Cyclic Redundancy Check) calculations are executed in parallel for the plurality of parallel signals. A series in which a pattern to be calculated satisfies a CRC rule is determined from results of the CRC calculations, and this series is generated, thereby establishing a cell delineation.

Abstract: An asynchronous serial data receiver utilizes plural samples of each data bit in a word to assure detection and reading of the midpoint of each bit to mitigate problems associated with noise and mismatches between the data and sampling rates. To this end, a shift register having plural stages for each bit samples the data stream at a clock rate which is a multiple of the data rate which provides multiple samples of each incoming bit. When the data word is fully read into the shift register the start bit is detected and initiates a parallel transfer of the data word using bit values taken from the midpoint of each bit period.

Abstract: A block encoded main signal and a balanced block encoded auxiliary signal are combined on a transmission path. The combined signal includes at least one block of encoded main channel signal alternating with one bit of the auxiliary channel signal. The block code for the auxiliary channel is simpler than the block code for the main channel.

Abstract: A serial data receiving circuit comprising a most significant bit input detecting circuit (20) for providing a given control signal in synchronism with input of the most significant bit of a serial data represented by twos complement and a data converter circuit (30B) for subjecting the serial data to a sign extension data when the control signal is active and providing the resultant sign extended data as a parallel data and shifting the serial data from a low order bit to a high order bit when the control signal is inactive and providing the shifted data as a parallel data.

Abstract: A signal generator having a Johnson counter including a plurality of flip-flops having CLOCK inputs to which a clock signal is inputted; a logic gate to which the clock signal and Q outputs of the flip-flops are inputted, the logic gate being constructed such that the clock signal is passed therethrough each time 2n clock pulses of the clock signal occur and that the logic gate outputs its output as a first signal, n representing the number of the flip-flops of the Johnson counter; and delay means for delaying the clock signal by a time corresponding to an input-output delayed time of the logic gate and for outputting the delayed clock signal as a second signal.

Abstract: A substantially simultaneous digital data regeneration and deserialization technique for communication systems and information and data processing systems is disclosed. A digital phase lock logic circuit (DPLL) receives the serial stream of clock and data bits at its input and outputs a plurality of clock signals with different phase. A plurality of latches are coupled to receive a respective one of the clock output signals from the DPLL. Each latch receives the serial stream of clock and data bits through a second input such that the latches are sequentially set by substantially simultaneously received clock and data information at the two inputs and the serial data bits within the stream appear as parallel data bits at the latch outputs. Enhanced versions of this circuit are also described, along with an alternate embodiment which uses an analog phase locked loop circuit.

Abstract: A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.

Abstract: A circuit for parallel-to-serial or serial-to-parallel conversion uses a multi-stage structure for conversion of long data words section-by-section. Each section of the data word corresponds to length/width of the respective registers or latches of the circuit which are successively controlled by an executive sequencer to process the data word in these smaller sections. The section-by-section conversion provides, for a high data rate, a reduction in clock loading and power dissipation.

Abstract: Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data.

Abstract: A format converting system includes a first converter which converts an input signal into N parallel signals (N is an integer). Each of the N parallel signals has a bit rate less than that of the input signal. A latch circuit temporarily latches the N parallel signals in accordance with a clock signal and outputs a plurality of latched signals having a number larger than the N. A selector selectively outputs the latched signals from the latch circuit and stuff bits to be inserted in the N parallel signals in accordance with a control signal so that N parallel output signals having the N parallel signal and the stuff bits are output from the selector. The stuff bits are used for converting a frame format of the input signal into a different frame format.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: An arbitration circuit (10) is provided for selecting between a serial port (19) and a parallel port (21) for interface with a system port (17) having a system data bus (14) and a system address bus (16). A RAM (12) is supported by the buses (14) and (16). The arbiter (10) is operable to store a count value in an arbitration byte (38) which is addressable by the parallel port (21). The serial port (19) is operable to transfer data through a serial/parallel converter (30) to the system data bus (14) and system address bus (16) during a serial port access window. The parallel port (21) is allowed to access the system data bus and address bus at all other times. A count value indicating the duration of time before occurrence of the access window is stored in the arbitration byte (38) and is accessible by the parallel port and a parallel CPU (24) to determine when address and data information can be transmitted to the arbiter (10) for transfer to RAM (12).

Abstract: An asynchronous serial data receiver for receiving a stream of data bits, characterized by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognizing points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronized with the incoming data.

Abstract: In Trellis coded modulation system in which an input digital signal in parallel form is encoded by a convolutional encoder which adds an additional bit to the input digital signal for error correction purpose, and a mapping circuit designated amplitude and phase for each symbol for QAM signal, the number of parallel bits at output of said convolutional encoder is the same as the number of parallel bits of an input digital signal. An input digital signal is first rate converted so that m+n bits in every T period is converted to m bits in every T' period, where T'=(m/(m+n)).T. The convolutional encoder adds n number of bits so that the total number of parallel bits is m+n, which is applied to the mapping circuit. In a receive side, a received signal having m+n bits in every T' period is decoded through an error correction decoder which provides m bits in every T' period, then, the decoded signal is rate converted to m+n bits in every T period.

Abstract: An original digital signal is converted into either a Miller-squared code signal or a Miller code signal, and undergoes serial-to-parallel conversion to produce n-phase signals (where n is desired to be a positive even number). N-phase virtual demodulated signals are simultaneously generated at clock timing having a period equivalent to 1/n times the period of the transmission clock. Out of the n-phase virtual demodulated signals, n/2 phases are selected to undergo parallel-to-serial conversion, the original digital signal being thus obtained.

Abstract: A system for bit character synchronization of an 8/10 bit code being deserialized is provided by a deserializer with a skip bit function input used to move a character boundary one bit at a time, and 8/10 code error detector, a zero disparity character detector and skip pulse generator. After character sychronism is lost, the skip pulse generator is permitted to generate a skip pulse if the following sequence occurs: all bits of the old character boundary have been flushed through the logic circuits, at least one non-zero disparity character has been detected, and an 8/10 code error is detected. After character synchronism is re-acquired, then the skip pulse generator is no longer permitted to generate a skip pulse.

Abstract: A digital code modulation circuit converts input data formed of sequentially received serial data into parallel data such that each parallel data has input data for reference in both preceding and following parallel data, and thereupon applies a code conversion to the parallel data and thereby executes modulation of the input data in parallel. Conversely, a digital code demodulation circuit applies a code conversion to input data formed of serial data sequentially input thereto to form parallel data such that each parallel data has input data for reference in both the preceding and following parallel data and thereby executes demodulation of the input data in parallel.

Abstract: A multiphase memory array is read out using two multiplexers and a demultiplexer under the control of a state machine. The state machine enables one portion of the memory array at a time using a gate to multiplex the memory portion outputs. While a particular portion is enabled, a bit multiplexer associated with that portion is directed by the controlling state machine to sequentially select each bit at the current address in that memory portion for output. A shift register demultiplexer performs serial to parallel conversion on the sequential bits from each memory portion to convert them to a readback byte or word for output. After the byte or word has been read out, the state machine enables the next portion of the memory array and repeats the multiplexing and demultiplexing process for the data at the same address in that memory portion. When all of the memory portions have read out, the address to the memory array is changed and the whole process is repeated for the data at the new address.

Abstract: A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.

Abstract: A data reception device extracts serial, unipolar data from both current mode and voltage mode differential transmission links and converts such data into parallel data suitable for use by end-user equipment.