Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: A variable length coder and encoding method of a video coder is disclosed. The present variable length coder includes a code buffer, a length buffer, and a bit packer of one register and one counter. Accordingly, the present invention allows a VLC with a compact size as well as lower power consumption.

Abstract: A parallel-serial conversion circuit includes a frequency divider circuit which outputs a dichotomized signal of an input clock signal. A positive edge triggered flip-flop and a negative edge triggered flip-flop receive data and the dichotomized signal is input. A tap signal generator receives the clock signal and generates and outputs a series of tap signals by providing different delays to the clock signal. A selection signal generator receives the tap signals and generates a series of pulse signals having the width equivalent to 1 bit of serial data. An inverter circuit inverts the dichotomized signal. A 10-bit parallel-serial converter receives data from of the flip-flops, a signal of the inverter circuit, and the pulse signals. The 10-bit parallel-serial converter performs parallel to serial conversion based on the input data and signals and outputs the serial data.

Abstract: A method for monitoring at least one telephony communication n-bit channel, wherein one of the bits is a parity bit, includes sampling the parity bit of the n-bit channel. A probable bit error rate is derived from the sampling of the parity bit. The probable bit error rate can be compared to a pre-determined bit error rate value to determine if the at least one telephony communication n-bit channel is corrupted. If the at least one telephony communication n-bit channel is corrupted, the at least one telephony communication n-bit channel is re-allocated to an uncorrupted and unallocated telephony communication n-bit channel. Further, at least one unallocated telephony communication channel can be periodically monitored and error data accumulated to indicate the quality thereof.

Abstract: An HFC return path system for digital communication signals using a sampled RF word interface to headend demodulators, provides higher performance equipment at an equivalent or lower cost and more flexible and efficient interfacing and traffic multiplexing. The return path signal from the fiber optic node to the headend/hub is represented ones and zeroes, and the digital return receiver at the headend/hub includes an optical receiver for receiving the serial stream of optical ones and zeroes and converting the optical digital signal to an electrical digital signal, a deserializer for deserializing the serial stream of digital words and synchronization information into parallel digital words, a digital filter for processing the deserialized digital words to interface digitally to an application receiver and a digital interface for interfacing and forwarding the processed parallel digital words to the application receiver.

Abstract: An image signal processing circuit (102) includes a phase-expansion circuit (103), a digital polarity-inversion circuit (104), first to sixth D/A converters (111 to 116), and first to sixth operational amplifiers (151 to 156). The resistance value of the first to sixth amplitude adjusting resistors (121 to 126) which cause the output amplitude of an analog signal output from the first to sixth D/A converters (111 to 116) to be fixed is adjusted by laser trimming. First to sixth gain setting resistors (161 to 166) are connected to the first to sixth operational amplifiers (151 to 156). The first gain setting resistor (161) includes a first resistor (131) and a second resistor (141), and the gain of the operational amplifier (151) is set by the resistance ratio (R2/R1) thereof. In order that this resistance ratio (R2/R1) is fixed for each set, the first resistor (131) and the second resistor (141) are formed on the same substrate by undergoing the same manufacturing process.

Abstract: Techniques and circuitry are provided to handle high frequency input data. The techniques and circuitry take a high-frequency serial input data stream and covert it into parallel form for handling within the integrated circuit. The circuitry ensures the high frequency data is strobed properly by accounting for skew between the high frequency data input and clock input. In an implementation, multiple clock strobes are generated having the same frequency but different phase. A predetermined series of bits is input to the high frequency input into the circuitry for training. One of the multiple clock strobes is selected based on which one correctly determines the bits in the predetermined input data stream. This clock strobe is selected to strobe the high frequency data input for the integrated circuit. In an embodiment, the high frequency data input is an LVDS input of a programmable logic integrated circuit.

Abstract: A receive deserializer which regenerates parellel data words that have been broken into smaller data words and serially transmitted over multiple data channels uses an external state machine to shift word clocks with respect to data until the output of the channel last to receive a predefined data reference pattern is framed and provides storage to hold data for the channels which receive the reference pattern earlier.

Abstract: A method for use in a data transmission system comprises the steps of: (i) adding timing information to a serial data stream; (ii) recovering the timing information from the serial data stream to generate a plurality of clock signals associated with the timing information, each clock signal having a common frequency and a different phase associated therewith, the common frequency being less than a frequency associated with the serial data stream; and (iii) converting the serial data stream to a plurality of parallel data streams respectively using the plurality of clock signals. The timing information may be added to the serial data stream at a data transmitter portion of the system. The invention provides for various ways to add the timing information to the serial data stream, i.e., enrich the serial data stream with the timing information. This timing information is preferably phase locked to the data and has a frequency less than the serial data transmission rate.

Abstract: A serial-parallel converter which includes a plurality of data extraction units for sequentially extracting different bit values of serial data, which are sequentially inputted, for individually holding the different bit values for a time period corresponding to the same number of cycles of a clock signal as the number of the data extraction units until the plurality of data extraction units extract next bit values of the serial data; a delay unit connected to the plurality of data extraction units for receiving the data signals from the plurality of data extraction units and delaying the data signals to generate delay signals which synchronize with each other; and a parallel register connected to the delay unit for receiving the delay signals from the delay unit for latching the delay signals to output the delay signals simultaneously as parallel data.

Abstract: Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.

Abstract: A digital delay line, comprising adjustable digital delay elements, receives and buffers an incoming bit stream by repeatedly delaying bits of the bit stream for a specific period of time. The outputs of selected adjustable digital delay elements are tapped for inspecting in parallel a specific pattern of bits of the bit stream. A programmable counter counts bit periods and generates a latch control signal to latch those specific bits at any offset within the bit stream before the entirety of the bit stream is received.

Abstract: A serial communication interface is provided in which the data length operating mode is selectable. Based on the selected data length operating mode, serial-to-parallel and/or parallel-to-serial conversion takes place in data blocks of the selected data length.

Abstract: A digital image signal is latched by four latches respectively in response to four latch clock signs, which have a frequency that is ¼ of a frequency of a dot clock signal and phases that are mutually shifted by every period of the dot dock signal. The four latched digital image signals are further latched by a common latch in response to a common latch signal. The digital image signals with respect to four consecutive pixels are then output as one set of digital image signals. The output digital image signals are written into consecutive storage areas in a frame memory, in response to a write sampling dock signal which has a frequency that is ¼ of the frequency of the dot clock signal The number of latches is regulated according to a frequency of an analog image signal. This arrangement facilitates image processing for high-frequency image signals.

Abstract: The present invention relates to the encoding and decoding respectively of serial data, using block codes. Encoding of a serial bit stream of input data in groups of N bits, so-called words (O), to serial output data in groups of 2N bits, so-called code words (KO), is preferably carried out by a logic circuit in a manner such that N of the 2N bits in the code words (KO) are comprised of the N bits input data, unchanged or inverted, and remaining bits in the code words (KO) are determined so that, seen statistically, the code words (KO) will include approximately as many zeros as ones, such that each code word (KO) will be unique for each word (O), and such that at least one of the code words (KO) will remain unique even in bit stream shifting processes. Decoding includes further encoding in a similar logic circuit and comparison of the incoming code words with the code words encoded in the logic circuit, in a predetermined manner.

Abstract: In a digital demodulation apparatus, a first signal generating circuit generates a first clock signal and a first frame signal which are always in an active state, and a second signal generating circuit generates a second clock signal and a second frame signal which are intermittently in an active state. An analog-to-digital converter converts an intermediate analog signal into a digital signal. A smoothing digital filter performs a smoothing operation upon the digital signal in synchronization with the first clock signal and the first frame signal to general parallel data. A data phase synchronization circuit converts the parallel data into serial data in synchronization with the second clock signal and the second frame signal. A digital signal processing circuit performs a signal processing operation upon the serial data in synchronization with the second clock signal and the second frame signal.

Abstract: A serial to parallel port signal converter for interconnection between a hosts utilizing Uniform Serial Bus communications protocols and a peripheral device uses IEEE 1284 complaint communications protocol. The signal converter appears to the host as a fully compliant bi-directional USB device, and to the peripheral device as a fully compliant IEEE 1284 host.

Abstract: A digital concatenator, the operation of which is triggered by the sequential arrival of a series of n-bit bytes thereto, accepts such sequential n-bit bytes and, by directing those n-bit bytes into sequentially identified n-bit channels, concatenates those n-bit bytes into (n×m)-sized words, where m is a pre-selected integral number of said n-bit bytes that are desired to be concatenated within an (n×m)-sized output buffer into a resultant sequence of (n×m)-sized words. The sequential identification of those n-bit bytes is brought about by a cyclical counter incorporated within a data enumerator that counts off the arrival of each n-bit byte and appends a corresponding position bit or byte to each one thereof. Each successive reading of the output of the concatenator is triggered by the arrival at that output buffer through an mth channel of an mth n-bit byte. The concatenator similarly operates on single bits so as to serve as a serial to parallel converter of arbitrarily selectable size.

Abstract: A process for initializing a serial link between two integrated circuits comprises an initialized input-output port associated with each integrated circuit connected between a parallel bus and a serial link. Each port uses two clocks with different frequencies, a first higher-frequency clock for the serial link, called a transmitting clock, and a second lower-frequency clock for the signals arriving from the parallel bus, called a system clock. The process comprises the following steps: reinitializing the port with isolation of the receiving clock logic; reinitializing the transmitting clock logic; resetting the serial link between two ports; and initializing a two-way serial link by a looped process, either automatic or dependent on a microprocessor.

Abstract: A control voltage is supplied from a phase locked loop (PLL), which includes a phase detector and a voltage controlled oscillator (VCO), to a delay circuit. The VCO is made up of a plurality of inverters connected together in a ring. The control voltage is also supplied to each of these inverters so as to control an oscillation frequency of the VCO. The control voltage is defined based on a phase difference between a reference clock signal and an oscillation clock signal. The delay circuit is made up of a plurality of inverters connected in series to each other. A delay caused by each of these inverters is controlled with the same voltage as the control voltage. A serial signal is input to an initial-stage one of the inverters. A latch circuit latches the output signals of the respective inverters of the delay circuit in response to a latch clock signal, which has been generated by dividing the frequency of the reference clock signal. And based on a result of latching, a parallel signal is output.

Abstract: The present invention is directed to a method and apparatus for converting between serial bus cycles and parallel port commands. A serial bus processor processes a serial bus transaction which is represented by the serial bus cycles and is responsive to the parallel port commands. A state machine circuit is coupled to the serial bus processor to provide a plurality of states corresponding to the serial bus transaction. The state machine circuit transitions from one of the states to any one of the states in response to a change condition asserted by a state signal.

Abstract: A differential multiplexer has first and second differential input pairs for receiving first and second input signals, a transistor for making active the first differential input pair by using as a control signal a first clock of a pair of differential first and second clocks, another transistor for making active the second differential input pair by using as a control signal the second clock, a first output terminal for outputting the first input signal if the first clock is larger than the second clock and outputting the second input signal if the second clock is larger than the first clock, and a second output terminal for outputting a paired differential signal of the signal output from the first output terminal.

Abstract: In a parallel-to parallel converter for converting an “m”-bit parallel signal into an “n”-bit parallel signal, a common multiple register has a bit width which is a common multiple of “m” and “n”. An input selector is connected to an input of the common multiple register, and writes the “m”-bit parallel signal into the common multiple register at a predetermined frequency. An output selector is connected to an output o f the common multiple register, and reads the “n”-bit parallel signal from the common multiple register at a frequency equal to m/n times the predetermined frequency.

Abstract: The present invention provides a serial-parallel conversion apparatus comprises N conversion circuits, each having: a separator for dividing an input data from an upper node according to a clock signal from the upper node, into a plurality of data corresponding to a plurality of terminals; and a clock generator that divides by two the input clock signal and outputs a resultant clock as a clock signal to a lower node. These N conversion circuits are connected in a tree structure. Thus, each separator divides a data according to a clock supplied from an immediate upper node, and each clock generator divides by two the input clock signal. The resultant clock signal serves as a clock signal in a conversion circuit of a lower node. Accordingly, it is possible to minimize the signal line length for transmitting the clock signal. This enables to obtain an optimal clock signal timing.

Abstract: Disclosed is a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into n parallel signals. The device uses a scheme derived from that of a static memory cell as a sample-and-hold unit and amplifier. The device continues to perform well when the differential signal comprises noise in common mode.

Abstract: Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis.

Abstract: The invention relates to fast serial-parallel and parallel-serial converters, and in them included frequency dividers. The serial-parallel converter comprises a shift register, an output register and a frequency divider. The parallel-serial converter comprises a register and a frequency divider. All registers and frequency dividers comprise clock inputs, that each is connected to some incoming clock signal. According to the invention, the frequency divider comprises at least two circuits with the function of AND-gates with clocked memory circuits. Each circuit comprises a clock input, a first AND-input, a second AND-input, and at least one output that outputs the value of the logical AND-function of the two AND-inputs. The first AND-inputs are connected to each other and to an inverted signal from one of the outputs. The second AND-inputs except on the first circuit are connected to the output of the preceding circuit. Finally a frequency divided clock signal may be taken out from one of the outputs.

Abstract: A clock synchronizer may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the bit rate of the asynchronous data signal, and the other programmed with a phase-delay value so that it generates a sample clock signal at a phase delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first shift register configured to shift a data word in serially and output the data word in parallel and a second shift register configured to track when the data word had been completely shifted into the first shift register and to cause the data word to be outputted in parallel from the first shift register so that a new word may be shifted into the first shift register.

Abstract: A parallel to serial conversion circuit is disclosed. The circuit is used for converting parallel bits representing a plurality of words into serial bits. The circuit consists of storing means which comprises a plurality of word locations for temporarily storing the plurality of words at a parallel clock rate, and serialization means connected to the storing means for converting the parallel bits into serial bits at a serial clock rate. Each of the plurality of word locations is organized as a plurality of cells for storing each, one bit. Moreover the serialization means comprises parallel pointing means connected to the storing means for pointing to the plurality of words locations synchronously to the parallel clock, and serial pointing means also connected to the storing means for pointing to the plurality of cells synchronously to the serial clock.

Abstract: A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking by incorporating logic within the interface itself to control data flow. A row/column count state machine in the interface accumulates serial clock pulses from the microcontroller and controls the latching of parallel output data. A read/write state machine accumulates addresses and controls the read/write operation in response to a command sent by the microcontroller in the serial data stream. The read/write state machine accumulates addresses in response to an interface clock derived from the serial clock from the microcontroller.

Abstract: A serial/parallel selective converter is provided that selectively receives and outputs data by using a plurality of serial input/output switching latches and a plurality of parallel input/output switching latches. The serial/parallel selective converter can further include three sets of transmission gates respectively coupling the plurality of serial input/output switching latches and the plurality of parallel input/output switching latches. The serial/parallel selective converter can output a serial input data signal as a parallel data signal and can also output a parallel input data signal as a serial data signal based on a serial/parallel selection control signal.

Abstract: In a signal processing circuit capable of handling different signal rates, an STS-3 signal input as 78 M.times.2 parallel signals is converted by a serial-to-parallel converter into 19 M.times.8 parallel signals, thus making the number of signal lines equal to that of an STS-12 signal input as 78 M.times.8 parallel signals. Depending on whether the mode is STS-12 mode or STS-3 mode, a first selector selects the 78 M.times.8 parallel signals of STS-12 or the 19 M.times.8 parallel signals of STS-3, and supplies the selected signals to a signal processor. Depending on whether the mode is STS-12 mode or STS-3 mode, a second selector selects a 78-M clock or a 19-M clock and supplies the selected clock to the signal processor.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: A digital delay line, comprising adjustable digital delay elements, receives and buffers an incoming bit stream by repeatedly delaying bits of the bit stream for a specific period of time. The outputs of selected adjustable digital delay elements are tapped for providing a specific pattern of bits in parallel to a function block. The function block operates on the parallel bits on-the-fly to detect and substitute bits for decoding, descrambling, decrypting, or performing any other such function.

Abstract: A parallel port to serial digital fiber link converter has a first high speed communications port connected to a first shift register for converting a serial digital signal, received from a first digital device via a first high speed communications link, to a parallel signal and transferring it to a personal computer via a parallel port. A second shift register and second high speed communications port are used for converting parallel data, retrieved via the parallel port of the personal computer, into serial digital data and sending it to a second digital device via a second high speed communications link for storage or playback.

Abstract: A method and system for parallel encoding of data for bit-stuffed HDLC compatible transmission is presented. The method analyses a byte in parallel with four recirculated previously encoded bits during each clock cycle. The recirculated bits allow for correct analysis of the presence of a fifth consecutive one within the byte including the first four bits thereof. The encoded byte is provided to a FIFO and, when 8 bits are stored therein, the eight most significant bits are extracted from the FIFO for transmission via a digital or analogue network. The FIFO provides two bytes without receiving an intervening encoded data byte when a risk of an overflow exists.

Abstract: A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A serial to parallel port signal converter for interconnection between a hosts utilizing Uniform Serial Bus communications protocols and a peripheral device uses IEEE 1284 complaint communications protocol. The signal converter appears to the host as a fully compliant bi-directional USB device, and to the peripheral device as a fully compliant IEEE 1284 host.

Abstract: A digital data transmission system used to transfer data between devices implements a serial bus to interconnect the devices. The system includes a delay line serializer having a bit serializer and a detection delay line to convert parallel data into serial data for transmission on the serial data bus. An optional clock multiplier coupled to a local clock increases the rate in which data is transferred onto the serial bus.

Abstract: The invention provides a serial to parallel conversion apparatus which can perform desired serial to parallel conversion processing at a high speed while it has a simple and small-scale circuit configuration.

Abstract: An electronic circuit can eliminate bubble errors by means of transferring a thermal code from spatial domain to time domain, and then from the time domain to the spatial domain. In accordance with the present invention, a rotator and a shift register are used to implement the circuit. The rotator is utilized to convert the data bits of the thermal code available in parallel into a serial thermal code. In other words, the data bits can be read serially at the output of the rotator. However, the serial thermal code is applied to the shift register for removing the bubble errors in response to the logic state in the serial thermal code and converting the serial thermal code into a corrected thermal code in parallel form. Accordingly, the electronic circuit for removing bubble errors according to the present can eliminate bubble errors occurring in the thermal code even if the bubbles occur randomly.

Abstract: The invention discloses a method and system for synchronizing external data to an internal timing signal. External data is received in conjunction with a clock input. The clock input has first set of values and a second set of values. The clock input is compared to an internal timing signal having a frequency that is a multiple of the clock input. The internal timing signal is shifted by adjusting the count of a counter if the clock input transitions from the first set of values to the second set of values within a predetermined range of the internal timing signal.

Abstract: In a data multiplexing/demultiplexing apparatus including a serial-to-parallel converter, a microprocessor and a memory, a data shift register inputs data from the memory by way of the microprocessor, a correction register stores a shift correction amount on a transmission path of the data shift register. A framing rule register stores a framing rule determined by the microprocessor, a counter, carries out a counting operation in accordance with the framing rule to an address information signal. A look-up table ROM outputs a selector selection signal in accordance with the address information signal, and a data selector distributes output data of the data shift register among a plurality of shift registers in accordance with the selector selection signal. The microprocessor analyzes data separated by the plurality of shift registers, performs a synchronism detecting operation and a protocol determining operation, and determines the framing rule.

Abstract: A parallel-to-serial converter based on the principle of current evaluation that, in addition having signal paths, has a reference path with intentionally generated, poorer running time properties than all signal paths, and a conversion and a deactivation of a current source in an input hold element already occurring as soon as the reference path supplies a ready message. The advantages of this converter are particularly high signal processing speed and low dissipated power, but also low line crosstalk and small chip area. A further critical advantage is that the converter is adaptive in view of technology parameters, temperature and supply voltage, i.e. these quantities have nearly no influence on the functionability of the parallel-to-serial converter.

Abstract: A system and method for converting data between a multi-bit time division multiplexed (TDM) bus and a faster single-bit TDM bus, wherein each TDM bus communicates data by means of frames, each frame comprising a fixed number of slots and each slot comprising a fixed number of bits, the system comprising digital circuitry for establishing a clock rate R.sub.SB for the faster single-bit TDM bus that has the following relationship to a clock rate R.sub.MB for the multi-bit TDM bus: R.sub.SB =R.sub.MB *((slots per frame)*(bits per slot)+1).div.(slots per frame).

Abstract: Apparatus and method are provided for enabling unimpeded, clock-to-clock communication between different classes of equipment including converting without queuing of data parallel bytes of digital data having a given number of binary bits to parallel bytes having a different (greater or smaller) number of bits.

Abstract: A signal processing apparatus transforms N-bit coded data into M-bit coded data, where M is larger than N. The N-bit coded data is obtained by converting an analog signal into a digital signal in the resolution of 1/2.sup.N. First cyclic data of K number sequential N-bit coded data of a sampling period Ts/K is generated in response to input N-bit coded data of a sampling period Ts, where K is a natural number of two or more. The first cyclic data is processed to output second cyclic data of K number sequential M-bit coded data of the sampling period Ts/K.

Abstract: A circuit to implement a multi-channel parallel to serial conversion and a multi-channel serial to parallel conversion in one minimal RAM Matrix. The number of RAM cells (bits) needed is equivalent to the number of Flip-Flops used in a standard shift register and holding register implementation.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.