Abstract: A method is disclosed for extracting data words from a binary serial bit stream having a fixed bit rate and consisting of fixed length words of n bits each, where n is an integer, each word is preceded by a start bit and followed by one or more stop bits. First a predetermined identifiable transition is detected in said bit stream preceding each data word. A clock signal (DCLK) consisting of n clock pulses is generated in response to each detection of the predetermined transition in coincidence with the bits the data word following the predetermined transition. A data ready signal (DR) is generated after the passage of n bits to delineate the word boundary, and the data words are extracted from the bit stream using the thus generated clock pulses and the data ready signal.

Abstract: A circuit for communicating between structures of an integrated circuit through a metallized layer is provided in which parallel data bits are bundled into serial data packages, serialized and sent from a structure to the metallized layer. A destination structure receives the serial data package from the metallized layer and deserializes the package back into a parallel set of data bits. The metallized layer may extend over a significant portion of a substrate of a chip as a metallized data plane or metallized clock plane. Moreover, the metallized layer may be coupled to a pin to allow communications between structures of separate integrated circuits.

Abstract: A serial-to-parallel data conversion and transmission system for converting incoming serial data sent by another system. The incoming data contains a data portion and identifying information and is converted into parallel data in response to a chip select signal. The apparatus is operable to store the data portion of the incoming data in a first register array, which is coupled to a multiple of receiving devices; and to store the identifying information in a second register array, which is coupled to a decoder. The decoder reads the identifying information from the second register array and decodes the information to determine which receiving device(s) should receive the data portion. The data portion is then transmitted from the first register array to the selected receiving device(s). The data portion is converted from serial data to parallel data upon passing through the first register array, and thus parallel data is transmitted to the selected receiving device(s).

Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.

Abstract: Bit error rate in holographic storage/reconstruction is reduced by 2-dimensionally dispersing symbols constituting codewords so that no two codeword-common symbols occupy a single row or column on the SLM display.

Abstract: A synchronization control unit for synchronizing serial-to-parallel (S/P) converters operating in parallel, or parallel-to-serial (P/S) converters operating in parallel. More specifically, first and serial-to-parallel (S/P) converters produce respectively corresponding first and second clock signals and operate in parallel. The first and second clock signals are in synchronization, and a synchronization failure occurs when the first and second clock signals fall out of synchronization. When a synchronization failure occurs, the synchronization control unit resets one of the first and second clock signals so that synchronization between the first and second clock signals is restored within a definite time period. Moreover, the synchronization control unit can perform the same operation with parallel-to-serial (P/S) converters, instead of with S/P converters.

Abstract: A particular encoding scheme for encoding four bit values into six-bit symbols selects from the table below the six-bit symbol corresponding to a particular four bit value:______________________________________ Binary 3 of 6 code value symbol lsb msb lsb msb p q r s t u y- v w z- ______________________________________ 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 ______________________________________

Abstract: A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers.

Abstract: The invention provides a parallel to serial data converter wherein the frequency of a basic clock pulse signal to be applied for driving can be reduced to one half with respect to a same data rate and consequently the operation speed required for a circuit in a preceding stage can be reduced, and a bad influence of noise such as, for example, jitters of serial data is eliminated. In the parallel to serial data converter, a clock pulse signal having a frequency f/2 Hz equal to one half the data rate of parallel data which is f bps is used as a basic clock pulse signal, and an inverted pulse signal is produced from the basic clock pulse signal. Then, a rising or falling edge of each pulse of the basic clock pulse signal and a rising or falling edge of each pulse of the inverted pulse signal are detected, and a byte clock pulse signal having a frequency equal to that of the parallel data is produced by logical ORing of such two edge detection outputs and is supplied to a multiplexer.

Abstract: Various innovative circuit techniques that make possible a single chip, cost effective implementation of a CCD signal digitizing circuit are disclosed. Among the various features of the single chip digitizing circuit is the use of a single clock to sample the CCD signal and to digitize the analog signal. By providing a tight control over the minimum required settling time delay at the input of the analog to digital converter (ADC), the speed of the circuit is optimized. Other features include support for various modes of CCD operations, reference voltage feedback from ADC to sampling circuit to compensate for offset voltage, dual register serial input/output circuit, and multiplexed ADC input.

Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.

Abstract: The present invention relates to a circuit for removing energy dispersal in the transmission of a data packet, the circuit including a polynomial counter for supplying, at the transmission rate of the bits of the packet, correction bits to be respectively X-ORed with the bits of the packet. The correction bits are supplied to a series-to-parallel converter having its output combined with the successive packet parallel transmitted bits of the packet.

Abstract: A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock lines typically found in other converters. The simplified circuit design also has the advantage of requiring minimal semiconductor layout area and reduced power requirements. One embodiment includes a buffer, a first data delay line, coupled to receive serial data from the buffer, and a phase lock loop (PLL), coupled to receive serial data from the buffer. A second data delay line is configured as a voltage controlled oscillator (VCO) within the PLL. The PLL locks onto the incoming serial data signal and provides a control signal back to the first data delay line to ensure it is storing serial data bits as they arrive.

Abstract: A serial/parallel converter includes a shift register arrangement (12', 12" to 12.sup.n) and an output register arrangement (13', 13" to 13.sup.n), each of which includes n storage devices (12', 12" to 12.sup.n ; 13', 13" to 13.sup.n). Each of the storage devices (13', 13" to 13.sup.n) of at least the output register arrangement includes two data inputs (DP, DS), a selection input (S) for selecting a data input, a clock input (CLK) as well as a data output (Q). The individual clock inputs (CLK) of the storage devices (13', 13" to 13.sup.n) receive a serial data signal and the selection inputs (S) receive a frequency-divided clock signal. Second data inputs (DS) of the storage devices (13', 13" to 13.sup.n) are connected to the data outputs (Q) of the shift register arrangement (12', 12" to 12.sup.n), the first data input (DP) of said storage devices being connected to the own data output (Q). The data signal can be derived in parallel from the data outputs (Q) of the storage devices (13', 13" to 13.sup.n).

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: In a method of transmitting multiple serial signals, parallel signals are converted into serial signals by a plural number of parallel-to-serial converters contained in a transmitter, serial signals are converted into parallel signals by a plural number of serial-to-parallel converters contained in a receiver, and multiple serial signals are transmitted between the transmitter and the receiver through a channel. In the method, for data transmission, said plural number of parallel-to-serial converters and said plural number of serial-to-parallel converters are connected in series, and the format of the serial signals on the channel, the format for the parallel-to-serial converters located preceding to the channel, and the format for the serial-to-parallel converters located succeeding to the channel are the same formats. In this case, these formats may be of the start-stop synchronization type.

Abstract: A variable length decoder which is particularly suitable for decoding digital video data for HDTV. The variable length decoder operates to decode in parallel qualifying code words, such as payload data in an MPEG data stream, during a single clock cycle, and operates to decode singular non-qualifying code words, such as setup data in the MPEG data stream, during a single clock cycle. Since the payload data constitutes approximately 95% of the MPEG data stream, the throughput of the VLD of the present invention is significantly higher than that of the presently available VLDs, at a clock rate that is significantly lower than that of the presently available VLDs.

Abstract: A serial data stream is recovered using a local clock, which is asynchronous to the clock used to transmit the serial data. The incoming serial data stream is phase shifted or delayed by a digital phase-locked loop so that it may be reliably sampled by the local clock. The DPLL samples the serial data stream and captures data on both the rising and falling edges of the local clock employing three edge detectors. This partitions the data stream into two bit samples, which the DPLL presents to a deserializer. The deserializer converts the serial data to parallel data and assembles the received data back into data bytes. The deserializer also generates a received byte clock used for presenting the parallel data to, for example, the ESCON channel logic.

Abstract: A data conversion circuit has an input terminal for receiving serial data as time-divided multiple signals, a plurality of sample-and-hold circuits each connected to the input terminal, and output terminals each connected to an associated one of these sample-and-hold circuits to output the received signals as parallel data.

Abstract: An adapter for performing bi-directional data transfers between a SCSI bus, which transfers data using a parallel format, and a serial transfer medium, which transfers data using a serial format and being connected to a serial device. The adapter bi-directionally transfers SCSI data between itself and the SCSI bus. In addition, the adapter bi-directionally converts between SCSI formatted data and serially formatted data. Furthermore, the adapter bi-directionally transfers serially formatted data between itself and the serial transfer medium.

Abstract: The display driving device of the invention has a display driver for driving a display device by using image data to perform a display. The display driving device includes: a time-series data generating section for arranging division data obtained by dividing the image data in a time-series manner, to generate time-series data; and transmission lines provided between the time-series data generating section and the display driver through which the time-series data is transmitted from the time-series data generating section. When the display area of the display device is divided into a plurality of display areas, a plurality of display drivers are provided.

Abstract: A communication apparatus comprising: a spatial communication circuit having a transmission part and a reception part; and a detection part for detecting the separate positional state from a communication partner apparatus. The communication method by the spatial communication circuit is switched according to the detection result of the detection part.

Abstract: A digital audio signal mixing circuit for mixing two digital audio signals which have sampling frequencies different from each other and for generating the mixed data of an analog format, includes: a first serial-parallel converting unit for converting first serial digital audio data into first parallel data in synchronism with a first bit clock; a second serial-parallel converting unit for converting second serial digital audio data into second parallel data in synchronism with a second bit clock; a first and a second latching unit for converting continually varying second parallel data into parallel data stabilized in one channel area, for respectively separating the converted parallel data into third data of a left channel and fourth data of a right channel, and for temporarily storing the separated data; a first selecting unit for selectively outputting one of the third and fourth data as fifth data in response to a signal representing whether the first parallel data is data of the left channel or data of

Abstract: A multiplexer includes an n-th stage as a final output stage (n=integer, 2.ltoreq.n); j stages (j=integer, 1.ltoreq.j.ltoreq.n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m.sup.n-j-1 (m=integer, 2.ltoreq.m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time.

Abstract: A serial-to-parallel (S/P) converter includes a tree of S/P cells. The tree level 1 includes one cell with two or more latches. The inputs of the latches are connected to the serial data input of the converter. The output of each latch is connected to the input of another multi-latch cell of level 2. The output of each latch of level 2 is connected to the input of a cell of level 3, and so on. In each cell, each latch latches respective bits from the cell input. Different latches latch different bits so that the cell converts the serial data on the cell input to parallel data on the outputs of the cell's latches. The serial data stream on the output of a latch of a tree level other than the highest level is converted to parallel data by higher-level cells. Latches of higher levels are clocked at lower frequencies than latches of lower levels. In some embodiments, latches of levels 3 and higher can be made slower than latches of level 1 without reducing the converter's input frequency.

Abstract: A 1:N divider 40 divides an input high rate data signal into N (N being 2 or greater integer) division data signals. Data transmission rate converters 70.sub.1 -70.sub.N for converting the transmission rate of each of the N division data signals. The respective N division data signals are transmitted through N transmission lines 30.sub.1 -30.sub.n. A multiplier 50 multiplies the transmitted N division data signals into a single high rate data signal.

Abstract: The present invention relates to an apparatus for modulating input data by encoding the data to a run length limited (RLL) code data satisfying the (d,k,m,n) condition and decoding the modulated data, in which d is a minimum run length, k is a maximum run length, m is the bit number of input code data, n is the bit number of transmission code data, and the encoding and decoding apparatus according to the present invention comprises a look-up table (LUT) for encoding input parallel m-bit code data to r-bit code data in which r is not less than m and less than n, a post-encoder for encoding the encoded r-bit data to an n-bit transmission code data, a pre-decoder for decoding the input n-bit transmission code data to the r-bit code data according to the minimum run length condition, and a LUT for decoding the decoded r-bit code data to the original m-bit code data, by which the transmission code length is shortened according to the minimum run length condition so that the memory size required for encoding and de

Abstract: A multi-code-book variable length decoder for decoding an input bit stream containing a plurality of variable length code words includes a plurality of individual variable length decoders and a controller. Each of the individual variable length decoders receives the input bit stream and decodes the input bit stream according to a different respective code book. The controller receives the input bit stream and, for each successive code word contained in the input bit stream, selects a correct one of the plurality of individual variable length decoders for decoding that code word.

Abstract: A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.

Abstract: A serial bit stream is first connected to two parallel bit streams using two half rate clocks. The 2-way parallel bit stream is then converted into a five-way parallel bit stream. Therefore, the clock rate of the five-way parallel bit stream is 1/5 of the clock rate of the input bit stream. The input bit stream contains a unique bit sequence or comma to identify the byte and word boundaries. The comma is detected in five way bit stream. Since the clock rate at the five-way bit stream is five times slower than at the input bit stream, substantially slower circuits which operate at lower power can be used to detect the byte boundaries. Therefore, substantially less expensive circuits can be used to adjust the byte boundaries. Quarter rate clocks in combination with two port latches can provide the same bit rate as half-rate clocks, but reduce the lifetime of CMOS circuits substantially less.

Abstract: A symbol to byte converter converts multilevel symbols into data bytes. The bits of each M level symbol are written to a parallel register and read out serially to a serial register under control of an 8 times symbol clock. Successive groups of eight bits are read out in parallel from the parallel register with a byte clock to form the data bytes.

Abstract: A counter circuit provides select signals SEL0-SEL3 of a cycle 4Tc sequentially attaining a high level for every 1/4 cycle Tc. A 4-input selector circuit receives data signals I0-I3 of a cycle 4Tc to sequentially output the same for every 1/4 period of Tc in response to a high level of select signals SEL0-SEL3. A flipflop circuit fetches and outputs an output of the selector circuit in synchronization with a clock signal C0. The number of hardware components is reduced in comparison with the conventional case where a select signal generation circuit generates only one select signal SEL, and where a plurality of flipflop circuits and 2-input selector circuits carry out a select and shifting operation of parallel data signals I0-I3.

Abstract: A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.

Abstract: A bit stream unpacking circuit (10) parses data fields from a serial bitstream as an initial step in decompression. The protocol of the incoming packed data stream is stored in a control ROM (24). As each packed data field arrives, the control ROM provides size and condition instructions (18) to parse out the fields from the serial data stream and store the fields in data storage (14) for later retrieval. The size instruction determines the length of the field in the incoming data. A counter (26) counts clock signals of the incoming serial bitstream and matches the count with the size instruction to determine when a data field has arrived. The condition instruction determines the next address in the control ROM based on the incoming bitstream. Once the incoming message has been parse out and stored, the individual data field may be read directly from the data storage for decompression.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: A transmitter test circuit (40) for serially transmitting multiple packets of digitized analog signals comprises translation circuitry in the form of analog-to-digital interface (142) that translates an analog signal into a digital representation of the analog signal. The digital representations comprise a plurality of binary bit positions. A shift register (200) receives and outputs the digital representations. The load/shift control bus operates between the shift register or PSA/sample register (200) and a serializer circuit (204) for loading the digital representations into the shift register (200). Output circuitry shifts the digital representations out of the shift register to an intermediate integrated circuit (43) and on to a test bus controller (44). Test bus controller (44) includes input/output circuitry (61), a memory (59), a processor (63) registers (45 and 47) and a test port controller (71). Test bus controller (44) may output to a plurality of external test port devices.

Abstract: A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.

Abstract: A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written.

Abstract: The invention realizes a serial to parallel conversion circuit which operates at a high speed with low power dissipation. High speed serial data are input and re-timed with a high speed clock input by a first high speed flip-flop. Differential divide-by-eight clock signals are produced by dividing the high speed differential clock input by two using a second high speed flip-flop and are supplied to ninth through eleventh flip-flops, by which divide-by-eight shift clock signals and another series of divide-by-eight shift clocks leading the divide-by-two clocks by a half-period are produced. The output of the first high speed flip-flop is input to a shift register comprising first through fourth flip-flops, and is shifted with the positive phase divide-by-two clock signals. The output of the shift register is then re-timed with the other divide-by-eight shift clock signals described above by twelfth through fifteenth flip-flops.

Abstract: A serial-to-parallel converter comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of serial-to-parallel converter cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be read when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the serial-to-parallel converter.

Abstract: A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.

Abstract: The present invention relates to a serial/parallel converter circuit with uncertainty removing function. The object of the invention is to offer that signals can be instantaneously rearranged in the same data arrangement as that of original parallel signals prior to a parallel to serial conversion.

Abstract: A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer.The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.

Abstract: A method of converting a parallel, time-division-multiplexed data stream into individual serial data streams wherein the individual parallel data words are written in parallel into and read serially from one of a plurality of buffers, wherein each parallel data word is presented simultaneously to the parallel inputs of all buffers, and that for each data word, the inputs of only one buffer are enabled. Also a converter for converting two or more individual serial data streams into a single parallel, time-division-multiplexed data stream, having one buffer per serial data stream which can be written into serially and read from in parallel, wherein all buffers are connected in parallel at the output end, that the outputs of each buffer can be enabled, and that a decoding device is provided on the parallel side which makes it possible to enable the outputs of one buffer at a time.

Abstract: A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

Abstract: An amplitude modulation system. An input analog signal indicating audio, etc., is converted into a digital form and the low-order bits of the resultant digital signal are converted into analog form. The resultant analog signal is used to control a gain of an analog controlled amplifier. On the other hand, a plurality of digitally controlled amplifiers are selectively turned on/off in response to the value of the high-order bits of the digital signal. Carrier amplified by the analog controlled amplifier are combined with carriers amplified by the plurality of digitally controlled amplifiers. Comparatively rough amplitude constituents are provided by outputs of the plurality of digitally controlled amplifiers and comparatively fine amplitude constituents are provided by output of the analog controlled amplifier.

Abstract: An integrated circuit and its using method. The integrated circuit having a serial-parallel converter and a driver unit is further provided with a setting circuit which is responsive to a selection signal value for setting the number of shift stages of the serial-parallel converter. When serial data consisting of a number of bits exceeding the setup stage count is input, the serial-parallel converter outputs data as overflow serial data in order starting at the first input bit of the serial data. A plurality of the integrated circuits are cascaded so that overflow serial data output from the integrated circuit at a preceding stage is supplied to the integrated circuit at the following stage as serial data to be converted into parallel data. The same selection signal value is supplied to each of the integrated circuits.

Abstract: A converting method and circuit for converting horizontal M-bit data and vertical N-bit data into vertical M-bit data and horizontal N-bit data. A square matrix of M or N whichever the larger is considered, and a part of data are transposed with the diagonal axis as an axis of symmetry. The circuit may be constituted by flip-flops less than the number M.times.M (N.times.N) and selectors less than the same number.

Abstract: A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with a successive approximation registers signal (SARS). Once the internal data conversion begins, the chip select signal may change to any signal state without interrupting the conversion process. Serial interface data output and SARS lines are tri-stated during conversion, while the chip select signal is high. This allows data input, data output, and SARS lines to serve other purposes during conversion. If chip select signal is high at the falling edge of SARS, converted data DO bits are then provided to an internal output register. However, DO data are not immediately routed to the output. Clocking of the output data does not resume until at the first transition to low of chip select signal after the falling edge of SARS.