Abstract: A parallel to sequential message converter including a pair of signal terminals for receiving a first input signal having a duration of a first time period and a second input signal having a duration of a second time period which is less than the first time period, and wherein the second input signal is received concurrently with a portion of the first input signal so that a time overlap in signals exists. The first input signal is delayed at the onset of the second input signal for a period substantially equal to the time period of the second input signal. The second input signal is inserted into the signal stream at the start thereof and the delayed first input signal is thereafter reinserted so as to provide a sequential output of the first and the second input signals at an output terminal without a loss of any portion of the first input signal.

Abstract: The present invention relates to the encoding and decoding. respectively, of serial data, using block codes. Encoding of a serial bit stream of input data in groups of N bits, so-called words (O), to serial output data in groups of 2N bits, so-called code words (KO), is preferably carried out by a logic circuit in a manner such that N of the 2N bits in the code words (KO) are comprised of the N bits input data, unchanged or inverted, and remaining bits in the code words (KO) are determined so that, seen statistically, the code words (KO) will include approximately as many zeros as ones, such that each code word (KO) will be unique for each word (O), and such that at least one of the code words (KO) will remain unique even in bit stream shifting processes. Decoding includes further encoding in a similar logic circuit and comparison of the incoming code words with the code words encoded in the logic circuit, in a predetermined manner.

Abstract: The present invention improves the drawback of requiring more clock signals in conventional high-frequency serial-to-parallel conversions that often use multi-phase clock circuits. The needed number of phase clocks is the bit width of the parallel data. In addition to effectively reduce the number of required clocks, the present invention can further solve the setup time problem associated with the switching one of two parallel data receivers as the parallel data output. A pre-register is employed in the converter of the present invention. Since this pre-register does not need switch control, it does not have the setup time problem during parallel data switching.

Abstract: A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal.

Abstract: Described is a scalable interface including a plurality of 2-bit transmission channels. An encoder partitions a digital bit stream into 3 bits which are coded into 4 bits with each pair of bits in each 4 bit pattern transmitted via back-to-back clock cycles on separate ones of the channels.

Abstract: A serial-to-parallel converter (130) samples serial data DA1 comprising a first data string, which includes one or more unit data strings each including a predetermined number of bits (00XXX . . . XXX) and which is input after a synchronization period, in accordance with a clock signal CL1 which has been used to generate the serial data by converting original parallel data into serial form, thereby converting the serial data to parallel data from one unit data string to another. Signal generation means (140) generates a synchronization signal corresponding to a synchronization period in accordance with the serial data DA1 and the clock signal CL1. The serial data includes a second data string (1100 . . . 000) which appears in each synchronization period and which includes one or more unit data strings having a predetermined bit pattern. If the signal generation means (140) detects a unit data string (11000 . . . 000) in the second data string, it generates a synchronization signal.

Abstract: In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

Abstract: A system and method are used to convert a parallel datastream to a serial datastream. N number of parallel bits are input to n number of selection devices. One of the n number of selection devices is selected as an active selection device. The active selection device is directly coupled to a corresponding current source. The (n−1) inactive selection devices are coupled to a current steering device. The current steering device is coupled to the corresponding (n−1) inactive selection devices. The current steering devices allow taking over by input data bit or latch on the previous bit if there is no input. The parallel bit is converted to a bit in the serial datastream by generating a voltage representative of a value of the serial bit utilizing a combined current from the n current sources.

Abstract: The present invention relates to a monitor device for a control system having a serial-parallel converter for receiving inputs of serial signals transmitted from a unit control section via serial lines and converting them into parallel signals, a synchronization signal-receiving section for receiving inputs of predetermined signals transmitted from the unit control section via the serial lines and specifying addresses at which the parallel signals are stored, based on states of the predetermined signals, a data buffer for storing at least the parallel signals at the addresses specified by the synchronization signal-receiving section, and a CPU for providing control such that predetermined displays are provided on a CRT based on the stored signals.

Abstract: A system normally converts a parallel data word to a single serial data stream to use a high speed serial link. The parallel data word is partitioned into N sub-sets or nibbles and each nibble is then serialized and transmitted over N serial links using high speed differential drivers. Each of the N serialized nibbles are received in a differential receiver. The serialized nibbles are then coverted back into N parallel nibbles and the N parallel nibbles are then assembled back to the original parallel data word. To increase reliability, the received data is coupled to a tapped delay element having M stages of delay. A training sequence and algorithm are used to determine which of the taps of the delay element are a desired delay distance away from data transitions. These taps are then used to sample the incoming signals to reconstruct the parallel data word.

Abstract: A system and method are used to convert a parallel datastream to a serial datastream. N number of parallel bits are input to n number of selection devices. One of the n number of selection devices is selected as an active selection device. The active selection device is directly coupled to a corresponding current source. The (n−1) inactive selection devices are coupled to a current steering device. The current steering device is coupled to the corresponding (n−1) inactive selection devices. The current steering devices allow taking over by input data bit or latch on the previous bit if there is no input. The parallel bit is converted to a bit in the serial datastream by generating a voltage representative of a value of the serial bit utilizing a combined current from the n current sources.

Abstract: A center phase decision circuit for deciding a center phase of a data signal, in which, in case the data signal is subjected to disturbance in the signal waveform, the signal is corrected for the disturbance to re-establish normal communication.

Abstract: A method for serializing bits without introducing glitches (i.e., spurious signals) into the serialized data stream is disclosed. Furthermore, the embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, the illustrative embodiment of the present invention requires timing signals with a frequency equal to the rate at which words are loaded into the serializer. The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second umanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: The device and method compensate for propagation differences between n serial data streams each transmitted over parallel optical lines. Data that can be transmitted via the n serial data streams are configured as m-bit words. The device has n regeneration devices in which data of the data stream can be regenerated. A data output and a clock pulse output of the regeneration devices are connected to a propagation time control device so that the regenerated data and the regenerated clock pulse can be transmitted to a data input or to a clock pulse input of the propagation time control devices. The propagation time control devices each have a demultiplexer for dividing the regenerated data as well as the regenerated clock pulses with a ratio of 1:(x·m), and each have an alignment device for distributing the divided regenerated data on x·m parallel data outputs of the propagation time control devices.

Abstract: A digital concatenator, the operation of which is triggered by the sequential arrival of a series of n-bit bytes thereto, accepts such sequential n-bit bytes and, by directing those n-bit bytes into sequentially identified n-bit channels, concatenates those n-bit bytes into (n×m)-sized words, where m is a pre-selected integral number of said n-bit bytes that are desired to be concatenated with an (n×m)-sized output buffer into a resultant sequence of (n×m)-sized words. The sequential identification of those n-bit bytes is brought about by a cyclical counter incorporated within a data enumerator that counts off the arrival of each n-bit byte and appends a corresponding position bit or byte to each one thereof. Each successive reading of the output of the concatenator is triggered by the arrival at that output buffer through an mth channel of an mth n-bit byte. The concatenator similarly operates on single bits so as to serve as a serial to parallel converter of arbitrarily selectable size.

Abstract: A method for serializing bits without introducing glitches (i.e., spurious signals) into the serialized data stream is disclosed. Furthermore, the embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, the illustrative embodiment of the present invention requires timing signals with a frequency equal to the rate at which words are loaded into the serializer. The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second unanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.

Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract: The invention relates to a method and an arrangement for reducing interference created in an output signal in connection with signal conversion. The arrangement may employ two structural sets, whereof the arrangement comprises at least one. The first structural set comprises a modulator (10) arranged to modulate the signal, and a DA converter (30) arranged to convert the serial-mode input signal arriving from the modulator into an analogue output signal. In addition, the first structural set comprises a serial/parallel converter (20) arranged to convert the modulated signal into parallel mode, and a divider (40) for generating a clock signal, the frequency of the clock signal generated by the divider being lower than the frequency of the clock signal used in serial-mode input signal transmission. The divider (40) is arranged to simultaneously clock several signals to the DA converter (30).

Abstract: In the asynchronous serial data transmission and/or reception conducted by an asynchronous serial data communication device, an asynchronous serial data receiving device as an asynchronous serial data receiver section inputs a count correction signal (15) from a count correction circuit (2), and a control signal generating circuit (1) that generates a data shift signal (120) controls the timing for outputting the data shift signal (120) in accordance with the count value correction signal (15). The time intervals during which a serial-to-parallel conversion circuit (3) samples a communication data (4) is changed as to each data bit in accordance with this data shift signal, so that the sampling interval can be set more precisely than just a multiple of integer of the operation clock (110), thereby to improve the baud.

Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

Abstract: An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.

Abstract: In general, one embodiment of the invention involves an apparatus that comprises a fast acquisition logic coupled to an oversampler. The fast acquisition logic is configured to detect whether any of a plurality of data samples produced by the oversampler is inaccurate, and if so, to cause data to be recovered from a new data sample different from the data sample previously being used for data recovery. The new data sample would be multiple sampling states away from the previous data sample.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.

Abstract: A method for controlling a plurality of service units in a telecommunications system with a multi-carrier transmission scheme is provided. Specifically, in one embodiment, the method includes broadcasting control signals for the service units over a plurality of control channels distributed in a number of subbands of a frequency bandwidth. The method further includes identifying the service unit to use the control signal with an identifier.

Abstract: By a shift register, n×d bits of data input Din are converted into parallel signals and latched by a register. A shift register is loaded with the parallel signals latched to the register when a data load signal is at high level and converts the loaded parallel signals into serial signals and outputs the serial signals as output data Dout when the data load signal is at low level. Therefore, connection between the register and the shift register is set such that a time-sequential order of the input data Din can be switched and accordingly, block interleaving can be carried out without using storages.

Abstract: A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

Abstract: A center phase decision circuit for deciding a center phase of a data signal, in which, in case the data signal is subjected to disturbance in the signal waveform, the signal is corrected for the disturbance to re-establish normal communication.

Abstract: An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed data signal. By using the buffers and registers, the incoming signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable communication link and will also provide a less expensive solution for serialization/deserialization. The present invention includes a serializer that receives parallel data input from a computer and serializes the data for transmission over a high-speed serial communication link.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: An image signal processing circuit (102) includes a phase-expansion circuit (103), a digital polarity-inversion circuit (104), first to sixth D/A converters (111 to 116), and first to sixth operational amplifiers (151 to 156). The resistance value of the first to sixth amplitude adjusting resistors (121 to 126) which cause the output amplitude of an analog signal output from the first to sixth D/A converters (111 to 116) to be fixed is adjusted by laser trimming. First to sixth gain setting resistors (161 to 166) are connected to the first to sixth operational amplifiers (151 to 156). The first gain setting resistor (161) includes a first resistor (131) and a second resistor (141), and the gain of the operational amplifier (151) is set by the resistance ratio (R2/R1) thereof. In order that this resistance ratio (R2/R1) is fixed for each set, the first resistor (131) and the second resistor (141) are formed on the same substrate by undergoing the same manufacturing process.

Abstract: Methods and systems for transmitting data over a printed circuit board such as a backplane for example, are provided. The printed circuit board has a number of primary tracks each connected to receive a data stream from a respective transmitter which may be located on a card connected to the printed circuit board for example. The data streams are offset in time with respect to one another such that rising edges and falling edges do not coincide with each other in time. The primary tracks are all coupled electromagnetically to a single coupling track at another location on the printed circuit board, and the coupling track is connected to a receiver which may be located on another card for example. The transmitted data streams are all coupled electromagnetically onto the coupling track with each rising edge of any of the data streams resulting in a positive pulse in a coupled signal, and each falling edge of any of the data streams resulting in a negative pulse in the coupled signal.

Abstract: A highspeed bus architecture featuring low signal levels, differential sensing, and zero net current over a four wire transmission line cluster. The bus system comprises a system for transmitting n bits of data and includes an encoding system for receiving the n bits of data and outputting m signals wherein the m signals have a zero net current, m transmission lines for carrying the m signals, and a decoding system for receiving the m signals and converting the m signals back into n bits of data, using differential amplifiers.

Abstract: An apparatus for adjusting the phase difference of a first clock signal (48) and a second clock (50) is disclosed. The apparatus includes a phase indicator (42) which receives a first clock signal (48) and a second clock signal (50) and determines a phase relationship. A microprocessor (44) outputs a digital value related to the phase relationship. An analog to digital converter (46) receives the digital value and outputs an analog value based on the digital signal. After that a voltage controlled constant current source (47) receives the analog value and outputs a constant current source proportional to the analog value. Finally, a phase lock loop circuit (10) receives the constant current source and adjusts the phase relationship.

Abstract: A circuit for serializing parallel data of n bits, comprising a first register for storing m bits of the parallel data, M being less than N, the first register being clocked by a first clock, at least one second register other than the first register for storing at least N-M bits of the parallel data, the at least one second register being clocked by at least one second clock which is different in phase from the first clock, at least one third register for storing at least the nth and (n−1)th bits of parallel data output from the at least one second register, the third register being clocked by at least one third clock which is different in phase from the first and the second clocks, and logic gates for receiving as inputs the n bits of parallel data output from the first register and output from one or both of the at least one second register and the third register to form N serial data.

Abstract: A format converter in which the data input is a 16 bit wide interface. The circuit finds the 66-bit coding block boundaries. In one embodiment, a circuit presents the 66-bit data blocks at the output in an aligned format. The circuit relies on control inputs from a state machine which controls the operating mode and to which it delivers status information. The two main operating modes are the “normal data” mode or the “hunt” mode for the 66-bit block boundaries.

Abstract: An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Abstract: An oversampling circuit and method is proposed, which is used for converting an input serial data stream into a parallel data format. The proposed oversampling circuit comprises an array of transmission gates arranged into N cascaded stages of main sampling circuits, each stage of main sampling circuit being composed of M parallel layers of sub-sampling circuits, where N, M are each an integer number; each transmission gate has an input end, an output end, and a control port; and the respective control ports of all the transmission gates are connected to a predefined sequence of sampling pulses.

Abstract: A circuit arrangement is described for converting a parallel data stream into a serial data stream and for intermediate storage and clocked supply of the data stream, which is characterized in that a first shift register (1) is provided in which the parallel data stream is stored in bit frames in dependence upon an externally supplied processor clock and which supplies a serial data stream by means of bit-wise scanning of the stored data, which serial data stream is applied in parallel to all memory locations of a second, bit-wise addressable shift register (2) from which the data stored therein are serially read in dependence upon a serial clock, and which supplies the serial data stream, in that the second shift register (2) is assigned to a load shift register (3) supplying a level indicator which constantly marks the limit between memory cells of the second shift register (2) with valid, stored data and memory cells which are to be newly written with data, and in that storage of the data supplied by the f

Abstract: A serial-deserializer converts a high speed serial data input to a lower speed parallel output. By including this circuit on a chip, connections to the chip are made more easily. A gated voltage controlled oscillator provides clock signals to sample the data input at a high rate. The output signals are thus provided at a slower rate.

Abstract: A multiple time domain serial-to-parallel converter includes a combiner operable to receive a stream of serial data within a first time domain and to accumulate a portion of the serial data into a set of parallel data. A first hold register is coupled to the combiner. The first hold register is configured to operate within the first time domain and operable to load the set of parallel data in response to a first load signal based on the first time domain. A second hold register is coupled to the first hold register. The second hold register is configured to operate within a second time domain and operable to load the set of parallel data from the first hold register in response to a second load signal based on the second time domain.

Abstract: A semiconductor integrated circuit device has a redundancy circuit such that when a parallel/serial conversion circuit converts the separation information of a program element group such as one fuse element group to serial data, the serial data is transmitted through a serial/parallel conversion circuit, thus controlling circuits to be controlled such as a plurality of RAMs. Further by introducing a CRC technique in the parallel/serial conversion circuit, even when there is an error input such as cutting error of the fuse element, the information may be reproduced.

Abstract: A semiconductor integrated circuit device has a redundancy circuit such that when a parallel/serial conversion circuit converts the separation information of a program element group such as one fuse element group to serial data, the serial data is transmitted through a serial/parallel conversion circuit, thus controlling circuits to be controlled such as a plurality of RAMs. Further by introducing a CRC technique in the parallel/serial conversion circuit, even when there is an error input such as cutting error of the fuse element, the information may be reproduced.

Abstract: A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus.

Abstract: A receiver interface for interfacing with an Advanced Technology Attachment Packet Interface (ATAPI) in a first device. The receiver interface includes a converter, a depacketizing circuit, and an ATAPI receiver circuit. The converter converts a first set of signals from a serial bus into a second set of signals. The first set of signals are serial to one another and use low-voltage, differential signaling (LVDS). The first set of signals are adapted to be received on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) bus. In contrast, the second set of signals are serial to another and use TTL voltage levels and single-ended signaling. Additionally, the second set of signals use a packet format to represent a packet. The depacketizing circuit disassembles the packet represented by the second set of signals to generate a third set of signals, which are parallel to one another and use TTL, single-ended signaling.

Abstract: A self-powered USB machine. A power control switch 23 is installed in a main power circuit 21 of the USB machine. By detecting whether a voltage occurs at a +5V power terminal of a USB port, the power control switch 23 is turned on or off. A pull-up resistor 17 is connected to a switch 18 in series. And, the pull-up switch 18 is turned on or off after the power control switch 23 is turned on or off. Thereby, the power consumption is reduced.

Abstract: A method of designing a semiconductor integrated circuit includes the steps of generating a cell that includes a flip-flop and backup transistors, designing a circuit by use of the cell, and adjusting a timing by connecting the backup transistors to the flip-flop if there is a need to adjust timing of the flip-flop.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: In a frame aligner, a serial/parallel converter converts an input serial data signal into a first parallel data signal. A first buffer receives the first parallel data signal to generate a first parallel data signal, and a second buffer receives the first parallel data signal to generate a second parallel data signal. A selector selects one of the first and second parallel data signals to generate a third parallel data signal. A parallel/serial converter converts the third parallel data signal into an output serial data signal. A buffer control circuit operates the first and second buffers at different phase timings in accordance with an input frame phase signal. A selector control circuit operates the selector in accordance with a difference in phase between the input frame phase signal and an output frame phase signal.