Abstract: An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.

Abstract: A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate.

Abstract: A transmitter apparatus is provided for converting parallel data of natural number n×12 bits into n pieces of serial data, and transmitting n transmission signals each of natural number m bits. In the transmitter apparatus, a dividing buffer divides inputted parallel data into n pieces of 12-bit parallel data, and an encoder circuit 12B14B-converts the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and outputs resulting data. A parallel-to-serial converter circuit parallel-to-serial converts the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and outputs resulting data, and an m-bit driver circuit amplifies and transmits the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths.

Abstract: In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.

Abstract: The invention relates to a method and a system for external, digital coding of a baseband or intermediate-frequency signal. Initially, a digital datastream is converted in a coding device into a digital-baseband signal in the time domain or into a digital intermediate-frequency signal in the time domain. The digitally generated signal is output via an asynchronous-serial interface of the coding device to another device. Such a device also provides an asynchronous-serial interface, which is connected to the asynchronous-serial interface of the coding device. The device reads in the output digital-baseband signal or intermediate-frequency signal for further processing.

Abstract: For synchronizing multichannel extension data with an audio signal, wherein the audio signal includes block division information and the multichannel extension data include reference audio signal fingerprint information, the block division information in the audio signal is detected by means of a block detector. Thereupon, block division of the audio signal is performed by a fingerprint calculator according to the block division information in order to obtain a sequence of test audio signal fingerprints. In addition to that, a sequence of reference audio signal fingerprints is extracted from the reference audio signal fingerprint information of the multichannel extension data. Both sequences of fingerprints are correlated in order to obtain a correlation result, by which a compensator is controlled in order to reduce or eliminate a time offset between the multichannel extension data and the audio signal.

Abstract: A first multiplexer, at each given cycle, outputs a second input data signal, after outputting a first input data signal. A second multiplexer, at each given cycle, outputs a fourth input data signal, after outputting a third input data signal. The second multiplexer outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer. At each given cycle, a third multiplexer, after outputting the first input data signal and the second input data signal output from the first multiplexer, outputs the third input data signal and the fourth input data signal output from the second multiplexer.

Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.

Abstract: A method for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: For calculating a fingerprint of an audio signal, the audio signal is divided into subsequent blocks of samples. For the subsequent blocks, one fingerprint value each is calculated, wherein fingerprint samples of subsequent blocks are compared. Based on whether the fingerprint value of a block is higher than the fingerprint value of a subsequent block or not, a binary value is assigned, wherein information about a sequence of binary values is output as fingerprint for the audio signal.

Abstract: The present invention refers to a signal concentrator comprising: a parallel to serial conversion device comprising a plurality of parallel inputs and a serial output, a control unit comprising detection means adapted for detecting the activity of said plurality of parallel inputs of said parallel to serial conversion device, indication means adapted for indicating the active parallel inputs to the parallel to serial conversion device and controlling means adapted for setting an operating bitrate of the serial output in function of said activity of said plurality of parallel inputs.

Abstract: The present disclosure is directed to a system and method for serializing data streams. In some implementations, a device includes a sapphire substrate and an integrated circuit formed on the sapphire substrate. The integrated circuit is configured to receive a plurality of digital signals from a detector and successively multiplex the plurality of digital signals to generate a serialized signal with a data rate approximately 4 Gb/s or greater, the integrated circuit having a feature size of approximately 0.10 ?m or greater.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: A serial-to-parallel converter which includes n input latching elements; k intermediate latching elements, and n output latching elements configured to sample outputs of the k intermediate latching elements and a remaining (n?k) input latching elements of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n>k.

Abstract: A parallel-to-serial conversion circuit includes a plurality of parallel-to-serial conversion units, each being configured to include a dividing circuit configured to divide a clock signal having a second clock cycle to generate a clock signal having a first clock cycle, a parallel input circuit configured to input a signal having a plurality of bits parallel to one another in the first clock cycle, and a serial output circuit configured to serially output the signal having the plurality of bits input to the parallel input circuit bit-by-bit in the second clock cycle, wherein, among the plurality of parallel-to-serial conversion units, one of the dividing circuits has a synchronization signal interface that causes an output clock signal to synchronize with a clock signal output from the other dividing circuit in another parallel-to-serial conversion unit.

Abstract: A semiconductor device includes a multiplexer and an output buffer. The multiplexer includes: n switches (n is an integer of 2 or greater) each including an input node receiving a different data signal and an output node coupled to an input node of the output buffer; and a plurality of switch control circuits each corresponding to a respective one of the n switches. Each of the plurality of switch control circuits turns on a corresponding one of the n switches based on a corresponding one of the signals each having a first cycle and a phase different by 1/n of the cycle from adjacent phases. When each of the plurality of switch control circuits detects that an input-side data signal of the corresponding one of the n switches appears at a corresponding output-side node, each of the plurality of switch control circuits turns off the corresponding switch.

Abstract: A circuit includes a first circuit portion operable as a digital-to-analog converter (DAC) for generating a DAC common mode voltage signal (outp), a second circuit portion having a comparator for comparing the DAC common mode voltage (outp) against a received signal common mode voltage (vsumdc), the comparator providing a single bit output, and a single bit register configured to receive the single bit output of the comparator, the single bit output used to control a feedback circuit, the feedback circuit configured to control the DAC common mode voltage signal.

Abstract: The invention provides a serializer. In one embodiment, the serializer converts parallel input data into serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively selects a plurality of received input bits from the input bits of the parallel input data, and respectively serializes the received input bits according to the full swing clock to generate a plurality of first middle data signals. The CML D flip-flops respectively latches the first middle data signals to generate a plurality of second middle data signals. The at least one multiplexer receives the second middle data signals, and interleaves the second middle data signals according to the noiseless differential clock to generate the serial output data.

Abstract: A method for converting image data from serial to parallel is provided. The method has steps of: receiving serial data of an image into a line buffer according to a serial clock signal of the image, wherein the serial data at least comprises a frame start code, and a row start code; detecting the frame start code of the serial data in the line buffer to trigger a vertical synchronous signal of the image; and detecting the row start code of the serial data in the line buffer to trigger a horizontal synchronous signal of the image.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: The invention provides a serializer. In one embodiment, the serializer converts parallel input data into serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively selects a plurality of received input bits from the input bits of the parallel input data, and respectively serializes the received input bits according to the full swing clock to generate a plurality of first middle data signals. The CML D flip-flops respectively latches the first middle data signals to generate a plurality of second middle data signals. The at least one multiplexer receives the second middle data signals, and interleaves the second middle data signals according to the noiseless differential clock to generate the serial output data.

Abstract: A transforming circuit between parallel data and serial data includes a current source, a clock input sub-circuit, and a parallel data input sub-circuit. The clock input sub-circuit includes a first clock signal terminal and a second clock signal terminal. The transforming circuit between parallel data and serial data also includes a clock control sub-circuit and a serial data output control sub-circuit. The clock control sub-circuit includes four switching elements. A first and a third switching elements are controlled by the second clock signal terminal, and a second and a fourth switching elements are controlled by the first clock signal terminal. The serial data output control sub-circuit includes a fifth switching element and a sixth switching element to speed up the falling edge of the output signal flip, a seventh switching element and an eighth switching element to limit the output signal amplitude. A transforming system thereof is also provided.

Abstract: The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a pixel array, a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively, and a plurality of serial link terminals coupled to the pair of IO circuit blocks. The pixel array may comprise a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise: a chemically-sensitive transistor, and a row selection device.

Abstract: A serializer includes a clock generator configured to receive N reference clock signals (?_<N?1:0>) (where N is a natural number) having different phases, and generate first clock signals (?_<N?1:0>) and second clock signals (?d_<N?1:0>); a logic circuit configured to generate output signals (?o_<N?1:0>) of N parallel data pieces using the first clock signals and the second clock signals; and a drive circuit configured to serialize data corresponding to N output signals received from the logic circuit, and output the serialized data.

Abstract: A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: In a method for decoding digital information, a bit-stream signal comprising binary information is received at a digital receiver utilizing wired communication. The received bit-stream signal is sampled for each binary value at least two different sampling points within an eye pattern associated with the related binary value in order to obtain a hard-bit value for each sampling point. A single soft-bit value for each binary value based on the hard-bit values of the relevant binary value is generated and the bit value of the binary value is determined by subjecting the soft-bit values to a soft-decision algorithm.

Abstract: Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order.

Abstract: An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of a frequency dividing bit pattern defining a frequency divisor. The parallel-to-serial converter performs a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream of the parallel word.

Abstract: A transmitter apparatus is provided for converting parallel data of natural number n×12 bits into n pieces of serial data, and transmitting n transmission signals each of natural number m bits. In the transmitter apparatus, a dividing buffer divides inputted parallel data into n pieces of 12-bit parallel data, and an encoder circuit 12B14B-converts the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and outputs resulting data. A parallel-to-serial converter circuit parallel-to-serial converts the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and outputs resulting data, and an m-bit driver circuit amplifies and transmits the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n?1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n?1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n?1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n?1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

Abstract: According to one embodiment, an electronic apparatus non-masks a clock signal portion used for shift-outputting respective digital signals by first parallel/serial converting device and masks the remaining clock signal portion, in the clock signal supplied to the first and second parallel/serial converting devices, in a first mode. The apparatus non-masks the clock signal supplied to the first and second parallel/serial converting devices, in a second mode.

Abstract: A data receiver identifies an alignment symbol in a parallel data stream including encoded symbols, generates a bit order indicator indicating a bit order of the alignment symbol identified in the parallel data stream, and generates a symbol stream including the encoded symbols. Further, the data receiver decodes symbols in the symbol stream and generates a bit polarity indicator indicating a bit polarity of the parallel data stream based on the decoded symbols. Additionally, the data receiver generates a formatted symbol stream having a predetermined bit order and a predetermined bit polarity, based on the symbol stream, the bit order indicator, and the bit polarity indicator. In some embodiments, the data receives a serial data stream and generates the parallel data stream by deserializing data in the serial data stream.

Abstract: A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: A parallel-to-serial conversion circuit includes a plurality of parallel-to-serial conversion units, each being configured to include a dividing circuit configured to divide a clock signal having a second clock cycle to generate a clock signal having a first clock cycle, a parallel input circuit configured to input a signal having a plurality of bits parallel to one another in the first clock cycle, and a serial output circuit configured to serially output the signal having the plurality of bits input to the parallel input circuit bit-by-bit in the second clock cycle, wherein, among the plurality of parallel-to-serial conversion units, one of the dividing circuits has a synchronization signal interface that causes an output clock signal to synchronize with a clock signal output from the other dividing circuit in another parallel-to-serial conversion unit.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: A serializer device is used for generation, from a parallel digital signal, of a clock signal or a serial binary data signal having a pre-determined amount of jitter. A binary number having consecutive groups of ones and zeroes, when serialized by the serializer device, produces a clock signal. By varying the number of ones and zeroes on the binary number, a pre-determined amount of jitter can be generated. Use of sigma-delta modulation in combination with a phase-locked loop circuitry allows one to obtain a smoothly varying jitter of the output signal.

Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

Abstract: A transmitter including an analog front end configured to receive a serial signal; a control circuit configured to generate a first gain signal and a second gain signal based on a characteristic of a serial channel; a first amplifier is configured to amplify the serial signal to generate a first amplified signal based on the first gain signal; a first delay device configured to delay the serial signal to generate a first delayed signal; a second amplifier configured to amplify the first delayed signal to generate a second amplified signal based on the second gain signal; and at least one summer is configured to sum the first amplified signal and the second amplified signal to generate an output signal. The output signal is transmitted on the serial channel.

Abstract: Provided is a multi-mode ultra broadband wireless communication apparatus and method, and a multi-mode ultra broadband transmitting apparatus may include a baseband outputting unit to parallelly output multiple digital signals, a mid-frequency processing unit to up-convert the outputted parallel digital signals to mid-frequencies, and the up-conversion is performed in a range where the outputted parallel digital signals do not cause interference with each other, a parallel-to-serial converter to convert, to a serial digital signal, the converted parallel digital signals that are up-converted to the mid-frequencies, a digital-to-analog converter to convert the serial digital signal to an analog signal, and a radio frequency processing unit to up-convert the analog signal to multiple transmission frequencies respectively corresponding to desired communication services.

Abstract: A transforming circuit between parallel data and serial data includes a current source, a clock input sub-circuit, and a parallel data input sub-circuit. The clock input sub-circuit includes a first clock signal terminal and a second clock signal terminal. The transforming circuit between parallel data and serial data also includes a clock control sub-circuit and a serial data output control sub-circuit. The clock control sub-circuit includes four switching elements. A first and a third switching elements are controlled by the second clock signal terminal, and a second and a fourth switching elements are controlled by the first clock signal terminal. The serial data output control sub-circuit includes a fifth switching element and a sixth switching element to speed up the falling edge of the output signal flip, a seventh switching element and an eighth switching element to limit the output signal amplitude. A transforming system thereof is also provided.

Abstract: A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second sampling circuit that samples, according to a second clock signal that is an inverse of the first clock signal, replica data that is synchronized with the serial data; a third sampling circuit that samples, according to plural third signals respectively having different phases, output from the second sampling circuit; and a control circuit that controls sampling timing of the first sampling circuit, based on each output from the third sampling circuit.

Abstract: The present invention refers to a signal concentrator comprising: a parallel to serial conversion device comprising a plurality of parallel inputs and a serial output, a control unit comprising detection means adapted for detecting the activity of said plurality of parallel inputs of said parallel to serial conversion device, indication means adapted for indicating the active parallel inputs to the parallel to serial conversion device and controlling means adapted for setting an operating bitrate of the serial output in function of said activity of said plurality of parallel inputs.