Abstract: A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

Abstract: Provided are a multiplexer for controlling a data output sequence and a parallel-to-serial converter using the multiplexer. The multiplexer is configured to simply control the output sequence of input data in accordance with a value of a selection signal. The parallel-to-serial converter with the multiplexer can easily control an output bit sequence of serial data without altering an interconnection structure of parallel data signal lines.

Abstract: A transmission device includes: parallel/serial conversion units; a clock signal transmission unit; a known-parallel data generation unit for inputting known-parallel data to the parallel/serial conversion units; a clock shift unit for sequentially shifting a clock signal, which is outputted from the clock signal transmission unit, by 1 UI of a data signal; sampling units for sampling data signals obtained by serializing the known-parallel data, in accordance with the clock signal shifted by 1 UI; and a diagnostic processing unit for making a diagnosis as to whether the transmission device is operating normally by comparing sampling results with the known-parallel data, and outputting a result of the diagnosis.

Abstract: The first data transmitting/receiving device according to the present invention includes: a serial-parallel conversion circuit for converting received first serial data to first parallel data; a data selection circuit for selecting any one of the first parallel data and externally-supplied second parallel data and outputting the selected data; and a parallel-serial conversion circuit for converting the first or second parallel data output from the data selection circuit to second serial data which is to be transmitted.

Abstract: A serializer receives parallel data and a control signal. The serializer splits the parallel data into multiple subportions of data and, based on the control signal, sequentially outputs each of said subportions as serial output data in one or more serial output channels. The number of serial output channels is dictated by the control signal.

Abstract: A flexible converter interface for interfacing with ADCs or DACs. The flexible converter interface may be comprised in a data acquisition device and may be a programmable ADC interface or a programmable DAC interface. The flexible converter interface may be programmed with a converter type parameter, a converter resolution parameter, and a converter data type parameter, among others, to interface with various types of ADCs or DACs and to allow for future expandability. The flexible converter interface may function as either a programmable parallel converter interface or a programmable serial converter interface depending upon the programmed converter type parameter. Additionally, functions associated with I/O pins corresponding to the flexible converter interface may vary depending upon the programmed converter resolution parameter and the programmed converter type parameter.

Abstract: Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop.

Abstract: A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.

Abstract: A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

Abstract: A LVDS and TMDS dualfunction transmitter for both LVDS and TMDS output channels is disclosed, including an encoder and a serializer. The encoder encodes twenty eight bits of LVDS signals to thirty bits of TMDS signals. The serializer includes four serializer channels for converting the LVDS signals to a serial signal when a LVDS mode is enabled, or converting the TMDS signals to the serial signal when a TMDS mode is enabled. Wherein a first serializer channel is coupled to seven bits of the LVDS signals and outputting a first pair of differential signals. Second, third and fourth serializer channel are coupled to seven bits of the LVDS signals and ten bits of TMDS signals, and outputting a second, third and fourth pair of differential signals, respectively.

Abstract: Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.

Abstract: The invention relates to a transceiver optical system in which a single serializer/deserializer (SERDES) chip is used to drive a plurality of transceiver modules.

Abstract: A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

Abstract: A serial bit transparent data transferring technique eliminating the bit ambiguity problem of the standard time-division multiplexing/demultiplexing architecture without introduction of any extra latency. A serializer multiplexer converts input parallel data words into a serial data bit stream under control of a serializer timing circuit. An output multilevel buffer retimes the serialized data and increases the amplitude of certain bits with a preselected value to mark positions of out-going serial data words. The bits are defined by a serializer digital data converter also controlled by the same timing circuit. The imposed marking pulses are retrieved from the input serial data stream by a multilevel input detector of a deserializer timing circuit and used for the synchronization of the demultiplexing operation. As a result, the deserializer directly reconstructs the original bit order from the serial data bit stream with no extra bits, thus providing minimal possible latency and full data rate.

Abstract: A method for serially transmitting data between a first and a second station is provided, the first station unidirectionally transmitting at least two signals to the second station on two signal paths. In this method, a shift register is provided in each station, the two signal paths of the first station being routed in parallel into a shift register, and the data transmission to the second station being carried out by automatically clocking the shift register from a time base.

Abstract: A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: Method and system on an aircraft for converting plural data inputs and plural data outputs from a parallel format to a serial format is provided. The system includes an integrated software module that accepts plural variable number of inputs and generates a plural variable number of outputs; an analog input processing module that receives plural analog inputs, converts the analog inputs to digital data and sends the digital data to the integrated software module; a digital input processing module that receives discrete digital inputs and transfers the digital inputs to the integrated software module; a digital output module that receives data from the integrated software module; and an analog output module that receives digital data from the integrated software module and converts the digital data into analog data by using a digital to analog converter.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A serial-parallel conversion circuit in which power consumption is reduced is provided by using a latch clock generation circuit including multiple latch signal generation circuits which outputs a latch signal with a period of an integer multiple of that of a system clock signal. Here, the latch signal generation circuit includes a gate circuit which receives a control signal and a feedback signal, and outputs, according to a combination of the received control signal and feedback signal, a latch signal obtained by inverting a pulse corresponding to one clock of the system clock signal, and an output synchronization circuit which holds the latch signal output from the gate circuit and at the same time outputs the latch signal as a control signal supplied to a gate circuit of a latch signal generation circuit of the succeeding stage and a feedback signal supplied to the gate circuit of the self stage.

Abstract: A parallel-to-serial converter selects variable-ml-bit parallel dummy data from m-bit parallel dummy data (0?m1?m) together with a n-bit parallel data signal synchronized with a first clock signal having a first frequency, and converts the selected (n+m1)-bit parallel data into a (n+m1)-bit serial data signal synchronized with a second clock signal having a frequency (n+m1) times the first frequency. A serial-to-parallel converter circuit selects n-bit serial data from the (n+m1) parallel data signal and converts the n-bit serial data into a n-bit parallel data signal synchronized with the first clock signal.

Abstract: In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

Abstract: A system for presenting serial drive signals for effecting communication of parallel data signals includes: a controller; a serializer coupled with the controller; and a tri-state logic device coupled with the serializer. The controller provides parallel logic state signals to the serializer. The serializer treats the parallel data signals to present a serial data signal representing the parallel data signals at a first output locus, and treats the parallel logic state signals to present a serial logic state signal representing the parallel logic state signals at a second output locus. The tri-state logic device receives the serial data signal and the serial logic state signal for logical evaluation. The tri-state logic device presents the serial drive signals at a third output locus. Each respective drive signal has a respective drive state. Each respective drive state is determined by the logical evaluation.

Abstract: A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuit 8 produces trigger phase information indicating the phase relationship between the trigger signal and a reference clock. A data pattern generating circuit 10 generates parallel data bits according to the reference clock in response to the trigger signal. A data shifting circuit 11 rearranges the parallel data bits in a predetermined order to produce shifted parallel data bits in which data bit order is shifted relative to the reference clock as a function of the trigger phase information. A parallel to serial converter 16 converts the shifted parallel data bits into serial data bits.

Abstract: An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a functional module adapted to communicate according to a narrow protocol and an emulation module that transforms between the two protocols so that the two functional components can communicate with each other using the physical interface.

Abstract: A physical layer device includes a deserializer that deserializes one of first and second data streams. The first data stream includes successive N-bit sequences having one of all ones and all zeros. A converter oversamples the first data stream, identifies edge transitions in the first data stream to locate N adjacent bits that substantially align with the N-bit sequences, and samples at least one bit of the N adjacent bits.

Abstract: The present invention provides a memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the parallel data. This memory device connects one external terminal to the serial-parallel conversion section and another external terminal to the parallel-serial conversion section when access using a serial interface is performed. On the other hand, the memory device connects a plurality of external terminals to the parallel-parallel conversion section when access using a parallel interface is performed, thereby enabling the memory device to occasionally realize parallel transfer of data while using a conventional package.

Abstract: Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A virtual-to-physical address translator is configured to translate a virtual address to provide physical addresses and select signals, where the physical addresses are locations of at least a portion of data words of a cell stored in the concatenated memories in successive order. The multiplexers are coupled to receive the select signals as control select signaling to align the at least one data word obtained from each of the concatenated memories for lane aligned output from the aligner.

Abstract: A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiring section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.

Abstract: A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

Abstract: Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.

Abstract: A PCI Express device is provided. The PCI Express device includes a symbol lock module that includes a state machine for detecting a special character in a serial bit stream received from a serial/de-serializer, wherein the state machine receives a first special character and verifies alignment of the special character by comparing with a previously stored alignment value and the state machine declares a symbol lock if at least more than one special character alignment matches with a same stored alignment value. The special character is a comma sequence. After a symbol lock is declared, the state machine continues to monitor incoming bit stream data and compares each new special character alignment with the previously stored alignment value. During the monitoring if a misaligned special character is detected, then the state machine waits to receive another special character before declaring a loss of synchronization.

Abstract: A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform.

Abstract: A method for transmitting a digital data word, and an apparatus for carrying out the method, include the following processing steps: First, the data word is converted into a first serial differential data sequence which contains the information in at least one initialization bit and in the data bits of the data word in time with a clock signal. The data word is also converted into a second serial differential data sequence which contains the information in at least one initialization bit and in the data bits of an inverted data word, obtained by inverting the data word, in time with the clock signal. Next, the first differential data sequence is transmitted via a first data channel, and the second differential data sequence is transmitted via a second data channel.

Abstract: The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

Abstract: A Recursive bit-stream converter (Rebic) having digital low pass filter and multi-bit quantizer means in a feedback arrangement and means to serialize digital words obtain a non-integer Rebic factor via at least two quantizers that are successively operative to serialize their digital words to the output of the converter.

Abstract: A data transfer apparatus comprises a plurality of selectors each having two inputs and an output, and a transfer gate gating the transfer of data, wherein one inputs of the plurality of selectors are connected to respective bits of a data bus in the order that transfer bits are arranged, while the other inputs thereof are connected to the outputs of the other selectors in the order, the transfer gate is connected to the output of the final-stage selector of the plurality of selectors, data of the respective corresponding bits of the data bus is set in the respective plurality of selectors when a transmission enable signal is in a negated state, and when the transmission enable signal is arranged to be in an asserted state, the plurality of selectors and the transfer gate are connected so as to serially transfer the data, and the set data is serially transferred in the connecting state by means of a delayed action resulting from an inter-selector delay time.

Abstract: An information-processing apparatus includes a controller for sending a first parallel digital signal having a plurality of bits, a first converter for time-dividing the first parallel digital signal as to convert the first parallel digital signal into a serial signal, a first case for accommodating the controller and the first converter, a second converter for converting the serial signal into a second parallel digital signal having a plurality of bits, a wireless communication device for receiving the second parallel digital signal to producing a high frequency signal based on the second parallel digital signal, an antenna for transmitting the high frequency signal, a second case for accommodating the second converter and the wireless communication device and for having the antenna mounted thereto, a hinge unit coupling the second case rotatably with the first case, and a signal line provided at the hinge unit and transmitting the serial signal between the first converter and the second converter.

Abstract: A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: Method and system on an aircraft for converting plural data inputs and plural data outputs from a parallel format to a serial format is provided. The system includes an integrated software module that accepts plural variable number of inputs and generates a plural variable number of outputs; an analog input processing module that receives plural analog inputs, converts the analog inputs to digital data and sends the digital data to the integrated software module; a digital input processing module that receives discrete digital inputs and transfers the digital inputs to the integrated software module; a digital output module that receives data from the integrated software module; and an analog output module that receives digital data from the integrated software module and converts the digital data into analog data by using a digital to analog converter.

Abstract: In an LVDS system for converting N types (for example N=3) of parallel signals into serial signals and sending/receiving the converted serial signals between a driver and a receiver through M (M?N) signal lines, a sequencer 11 for selecting drivers 10a to 10c to be used in accordance with the number of signal lines used for transmission/reception and a reception-side sequencer for selecting a receiver to be used in accordance with the number of signal lines M used for transmission/reception are included to perform transmission/reception by using the driver and receiver selected by the both sequencers. Thus, it is possible to select the number of channels and a data rate optimum for the impedance of a signal line without fixing the number of signal lines used for transmission/reception.

Abstract: A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit.

Abstract: A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and to generate a second plurality of timing signals when the width of the parallel input data is of a second multiple. The parallel to serial module is operably coupled to convert the parallel input data into serial output data based on the first or second plurality of timing signals.

Abstract: A key signals input apparatus and related operating method used for reducing chip I/O number is described. The key signals input apparatus has a plurality of keys and a signal conversion module. The signal conversion module converts key signals into an analog voltage before directing to the chip for further processing. An analog signal decoding module designed in the chip decodes the analog signal so as to recover a plurality of input key values such that the chip may perform further operations according to the indication of the key signals.

Abstract: A method and apparatus for synchronizing multiple-stage multiplexers are disclosed. According to exemplary embodiments of the present invention, multiplexer circuits in the multiple-stage multiplexer are synchronized based upon a frequency response of the output of the multiplexer. The power level of the output of the multiple-stage multiplexer is measured at a frequency corresponding to the input data rate of the multiple-stage multiplexer, during the time a test pattern is sent through the multiple-stage multiplexer. In an exemplary embodiment of the invention, the multiple-stage multiplexer is placed in substantially random states until the measured power level reaches the predetermined.

Abstract: A hybrid serial/parallel bus interface method and apparatus for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The method/apparatus is adaptable for either bidirectional or unidirectional applications.

Abstract: A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero (“RTZ”) data latch register. The RTZ data latch register has a first (“even”) series of RTZ data latches and a second (“odd”) series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.

Abstract: A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+? with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+?. so as to create a null time ? and a control signal is inserted into the null time ?, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.

Abstract: A serializer for multiplexing 2N data streams, each data stream having a frequency of f/(2N), N being a positive integer. The serializer comprises 2N?1 instances of a dual-edge multiplexer flip-flop circuit, N frequency domains including a first frequency domain having the frequency f/2N and a last frequency domain having a frequency f/2, and an output providing serialized data at frequency f clocked at half that rate. Thus, the highest clock signal frequency input into the serializer is f/2.

Abstract: In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.