Abstract: A serial/parallel data conversion apparatus and a method thereof are used to convert serial data into parallel data by a delay pulse and three stage registers, wherein the device includes a first data register, a second data register, a third data register, a frequency divider and a delay controller. Moreover, the first data register converts the serial data into the parallel data according to a first working clock signal. The frequency divider performs a frequency division for the first working clock signal for producing a second working clock signal. The second data register acquires the parallel data from the first register according to the second working clock signal. The delay controller delays the second working clock signal to produce a third working clock signal. Finally, the third data register obtains the parallel data from the second register according to the third working clock signal.

Abstract: A method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same, are provided. The method for converting coded parallel data into serial data and transmitting the serial data in a serial communication system includes determining a position, in which an information bit of the coded parallel data is found first, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed; and serially transmitting the information bit found first and at least one bit following the information bit found first as compressed serial data until the determined position is reached.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.

Abstract: Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Some interface signals are selected from among signals of a plurality of different parallel interfaces, then being multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface-signal selector IFS, and a transfer programmer TP for issuing a control signal to instruct the selection from among the parallel interfaces. The transfer programmer TP implements the multiplexing of the selected interface signals in such a manner that the specification of the parallel interfaces is satisfied. Also, the transfer programmer TP changes, as occasion requires, the control signal to instruct which interfaces to select. This change allows the interface signals to be multiplexed onto the serial connection while dynamically changing the interface signals to be multiplexed.

Abstract: A first data path is coupled between a data input and a data output of a circuit. A second data path is coupled between the data input and the data output. The first data path includes a parallelization circuit coupled to the data input to receive a serial data signal and configured to generate a parallelized data signal from the serial data signal, a first sampling circuit coupled to the parallelization circuit and configured to sample the parallelized data signal, and a serialization circuit coupled to the first sampling circuit and configured to serialize the sampled parallelized data signal. The second data path includes a second sampling circuit coupled to the data input and configured to sample the serial data signal. A selection circuit is configured to select between the first data path and the second data path.

Abstract: A data converter includes multiple analog to digital converters (ADCs) and uses a reduced number of data ports at the digital interface for transferring signal samples. The bits of the signal samples generated in parallel by the ADCs are multiplexed into fewer data streams than the number of ADCs. The data ports transfer the data streams at a higher data transfer rate than the bit rate of the samples output from the ADCs. Unused data ports are powered down, decreasing power consumption and system complexity. A host device receives the data streams using fewer input data ports and demultiplexes the received data streams to reproduce the signal samples. Efficient data transfer to a data converter including multiple digital to analog converters (DACs), from a source device generating multiple digital signals can also use fewer data ports having higher data transfer rates.

Abstract: A data transmission circuit that converts parallel data signals into a serial data signal to transmit the serial data signal includes a clock generation circuit, an output circuit, and a shift register circuit for securely conducting data communication among internal elements regardless of the improvement in data transfer rate, the increase in manufacturing variance, the variation in power supply voltage and temperature, and the like. The clock generation circuit generates a clock signal. The output circuit is provided to output the serial data signal. The shift register circuit acquires the parallel data signals and sequentially transfers the acquired parallel data signals to the output circuit in a bitwise manner with the use of a shift operation synchronized with the clock signal from the clock generation circuit.

Abstract: A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Abstract: A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m?n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.

Abstract: A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

Abstract: Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.

Abstract: A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.

Abstract: An interface control circuit including a physical layer receiver, a lane receiver, a bridge circuit, a transmitter command encoder, a lane transmitter and a physical layer transmitter is provided. The physical layer receiver receives and converts serial data into parallel data, and determines to transmit the parallel data in a high speed transmission mode or a low power transmission mode according to the serial data. The lane receiver receives and decodes the parallel data. The bridge circuit outputs the decoded parallel data. If the serial data includes a read command, the transmitter command encoder encodes the parallel data. The lane transmitter receives target parallel data from the bridge circuit, and transmits the target parallel data in the low power transmission mode according to the encoded parallel data. The physical layer transmitter converts the target parallel data into target serial data and outputs the target serial data.

Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.

Abstract: An RFIC controller configured for executing multiple tasks. A serial interface is included having a serial bus for receiving a data stream having control bits and data bits. One or more registers are coupled to the serial bus for storing the control bits and data bits as they are received. Control circuitry is also included. The data stream is formatted such that the control bits are received before the data bits, the control bits specifying an operation. The control circuitry is configured to examine the control bits as they are received to determine the operation specified by the control bits before the data bits are received. A task corresponding to the operation specified by the control bits is then initiated before the data bits are received.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A device for parallel-serial conversion of several evaluation parameters determined respectively by a detector from detected signal values. The device includes a primary buffer memory for the synchronized buffering of each determined evaluation parameter, a synchronization unit for the generation of a synchronization signal for the synchronized buffering and a unit for the serial readout of the evaluation parameters stored in a synchronized manner in the primary buffer memory. A synchronization signal generated by the synchronization unit is derived from a release signal which provides the highest data rate of all the release signals associated respectively with the determined evaluation parameters.

Abstract: The semiconductor integrated circuit includes: a plurality of macro cells; and a serial-parallel conversion circuit for converting a serial signal inputted from outside to generate parallel selection control signals during testing, or an A/D conversion circuit for converting an analog signal inputted from outside to generate digital selection control signals during testing. One or more among, the plurality of macro cells are selected based on the selection control signals and brought to a test operation state.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operable in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: Provided are a multiplexer for controlling a data output sequence and a parallel-to-serial converter using the multiplexer. The multiplexer is configured to simply control the output sequence of input data in accordance with a value of a selection signal. The parallel-to-serial converter with the multiplexer can easily control an output bit sequence of serial data without altering an interconnection structure of parallel data signal lines.

Abstract: In accordance with the teachings described herein, a digital video cable driver is provided that includes an input stage, an output stage and an amplification stage. The input stage converts a pair of differential input voltages into a control current. The output stage generates a digital output voltage for transmission over a cable. The amplification stage responds to the control current to control a voltage swing of the digital output voltage as a function of the control current. The amplification stage may include a transistor circuit that varies the digital output voltage in proportion to variations in the control current to cause the voltage swing, wherein the control current causes one or more transistors in the transistor circuit to remain in a saturated state during operation of the digital video cable driver.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes). A configurable SerDes can be designed to operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: A serial data receiving circuit and a serial data receiving method are provided which are capable of performing interconversion on bit sequences of data bit groups, between LSB first and MSB first, in serial data transmitted serially in successive data bit groups. Conversion parts C1 through C8 receive 8 different bit strings BS1 through BS8 having a 32-bit bit length and in which a start position of a head bit is shifted by one bit at a time. Conversion parts C1 through C8 perform a conversion operation to reverse a bit sequence of the bit strings BS1 through BS8 every 8 bits starting from a head bit. Coincidence detection circuits D1 through D8 perform coincidence detection on the bit strings BS1 through BS8 to detect coincidence with a synchronization pattern RS. A selector circuit 60 extracts any of upper bit strings HCBS1 through HCBS8 from the bit strings on which coincidence detection was performed, and outputs the result as detection data FD.

Abstract: A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

Abstract: A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.

Abstract: A data conversion unit includes a first input/output unit, a second input/output unit, an encoder, a decoder, a random number generator for generating random number data, and a control unit which selects a first, second and third setting function. The first setting function sets the data conversion unit to input data from the first input/output unit, encode data by the encoder, and output the encoded data from the second input/output unit. The second setting function sets the data conversion unit to input data from the first input/output unit, replace the data with the random number data generated by the random number generator, and output the random number data from the second input/output unit. The third setting function sets the data conversion unit to input encoded data from the second input/output unit, decode the encoded data by the decoder, and output the decoded data from the first input/output unit.

Abstract: A semiconductor system has a SerDes circuit for receiving serial data, and a reference SerDes circuit for receiving clock signals running in parallel. The SerDes circuit performs serial to parallel conversion of the serial data captured by the recovery clock whose phase is controlled by utilizing the phase control signal P_CS generated by the reference SerDes circuit.

Abstract: A high speed transmission system includes at least one transmitter; a buffer circuit for assembling into a data packet in parallel a number of sample conversion words from said transmitter; a marker circuit for adding a marker word to said data packet for framing said data packet; and a serializer circuit for serializing said data packet either before or after said marker word is added, with an embedded clock for transmission.

Abstract: Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream.

Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver.

Abstract: A transmit path in a physical layer device comprises a first transmit encoding device that has N outputs, that receives a first data stream at a first data rate and that performs a first type of encoding on the first data stream. A second transmit encoding device has an output, receives a second data stream at a second data rate and performs a second type of encoding on the second data stream. The first data rate is N times the second data rate. An output selector has a first set of N inputs that communicates with the N outputs of the first transmit encoding device, a second set of N inputs that communicate with the output of the second transmit encoding device and N outputs. The output selector selectively connects one of the first and second sets of N inputs to the N outputs.

Abstract: A method of transmitting digital data, with which parallel data, which are constituted with first, second and third data sequences each constituting 12-bit word sequence and multiplexed in parallel with one another to form a digital video signal, are first converted into first and second word sequence data, each of which are constituted with 10-bit words arranged in sequence. Each of the 10-bit words arranged in sequence to form each of the first and second word sequence data does not correspond to a predetermined forbidden code, and consequently, each of the first and second word sequence data do not contain specific 10 bits corresponding to the predetermined forbidden code and therefore can be easily and appropriately reconverted into the original parallel data forming the digital video signal. Then, the first and second word sequence data thus obtained are subjected to P/S conversion to be converted into the first and second serial data, respectively, and the first and second serial data are transmitted.

Abstract: Systems and methods provide synchronization techniques across a number of communication channels. For example, in accordance with an embodiment of the present invention, a synchronization scheme is disclosed for synchronizing across multiple data transmission channels, with each transmission channel multiplexing parallel data into serial data.

Abstract: A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing alignment of the data bit and the timing signal. No clock is used. This allows the deserialzer/receiver to reliably receive the data bit. Each illustrative delay circuit is configured to trigger the next register/delay circuit to output the next sequential bit and its timing signal.

Abstract: Disclosed is a serial-to-parallel conversion circuit that detects phase difference between a timing of receiving serial receive data and reconstituting parallel data for each symbol and a timing of outputting the reconstituted parallel data to an inside of an LSI, and outputs the detected phase difference as delay time information.

Abstract: A serializer including a pull-up unit configured to pull up an output node, and a plurality of data select units configured to receive a plurality of input data signals. Each data select unit includes a pull-up device configured to pull up the output node in response to a corresponding input data signal, and a pull-down device configured to pull down the output node in response to the corresponding input data signal.

Abstract: A transmission device includes: parallel/serial conversion units; a clock signal transmission unit; a known-parallel data generation unit for inputting known-parallel data to the parallel/serial conversion units; a clock shift unit for sequentially shifting a clock signal, which is outputted from the clock signal transmission unit, by 1 UI of a data signal; sampling units for sampling data signals obtained by serializing the known-parallel data, in accordance with the clock signal shifted by 1 UI; and a diagnostic processing unit for making a diagnosis as to whether the transmission device is operating normally by comparing sampling results with the known-parallel data, and outputting a result of the diagnosis.

Abstract: A parallel-to-serial converter selects variable-m1-bit parallel dummy data from m-bit parallel dummy data (0?m1?m) together with a n-bit parallel data signal synchronized with a first clock signal having a first frequency, and converts the selected (n+m1)-bit parallel data into a (n+m1)-bit serial data signal synchronized with a second clock signal having a frequency (n+m1) times the first frequency. A serial-to-parallel converter circuit selects n-bit serial data from the (n+m1) parallel data signal and converts the n-bit serial data into a n-bit parallel data signal synchronized with the first clock signal.

Abstract: A serial data communication unit includes a parallel-serial converter for separating n-bit parallel data containing decision data into plural groups, and converting the parallel data into serial data every group to output, a serial-parallel converter for reconverting the serial data fed from the parallel-serial converter every group into the n-bit parallel data to output, and a deciding circuit into which data located in bit positions corresponding to the decision data out of the parallel data from the serial-parallel converter is input.

Abstract: A multiplexer of a transmission section generates a clock signal by multiplying a reference clock signal of a digital image signal by a predetermined number ‘K’. A parallel digital image signal is converted into a serial digital signal on the basis of the clock signal, and the serial digital signal is converted into an optical signal in an optical transmission section for transmitting. A demultiplexer extracts a reception clock signal from a serial digital reception signal which is converted into an electric signal in an optical reception section of a reception section, the serial digital reception signal is converted into a parallel signal and a signal corresponding to the parallel digital image signal on the basis of the reception clock signal, and a clock signal corresponding to the reference clock signal is recovered by multiplying the reception clock signal by ‘1/K’.

Abstract: A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I1 and I2 to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.

Abstract: Disclosed is a method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same. The method for converting coded parallel data into serial data and transmitting the serial data in a serial communication system includes determining a position, in which an information bit of the coded parallel data is found first, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed; and serially transmitting the information bit found first and at least one bit following the information bit found first as compressed serial data until the determined position is reached.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.

Abstract: A method of serializing parallel output from an analog-to-digital converter includes receiving a parallel output from an analog-to-digital converter; serializing the parallel output; and encoding the serialized output such that it is DC balanced. A system for serializing and DC balancing an analog-to-digital converter output includes an analog-to-digital converter that outputs digital data over a parallel bus; a serializer configured to receive said digital data from said parallel bus, said serializer serializing said digital data into serial output; and a means for encoding the serial output such that it is DC balanced.

Abstract: A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.