Abstract: An optical path is configured to propagate an input optical signal. A plurality of electrodes are configured to produce a plurality of discrete phase shifts on the optical signal. An output optical signal is phase-shifted with respect to the input optical signal by a sum of the plurality of discrete phase shifts.

Abstract: The inventive data conversion device is typically embodied as a modular unit including a PCBA and a frame that houses it. The PCBA includes a PCB and electronic components mounted thereon including a computer and one or more conventional conversion devices, viz., at least one conventional synchro-to-digital converter and/or at least one conventional digital-to-synchro converter. According to typical inventive synchro-to-digital conversion, analog synchro data (received from a synchro) is converted by the synchro-to-digital converter(s) to lower-level-format parallel-binary-angle digital synchro data, which in turn is converted by the computer to higher-level-format digital synchro data.

Abstract: A control device for a travel motor mounted to a vehicle has a resolver which works as a rotation-angle sensor. The control device has a RDC which calculates a rotation-angle output value ? based on rotation detection signals Sa, Sb transferred from the resolver. The control device supplies electric power to the travel motor based on the rotation angle output value ?. The RDC calculates “sin(???)” as an error deviation ? based on the signals Sa and Sb and the rotation-angle output value ?. The RDC calculates an angular acceleration by multiplying the error deviation ? with a gain (=Ka·Kb), and integrates the angular acceleration two times in order to obtain a next rotation-angle output value. A gain control part of the RDC decreases the gain when the judgment means judges that the travel motor rotates at a constant rotation speed.

Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with motion encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. Problems with noise spikes common to zero-hysteresis comparators typically employed in interpolation circuits are eliminated, as are problems with time delays differing between comparators that do feature hysteresis. The disclosed interpolation circuits may be implemented using CMOS processes without undue effort.

Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with optical encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.

Abstract: Land-based vehicle including an arrangement for monitoring objects in or about a vehicle includes a source from which modulated illumination is emitted into an area in or about the vehicle, a receiver arranged to receive illumination reflected from an object in the path of the modulated illumination, and circuitry coupled to the receiver and the source and arranged to compare a phase of the modulated illumination with a phase of the reflected radiation at a common frequency to determine whether there is a phase difference between the modulated illumination and the reflected illumination. The phase difference is a measure of a property of the object, such as the distance between the object and the source/receiver, which can be co-located. Otherwise, if the source and receiver and not co-located or substantially co-located, the distance is a measure of the distance of travel of the illumination.

Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

Abstract: A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal.

Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with optical encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.

Abstract: A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal.

Abstract: A method, system, and apparatus of a balanced rotator conversion of serialized data are disclosed. In one embodiment, a method to convert serialized data includes acquiring a rotator module output, and generating a balancing signal with a reference module, which operates with a reference frequency. The method further includes processing the rotator module output and the balancing signal in an interpolation module to generate a balanced rotator output. The method may include a rotator module output that is generated by an analog phase rotator when a control voltage is received by the analog phase rotator. The reference module may include an other analog phase rotator to generate a balancing signal. The interpolation module may interpolate the balancing signal and the rotator module output to modulate a phase of the balanced rotator output. The balanced rotator output may include an orthogonal output.

Abstract: A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase.

Abstract: A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

Abstract: A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.

Abstract: An encoder signal processing device comprising an A/D converter converting a periodic analog signal, a memory storing position detection error information and a computing unit including a position data calculator which calculates position data from the digital data and an error correcting section which corrects the position data based on the position detection error information. The memory includes a first memory encoding position error data which is included in the position data by the use of the computing unit and storing a correction coefficient. A second memory decoding the position error data on the basis of the correction coefficient by the use of the computing unit and storing correction data for correcting the position data and error-containing position data generated on the basis of the encoded position error data.

Abstract: A device for converting position data to Hall code data includes a data input for providing the position data, a data output for providing the Hall code data, a first adder circuit operative to provide a sum of a first predetermined number and a value provided by the data input, and a memory circuit for storing a plurality of data. A most significant bit of the data input is provided to a first storage location of the memory circuit, and a most significant bit of the first adder circuit's sum is provided to a second storage location of the memory circuit. An output of the memory circuit is operatively coupled to the data output.

Abstract: A method for cadence detection in a sequence of video fields is based on at least a search for cadence patterns in a sequence of bits representative of the motion in at least a part of the field from one field to another in the field sequence. The signaling of field skip and/or field repeat commands as applied to the fields in the field sequence is considered during the cadence detection operation so as to field skips and repeats.

Abstract: A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal.

Abstract: Since an abnormality is judged by executing a square calculating process with respect to sin ? and cos ? for detecting an abnormality in an angular resolver, a processing time is elongated, and a burden to a CPU is great. Since the invention prepares a map which can judge whether the combination of sin ? and cos ? is normal or abnormal, and judges by mapping the combination of the detected sin ? and cos ?, a process can be easily executed, a processing speed is high, and a burden to the CPU can be reduced. Further, an assist can be maintained by controlling a motor by a rectangular wave current by detecting a rotation angle signal at low resolution level, such as Hall sensors arranged around the motor.

Abstract: Two-phase sinusoidal signals QA, QB output from an encoder are interpolated by sample-and-hold (S/H) circuits and A/D conversion (ADC) circuits, and data D is output in accordance with a data request signal RQ from exterior. For this interpolation of encoder output, a direction discrimination up/down counter is arranged near a two-phase square-wave uniform pulse generating circuit, and the data D is latched and output using a signal which is obtained by delaying the data request signal RQ. This can reduce synchronization errors between the data request signal RQ from exterior and the interpolated data, with an improvement in dynamic precision.

Abstract: An interpolation apparatus in an encoder includes an analog-to-digital converter for digitizing a sine wave signal and a cosine wave signal, respectively. An amplitude level detecting circuit detects each amplitude level of the digitized sine wave signal and cosine wave signal. A computing circuit multiplies the amplitude level of one of the signal by an interpolation position parameter according to a tangent value at an interpolation position. A comparing circuit compares an output from the computing circuit to an output from the amplitude level detecting circuit. The comparison is made at every the interpolation position. A region detecting circuit identifies a region sectionalized by the interpolation positions adjacent to each other based on an output from the comparing circuit corresponding to each the interpolation position. The phase angle of the sine wave signal and the cosine wave signal exists in the region.

Abstract: A duo-binary encoder performs a parallel processing and an optical duo-binary transmission apparatus using the encoder to enhance transmission capability. The duo-binary encoder has a judgment unit for judging whether an odd number or even number of ‘0’s exists in data input signals of N channels, a toggle unit for toggling an output signal of the judgment unit when a number of ‘0’s is even, an intermediate signal generation unit for determining whether phases of other channels are shifted or not, according to an data input signal on the basis of a predetermined channel of the N channels. A phase division unit divides data into a first data group having non-shifted phases and a second group of data that require a phase shift, according to an output signal of the intermediate signal generation unit and the data input signal. The divided first and second data groups are then output.

Abstract: A method and apparatus for detecting the position of a movable device are provided, in which an acceleration signal of the movable device is obtained and the acceleration signal is converted to a digital signal using an acceleration sensor; a high level time of the digital signal is counted, based on a predetermined frequency; the absolute displacement of the movable device is calculated by integrating the counted high level time of the digital signal twice; and the absolute displacement is converted to a binary gray code and the binary gray code is output.

Abstract: An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such that a plurality of bits can be determined during a single trial step; and during a second phase of the analog to digital conversion the conversion engines work independently; and the controller receives the outputs of at least one of the conversion engines and processes them to provide an output word.

Abstract: An apparatus and method for determining an angular position of a shaft are disclosed, which comprise resolving an excitation signal at an excitation frequency into at least two orthogonal signals, converting the orthogonal signals to a digital estimate, for each of the orthogonal signals, and evaluating an amplitude and a polarity of the orthogonal signals to determine the angular position. The process of converting the orthogonal signals comprises comparing the orthogonal signal to an analog feedback signal to generate a comparison result and incrementally adjusting the digital estimate in response to sampling the comparison result at an estimation frequency. The converting process also includes converting the digital estimate to the analog feedback signal, collecting a digital estimate history at a sample frequency that is a binary multiple of the excitation frequency, and analyzing the digital estimate history to determine the amplitude and the polarity substantially near the excitation frequency.

Abstract: A precoder for an optical duo-binary transmission apparatus disposing the precoder before a time division multiplexer includes a judgment unit for judging whether an odd number or even number of ‘1’s exist in data input signals of N channels inputted at an nth time of channel input. Further included in the precoder is a toggle unit for toggling an output signal of the judgment unit when the judgment is odd, and for determining an output value for one of the channels. The precoder also has an output unit for determining output values of other channels according to a respective data input signal and a predetermined channel from among the N channels.

Abstract: Structures and methods are provided for generating a digital display signal from an analog signal that is limited to 2N discrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. These structures and methods accurately synchronize digitizers to the analog signal and they follow from a recognition that enhanced digitizer resolution will generate code patterns which easily distinguish between correct and incorrect sampling of the analog signals. Accordingly, the digitizers quantize the analog samples into an M-bit digital display signal wherein M exceeds N.

Abstract: A resolver use angle detection IC subjected to a phase lock operation so as to follow not an angle ?(t) for detection, but a phase angle ?ot±?(t) having an offset of a frequency ?ot in the phase lock units. For this reason, when the excitation frequency ?ot is set sufficiently high with respect to the frequency of the angle ?(t), the phase angle ?ot±? to be followed in the phase lock units will not become zero. For this reason, an angle having a high precision can be found in real time regardless of the configuration not including the conventional apparatus in which the configuration is complex and the power consumption is large like a bipolar VCO and an up/down type counter.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: A transcoder reduces excess requantization error in quantization of spectral data. The transcoder phase shifts data decompressed by a decompressor. The phase shifting causes a change to corresponding spectral data produced in later transform coding of the decompressed data. When the spectral data is then quantized to reduce bitrate, the earlier phase shifting reduces excess requantization error. After transcoding, a second decompressor can compensate for the phase shifting by, for example, reverse shifting by the amount of the phase shift. Instead of phase shifting, the transcoder can reduce excess requantization error by, for example, adding random noise to the decompressed data or changing transform block sizes.

Abstract: The present invention provides a device and a method for enhancing the resolution of the digital signal of a digital encoder. The device comprises a digital encoder which outputs a fundamental position signal. Beside, the device comprises a selected integral circuit which receives the fundamental position signal to produce an integral signal according to a predetermined way, a reset circuit which resets the select integral circuit according to the fundamental position signal, a level shift and gain circuit which transforms and amplifies the level of the integral signal to produce a processing signal, and an analog-digital converter which receives the processing signal to produce an expanding position signal. In the device, the resolution of the expanding position signal is higher than the resolution of the fundamental position signal, so that it enhances the resolution of the digital signal of the digital encoder.

Abstract: A low cost x-y digitising system is described for use in consumer electronic devices, such as portable digital assistants, mobile telephones, web browsers and the like. The digitizer includes a resonant stylus, an excitation winding for energising the resonant stylus and a set of sensor windings for sensing the signal generated by the stylus, from which the x-y position of the stylus is determined. The excitation signals applied to the excitation winding are designed to reduce the power drawn from the power supply which makes the digitising system particularly suited to battery operation.

Abstract: The invention relates to a device and a method for determining an electrical starting rotor angle of an electromotor. According to the invention, the electromotor (10) is subjected to an approximately sinusoidal voltage and the corresponding current path (i) that is established is then detected. The electromotor (10) is again subjected to an approximately sinusoidal voltage and again, the corresponding current path (i) is detected. A ratio of a measure of the fundamental wave (I1) and the measure of the first harmonic wave (I2) is then determined from the current paths (i) as a measure of the electrical starting rotor angle (?).

Abstract: Processing circuitry is provided for processing signals received from, for example, sense coils forming part of a position encoder used to encode the relative positions of two relatively movable members. The position encoder is such that each of the plurality of signals from the sense coils varies sinusoidally with the relative position of the members but out of phase with respect to each other. The processing circuitry comprises mixers for multiplying each of the received signals with one of a corresponding plurality of periodic time varying signals, each having the same predetermined period and a different predetermined phase, and an adder for adding the signals from the mixers. The phase of the mixing signals are chosen so that the output signals from the adder contains a single periodic component having the predetermined period whose phase varies with the relative position of the two members.

Abstract: The invention relates to a method for automatically generating several electrical pulses using numeric default values, in particular for simulating an incremental encoder for a sequential, digital counting of linear or angular displacement values using said pulses. The method incorporates a value generator that outputs the default values repeatedly within each first cycle time, calculation and control means that detect the default values in a cyclic manner and a pulse switching interface that has one or more outputs for the pulses.

Abstract: A method of digitizing first and second signals in imperfect quadrature for obtaining characteristic parameters of the first signal comprises providing a first signal, the first signal comprising an inphase quasi-sinusoidal analog signal. The method comprises providing a second signal, the second signal comprising a quadrature signal. The method comprises digitizing the first signal at a sampling rate, thereby generating a first plurality of sets of digital signal waveform samples and digitizing the second signal at the sampling rate, thereby generating a second plurality of sets of digital signal waveform samples. The method comprises digitally processing successive first and second sets of digital signal waveform samples to generate continually updated digital characteristic parameters representing a characteristic behavior of the first signal.

Abstract: An optical duo-binary transmission apparatus using an optical duo-binary transmission method is disclosed. The apparatus includes a duo-binary encoder that performs parallel processing. The duo-binary encoder includes a level change detection unit for detecting that levels of data input signals of N channels input at an nth input of channels change from 0 to 1, or from 1 to 0; a judgment unit for judging whether a number of level changes detected by the level change detection unit is odd or even; and a toggle unit for toggling an output signal of the judgment unit when the number of level change is odd.

Abstract: A transmitter circuit (10) includes a phase shifter (20) that receives phase shift compensation and timing data (40), and an amplifier (30) that receives a control signal (70) to initiate an efficiency enhancement technique. The phase shifter (20) receives the phase shift compensation and timing data (40), and the amplifier (30) receives the control signal (70) at a pre-defined relative time such that the compensation phase shift by the phase shifter (20) compensates for a pre-determined phase change in the amplifier (30) to produce an RF output signal (80) with a reduced predicted phase change.

Abstract: An analog-to-digital metering circuit includes a first programmable gain amplifier to amplify a first voltage signal from a first channel before being received by a first analog-to-digital converter that converts the amplified first voltage signal to a first digital signal. A second programmable gain amplifier amplifies a second voltage signal from a second channel and feds the amplified signal to a second analog-to-digital converter that converts the amplified second voltage signal to a second digital signal. A first lowpass filter circuit receives the first and second digital signals, to generate therefrom, a multi-bit analog-to-digital value. A direct digital synthesizer generates a digital signal representing a predetermined waveform that is fed to a digital-to-analog converter. The second voltage signal and the digital signal representing the predetermined waveform are multiplied together to generate a digital value.

Abstract: A method and apparatus to inexpensively and efficiently process audio and speech signals. A method for processing a signal having at least one region of interest is provided. The method begins by dividing the signal into a plurality of sub-band signals, wherein a selected sub-band signal includes the region of interest. The selected sub-band is processed by a phase vocoder to produce a vocoder output signal. Next, at least a portion of the subbands are time-aligned with the vocoder output signal. Finally, the aligned sub-band signals and the vocoder output signal are combined to form an output signal.

Abstract: Pulse width modulation systems and methods are described. In one aspect, a pulse width modulation system includes a register and a code word generator. The code word generator has an input for receiving a specified output frequency and a specified duty cycle and is operable to generate code words of different lengths. The code word generator is operable to generate a base code word having a length set to achieve the specified output frequency and having a thermometer code value set in accordance with the specified duty cycle. The code word generator is further operable to load the register with a code word pattern including a sequence of one or more copies of the base code word.

Abstract: An analog/digital converter includes a first transfer circuit which receives an input voltage and outputs an output clock signal having a phase delay that is dependent on the input voltage, a second transfer circuit which receives a reference voltage and an input clock signal and outputs a reference clock signal having a phase delay that is dependent on the reference voltage, and a comparator which compares the output clock signal and the reference clock signal and outputs a digitally-coded output signal that is based on the result of the phase comparison of the output clock signal and the reference clock signal.

Abstract: Processing circuitry is provided for processing signals received from, for example, sense coils forming part of a position encoder used to encode the relative positions of two relatively moveable members. The position encoder is such that each of the plurality of signals from the sense coils varies sinusoidally with the relative position of the members but out of phase with respect to each other. The processing circuitry comprises mixers for multiplying each of the received signals with one of a corresponding plurality of periodic time varying signals, each having the same predetermined period and a different predetermined phase, and an adder for adding the signals from the mixers. The phase of the mixing signals are chosen so that the output signals from the adder contains a single periodic component having the predetermined period whose phase varies with the relative position of the two members.

Abstract: A adaptive deciding method and apparatus for frequency shift key signals are provided to sample the demodulated FSK signal, input the values of the sample points in sequence to a sample group, and compare at least a pair of the sample points, thereby finding out the central point of the FSK signal to improve decoding due to signal attenuation.

Abstract: An arrangement for interpolating signals interpolates an analog measured signal which is dependant on a measured variable and which is fed to a voltage divider whose pickoff signals are fed to comparators from whose output signals the interpolated measured variable is determined. In order to reduce cost, the pickoff signals are fed by switches to comparators whose number is smaller than that of the pickoff signals. In this process the switches must connect the pickoff signals to the comparators consistently.

Abstract: The present invention comprises a centrally synchronized distributed time-space-time switch fabric wherein connection memory page (CMP) selection information is communicated to remote devices without having to add any extra hardware to the system. The central processor only needs to communicate to the space switch device, and by writing to certain registers in the space switch the processor can control the CMP selection in each of the time switch devices. By providing the page selection information over the same signals that transfer data, these page selection signals do not have to be routed externally or controlled by the distributed software.

Abstract: An information recording medium which ensures high reliability and favorable overwrite cycle-ability is provided, even when an interface layer is not provided between a recording layer and a dielectric layer. The recording layer 4 and the dielectric layers 2 and 6 are formed on the surface of the substrate 1. In the recording layer 4, a phase change is generated between a crystal phase and an amorphous phase by irradiation of light or application of an electric energy. The dielectric layers 2 and 6 are Zr/Hf—Cr—O-based material layers comprising at least one of Zr and Hf, Cr and O, preferably consisting essentially of material expressed, for example, with the formula (MO2)N(Cr2O3)100−N (mol %) wherein M is either or both of Zr and Hf, and 20≦N≦80.

Abstract: A device for generating synchronous numeric signals, including a reference generating device supplying a reference signal and a first timing signal, both having a reference frequency; and a timed generating device supplying a synchronized signal having the reference frequency. The device further includes a synchronization stage generating a second timing signal having a first controlled frequency correlated to the reference frequency, and phase synchronization pulses having the first frequency and a preset delay programmable with respect to the first timing signal.

Abstract: A multiple receiver approach is disclosed for a pulse decoding communication system, which can enhance system robustness and increase information carrying capacity. Two or more receivers are used to produce groups of pulses from a received signal. In one embodiment, system robustness is enhanced by redundancy. In another embodiment, information capacity is increased by producing independent groups of pulses from one cycle of an analog waveform.