Abstract: An information recording medium which ensures high reliability and favorable overwrite cyclability is provided, even when an interface layer is not provided between a recording layer and a dielectric layer. The recording layer 4 and the dielectric layers 2 and 6 are formed on the surface of the substrate 1. In the recording layer 4, a phase change is generated between a crystal phase and an amorphous phase by irradiation of light or application of an electric energy. The dielectric layers 2 and 6 are Zr—Cr—O-based material layers comprising Zr, Cr and O, preferably consisting essentially of material expressed, for example, with the formula (ZrO2)M(Cr2O3)100-M (mol %) wherein 20≦M≦80.

Abstract: The present invention provides an automatic resolution changing method and circuit for use in a high-precision digital conversion of two-phase sinusoidal wave signals. The angular velocity (d&phgr;/dt) of the rotor obtained from the difference between these two-phase sinusoidal wave signals is integrated by a counter. Subsequently, digital conversion of the rotation angle (&thgr;) of the rotor with respect to the stator is performed, and a result of the digital conversion is outputted. At this time, in the case where the angular velocity (d&phgr;/dt) is equal to or higher than a first percentage of the follow-up speed at the current resolution of the counter, the resolution of the counter is reduced. Further, in the case where the angular velocity (d&phgr;/dt) is equal to or lower than a second percentage of the follow-up speed at the current resolution of the counter, the resolution of the counter is increased.

Abstract: A clock synchronization device divides a digital-to-analog converting unit into main and sub digital-to-analog converters and operates both main and sub digital-to-analog converting units if an output voltage of the digital-to-analog converting unit is lower than a reference voltage based on a voltage obtained when the delay rate of a variable delay line VDL is sharply increased or operates only the main digital-to-analog converting unit if the output voltage of the digital-to-analog converting unit is higher than the reference voltage. As a result, the clock synchronization device can make the output voltage of the digital-to-analog converting unit be linear with respect to a digital code, thereby improving a jitter property in a band with a very large gain of the variable delay line.

Abstract: A system and method are disclosed for improving resolution of an encoder or other position sensing device that provides one or more signals indicative of relative movement between two bodies. The signals are employed to determine an operating mode, which varies as a function of relative speed between the two bodies. In one operating mode, the system determines an indication of position by interpolating between position information of a table. Position also can be predicted in this operating mode, which can be used to update the position information. The table is populated with position information based on a sample of the signals from the position sensing device, such as to provide the position information for the table. In another operating mode, an indication of position is determined as a function of velocity and time.

Abstract: A system to perform angle quantization includes a log ROM lookup table to provide a log of a real input (10) of a signal and a log of an imaginary input (20) of the signal. A subtractor (100) computes the difference between the log of the real input and the log of the imaginary input to provide a difference (102) equivalent to a division of the inputs, and a ROM lookup table (110) determines a phase from the difference.

Abstract: Processing circuitry is provided for processing signals received from, for example, sense coils forming part of a position encoder used to encode the relative positions of two relatively moveable members. The position encoder is such that each of the plurality of signals from the sense coils varies sinusoidally with the relative position of the members but out of phase with respect to each other. The processing circuitry comprises mixers for multiplying each of the received signals with one of a corresponding plurality of periodic time varying signals, each having the same predetermined period and a different predetermined phase, and an adder for adding the signals from the mixers. The phase of the mixing signals are chosen so that the output signals from the adder contains a single periodic component having the predetermined period whose phase varies with the relative position of the two members.

Abstract: A phase-synchronizing circuit includes a phase error detection circuit detecting a phase-error in a given clock signal and producing an output indicative of the phase-error as a first phase-error signal, a phase-error creating circuit creating a second phase-error signal determined so as to minimize a time for establishing a phase-synchronization for the clock signal, and a selection circuit selectively supplying the first or second phase-error signal selectively to a phase control circuit.

Abstract: A method of presenting audio information where changes in amplitude and changes in frequency in two channels (stereo) have the additional parameter of phase information added to re-create the feeling of a live performance. Also, all three parameters are converted into duty cycle modulation of a high frequency digital pulse. Conventional loudspeakers and the brain decode the signal to provide audio signals that contain more information than simply frequency and amplitude changes as a function of time.

Abstract: According to the invention, oscillating signals are generated from analog signals by providing an analog signal having a variable slope or amplitude to a circuit with a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first and a second stable operating region. The unstable operating region contains a first and a second reference point. The circuit is capable of producing an oscillating signal having a variable duty cycle, the duty cycle increasing as the variable operating point is positioned closer to the first reference point, the duty cycle decreasing as the variable operating point is positioned closer to the second reference point. The variable operating point is positioned substantially within the unstable region to produce the oscillating signal. The positioning of the operating point relative to the first and the second reference points is a function of the variable slope or amplitude of the analog signal.

Abstract: A method and apparatus for generating pulses that includes a circuit having a dynamical transfer function is disclosed. The circuitry exhibits oscillatory behavior when its operating point is forced to an unstable region of the transfer function by means of manipulating the transfer function. In an embodiment, a voltage source signal is used to manipulate the transfer function of the circuit. By manipulating the transfer function, the operating points can be dynamically set in the stable or the unstable region.

Abstract: A decoder for generating output pulses or oscillations in response to input analog waveforms includes a circuit having a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. In one embodiment, the circuit is characterized by having a resistive input impedance. The analog waveform forces the operating point of the circuit into its unstable and stable regions to produce oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: A digital display unit adjusting the phase of a sampling clock based on the examination of a display data signal contained in a received analog display signal. The phase may be adjusted by determining a boundary between display data portions representing successive pixel data elements. As the boundaries provide the timing information related to the source clock, the phase of the sampling clock can be adjusted when ever the boundaries can be determined accurately. The phase of the sampling clock can be adjusted potentially every sampling clock cycle if the boundaries can be determined. The area for examination can be minimized by first determining an expected boundary based on synchronization signal accompanying the analog display data, and examining only a small area surrounding the expected boundary.

Abstract: A system and method of digitizing characteristic parameters of a quasi-sinusoidal analog signal of unknown magnitude, frequency and phase-offset, includes digitizing the analog signal at a first sampling rate, thereby generating a plurality of sets of digital signal waveform samples. Successive sets of the digital signal waveform samples are digitally processed to generate continually updated digital characteristic parameters representing a characteristic behavior of the quasi-sinusoidal analog signal.

Abstract: A method and apparatus that allows an analog waveform to carry multilevel of information is disclosed. This allows information capacity enhancement in pulse decoding communication system by concatenating several information regions in one cycle of analog waveform.

Abstract: A sampling device for sampling an input signal having intrinsic filter properties. The sampling device samples a continuous analog input signal according to a sampling signal. The sampling device includes a first sampling switch for sampling the input signal, in response to a sampling signal, to create a first set of samples. Furthermore, the sampling device incorporates a time delay device for time delaying the first set of samples. The sampling device also includes a phase shift device for phase shifting the input signal. The phase delayed input signal is then fed into a second sampling switch for sampling in response to the sampling signal to create a second set of samples. Further, a summer is incorporated to sum the first set of samples with the second set of samples to create the output samples.

Abstract: A method and apparatus are provided for generating output pulses or oscillations in response to input analog waveforms which involves exciting, with a known but arbitrary analog waveform, a circuit with a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. The analog waveform is characterized by having a first information region and a second information region. In response to sensing the first and second information regions, the operating point of the circuit is forced into its unstable and stable regions. This produces a sequence of oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: A magnetic encoder includes a magnetic drum having, on the outer peripheral surface thereof, magnetized portions spaced at equal pitches; a magnetic sensor unit opposed to the outer peripheral surface of the magnetic drum; magnetic sensors are provided in the magnetic sensor unit spaced at a distance smaller than one pitch of the magnetized portions; a calculation device for calculating two sets of vectorial signals, from detection-signal output levels of the magnetic sensors generated upon rotation of the magnetic drum or the magnetic sensor unit, using the following equations (1) and (2):

Abstract: A delta filter for use in a protective relay which includes an input circuit for receiving phasor signals representative of electrical signal quantities on the power line. A difference value, if any, is determined between the phasor signals at a present time and the phasor signals at a past point in time (delayed), the delay typically being one cycle. A first incremental output value is produced if there is a difference. When a power line disturbance is first noted by the recognition of a first incremental output value, the phasor signal value at the beginning of the disturbance is stored and then used as a reference value for comparison with subsequent present time phasor signals to determine continuing change in power system condition.

Abstract: A frequency estimator for estimating the frequency of a digital input signal (x(k)) includes a phase detection device (2) for determining the phase (&phgr;(k)) of the input signal (x(k)), a differentiator (3) for generating the phase difference (&phgr;diff1(k)) between adjacent samples of the phase (&phgr;(k), &phgr;(k-1)) and a filter (4) for averaging the phase difference (&phgr;diff(k)) and having a trapezoidal pulse response (hM(k)). The trapezoidal pulse response (hM(k)) is generated by superimposing a first triangular pulse response with a second triangular pulse response which is offset in time with respect to the first triangular pulse response.

Abstract: In an incremental encoder signal processing system there is provided a pair of sensor/encoders adapted to generate a quadrature pair of analog positioning signals that are converted to digital signals and processed to produce a digital position vector and a digital error signal. The digital position vector is processed in a novel logic analyzer to determine if sequential position vectors are indicative of an invalid change of state. The digital position vector signal is filtered in a novel low pass digital filter and the before-and-after signals at a plurality of states of the digital filter are analyzed and compared to detect conditions which permit the system to produce optimum rates of change in the servo-controller which controls a servo-drive at optimum speeds without creating error conditions and to detect error conditions in the sensor/encoder.

Abstract: The present invention provides an automatic resolution changing method and circuit for use in a high-precision digital conversion of two-phase sinusoidal wave signals. The angular velocity (d&phgr;/dt) of the rotor obtained from the difference between these two-phase sinusoidal wave signals is integrated by a counter. Subsequently, digital conversion of the rotation angle (&thgr;) of the rotor with respect to the stator is performed, and a result of the digital conversion is outputted. At this time, in the case where the angular velocity (d&phgr;/dt) is equal to or higher than a first percentage of the follow-up speed at the current resolution of the counter, the resolution of the counter is reduced. Further, in the case where the angular velocity (d&phgr;/dt) is equal to or lower than a second percentage of the follow-up speed at the current resolution of the counter, the resolution of the counter is increased.

Abstract: An absolute encoder that can generate an absolute value signal by performing simple operation processing.

Abstract: A method for the absolute determination of the position of two objects, which are movable in relation to each other over a defined measuring distance. The method includes scanning a first measuring graduation with a first graduation period so as to generate a first periodic scanning signal and scanning a second measuring graduation with a second graduation period so as to generate a second periodic scanning signal, wherein the second graduation period is finer than the first graduation period. Correcting the first scanning signal with respect to its ideal phase position, in that a phase correction value is applied to the first periodic scanning signal and determining the phase correction value for at least a partial section of the measuring distance, wherein the phase correction value is a mean value from a maximum and a minimum phase position deviation of an actual phase position from a setpoint phase position in the at least one partial section.

Abstract: A phase-calculation circuit includes a buffer, an approximation circuit, and an interpolator. The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator then calculates the absolute phase of the one sample with respect to a predetermined point of the signal using the relative phase of the sample within the signal portion and the values of the first and second samples. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock.

Abstract: Methods and apparatus are presented for precise measurement of mechanical position comprising combination of a plurality of coarse position signals to obtain substantial cancellation of spatial harmonics, generating a digital course position from a resolver system responsive to non-time harmonic signals, and providing precise incremental position signals from memory locations addressed by digital coarse position words.

Abstract: There is provided an R/D converter capable of realizing a high speed response. When a sine wave for excitation of a resolver is a positive (or negative) maximum value, an AD converter makes AD conversion of a sine-wave output and a cosine-wave output of the resolver and makes input to a DSP. The DSP calculates on the basis of the input data, and outputs an obtained digital value to a DA converter and the like. Since the DSP calculates a rotor shaft angle, as compared with prior art (R/D converter of a tracking system) which includes a close loop made up of a demodulator circuit, a voltage controlled oscillator, and the like, and carries out a kind of PLL control, it becomes possible to carry out rotor shaft angle calculation at higher speed, and the high speed response can be realized by this.

Abstract: An absolute-value encoder device for detecting a plurality of rotation quantities is disclosed. An A/B phase forming portion 610 forms an A-phase pulse signal and a B-phase pulse signal, based on light passing through a slit rotating together with a rotary shaft. One period of each of those pulse signals corresponds to one revolution of a rotary shaft. The A- and B-phase pulse signals are displaced in phase by 90° from each other. When an A/B-phase state detecting portion 640 detects a state change of each of those pulse signals, a clock forming portion 66 changes a frequency of a clock pulse signal to another frequency.

Abstract: A method and a device of sampling an analog signal (U(t)) by obtaining first sequences of discrete sample values (SI1(t), SQ1(t)) of In-phase (I) and Quadrature-phase (Q) components (Ui(t), UQ(t)) of the analog signall (U(t)) and second sequences of discrete sample values (SI2(t), SQ2(t)) of the I and Q components (Ui(t), UQ(t)), by sampling of the I and Q components with sampling sequences (&phgr;1(t), &phgr;2(t)) having equal sampling rate (&ohgr;s) and a mutual phase shift of 90° relative to their sampling rate period (T). The sample values of the I component of the first sequence (SI1(t)) and the sample values of the Q component of the second sequence (SQ2(t)) are summed (9) to form a third sequence of sample values S3(t). The sample values of the Q component of the first sequence (SQ1(t)) and the sample values of the I component of the second sequence SI2(t)) are summed (10) to form a fourth sequence of sample values (S4(t)).

Abstract: A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.

Abstract: A sampling device for sampling an input signal having intrinsic filter properties. The sampling device samples a continuous analog input signal according to a sampling signal. The sampling device includes a first sampling switch for sampling the input signal, in response to a sampling signal, to create a first set of samples. Furthermore, the sampling device incorporates a time delay device for time delaying the first set of samples. The sampling device also includes a phase shift device for phase shifting the input signal. The phase delayed input signal is then fed into a second sampling switch for sampling in response to the sampling signal to create a second set of samples. Further, a summer is incorporated to sum the first set of samples with the second set of samples to create the output samples.

Abstract: A method and apparatus are provided for generating output pulses or oscillations in response to input analog waveforms which involves exciting, with a known but arbitrary analog waveform, a circuit with a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. The analog waveform is characterized by having a first information region and a second information region. In response to sensing the first and second information regions, the operating point of the circuit is forced into its unstable and stable regions. This produces a sequence of oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: Disclosed is a system and method for modulating and demodulating a data signal. The system includes a number of configurable multi-rate signal processing modules coupled to a local interface. The system also includes a control module coupled to the local interface, the control module being adapted to shuttle a number of data symbols among the configurable multi-rate processing modules according to a predefined modulation or demodulation scheme. The system can advantageously be configured to perform one of multiple modulation or demodulation schemes.

Abstract: The loop latency compensated PLL filter comprising two additional feedback terms, a delayed phase compensation signal and a state compensation signal, that are provided as input of a PLL filter. Accordingly, the PLL filter input comprises two additional compensation input signals: the delayed phase compensation signal and the state compensation signal in addition to a phase estimated error output from a phase detector that is also coupled to the input of the PLL filter. Consequently, PLL filter thus is able to provide a latency compensated phase error control output that is fedback to control a phase mixer to generate a square waveform used to drive an A/D of the PLL in accordance with the principles of this invention. The loop latency compensated PLL of this invention thus minimizes the jitter of the PLL circuit, provides higher format efficiency, and also has reduced sensitivity to large bursty noises.

Abstract: A method for detecting a pulsed usable signal that particularly includes the highest frequencies and possesses a poor signal/noise ratio. First an analog, frequency-limited input signal that corresponds to the usable signal to be detected is formed from the analog input signal through analog filtering. This signal is then converted into a series of digital phase values through a phase/digital converter. First phase difference values are formed from these digital phase values by parallel or serial signal processing, and second phase difference valves are formed from these first difference values. Absolute values of the second difference values are then supplied via a digital low-pass filter to a comparator having hysteresis. There, an output signal that can be digitally utilized and corresponds to the pulsed usable signal is formed by predeterminable threshold values.

Abstract: The present invention is directed to a method and apparatus which utilizes a software-based digital signal processing circuit to generate a signal which is representative of the status of a movable component. A preferred embodiment of the apparatus of the present invention includes a synchro which is connected to a movable component. An analog reference excitation may be applied to the synchro, and the synchro generates analog synchro signals which bear a relationship to the status of the movable component. The analog synchro signals are converted to digital synchro signals by a plurality of analog-to-digital converters. A digital reference signal and the digital synchro signals are provided to a software-based digital signal processing circuit which preferably corrects constant and time-varying errors in the digital synchro signals and generates a status signal which is representative of the status of the movable component.

Abstract: An offset correcting circuit for an encoder capable of detecting a correct offset value even when a sampling period is long as in the case of a low-speed A/D converter and restraining the influence of noise. The offset correcting circuit for an encoder adapted to output an angle signal based on digital signals obtained by performing A/D conversions of two signals having phases different by about 90 degrees in accordance with the same timing includes an offset detecting circuit for obtaining an offset value of one of the two signals, using an A/D converted value of that one signal which is obtained when an A/D converted value of the other of the two signals is zero or close to zero, and a compensating circuit for compensating an offset of that one signal using the offset value detected by the offset detecting circuit.

Abstract: A DC offset cancellation circuit receives two input signals. A first one of the input signals is amplified by an amplifier, and the amplified output signal of the amplifier is tracked and held during a first clock phase. Simultaneously, during the first clock phase, the second one of the input signals is tracked and held. During the second clock phase succeeding the first clock phase, the stored second one of the input signals is amplified by the same amplifier that was used to amplify the first one of the input signals. The amplified and stored first one of the input signals and the amplified second one of the input signals are summed during the second clock phase to remove any DC offset. The summed signals are sampled and held during the second clock phase. The offset of the summer circuit can be canceled by sequential digital processing.

Abstract: An encoder interpolation circuit for obtaining interpolation data within one wave from two sine-wave encoder signals of different phases comprises interpolative computation means (2) for receiving two sine-wave encoder signals received and carrying out to interpolative computation within one wave, signal deviation detecting means (3) for detecting a deviation of the two sine-wave encoder signals, correction data forming means (4) for outputting correction data corresponding to the detected deviation and the output of the interpolative computation means, and corrective computation means (5) for obtaining the corrected interpolation data by carrying out corrective computation for the output of the interpolative computation means with the correction data and obtaining corrected interpolation data.

Abstract: The present invention is directed to a method and apparatus which utilizes a software-based digital signal processing circuit to generate a signal which is representative of the status of a movable component. A preferred embodiment of the apparatus of the present invention includes a synchro which is connected to a movable component. An analog reference excitation may be applied to the synchro, and the synchro generates analog synchro signals which bear a relationship to the status of the movable component. The analog synchro signals are converted to digital synchro signals by a plurality of analog-to-digital converters. A digital reference signal and the digital synchro signals are provided to a software-based digital signal processing circuit which preferably corrects constant and time-varying errors in the digital synchro signals and generates a status signal which is representative of the status of the movable component.

Abstract: A digital phase measuring system and method for measuring the phase difference between two signals including generating quadrature clock signals for a first reference signal, converting a second measured signal from analog to digital form by sampling the second measured signal using the quadrature clock signals to produce quadrature cartesian samples of the measured signal, and converting the quadrature cartesian samples to polar coordinates to define the polar phase coordinate representative of the phase difference between the two signals.

Abstract: A reproduced signal from a recording medium 1 is equalized at partial response (1, 0, -1) by a reproducing equalizer 3, and is converted into a reproduced and equalized signal. A clock reproducing circuit 4 issues a reproduced clock synchronized with the timing of data identification, and applies it to a phase adjusting circuit 5. A phase control signal generating circuit 6A detects a specific pattern from a reproduced digital signal issued from an A/D converter 7, and the advance or delay amount of phase of the reproduced clock is detected by the amplitude or distribution of the sampling value. This phase deviation amount is given to the phase adjusting circuit 5 as a phase control signal. The phase adjusting circuit 5 given a delayed clock to the A/D converter 7, and controls to A/D convert the reproduced signal at correct timing.

Abstract: Output of an encoder are sampled by A/D converters 11a and 11b to be converted to N bits A-phase and B-phase digital data DA and DB. In a look-up table memory 12, reference phase angle data of phase divisions and average gradient vectors of changes in phase angle data within the phase divisions are stored, the phase divisions being addressed by the high order NU bits of data DA and DB. An arithmetic circuit 13 determines a vector inner product of an average gradient vector and phase-interpolating data represented by the low order NL bits of the data DA and DB to add the resultant to a phase angle data, thereby outputting an interpolated phase angle data.

Abstract: An interpolation circuit of an encoder of which dynamic accuracy is improved is disclosed. The phase angle data detecting circuit 1 detects to store the phase angle data PH for each of the first clock CK1. The phase angle data PH is input to the updating circuit 2 in which the current data CNT is subtracted from the subsequent phase angle data PH so as to be updated. The differential data DX is limited within an upper limit to be added to the current data CNT. The integrating circuit 3 integrates the differential data DELTA1, whose upper limit is predetermined, by the second clock CK2 to generate the carry signal QUADEN at each timing when the integrated value leads to the period ratio of CK1 to CK2. The two-phase square wave generating circuit 5 generates two-phase square wave signals at each timing of the carry signal QUADEN. The over-speed detecting circuit 6 monitors the differential data DX to generate the over-speed alarm signal OSALM under a predetermined condition.

Abstract: An angle data computation apparatus, which comprises arithmetic means (4) for computing the angle data by considering the encoder signals in different phases as triangular-wave signals; correction data storage means (5) for storing correction data for correcting angle errors between the encoder signals and triangular-wave signals based on arithmetic data from the arithmetic means (4) serving as addresses; adder-subtracter means (6) for adding up the arithmetic data from the arithmetic means (4) and the correction data from the correction data storage means (5); and converter means (7) for converting the angle corresponding to the quadrant for the encoder signals.

Abstract: An ultrahigh-speed analog-to-digital converter that does not use optical signals is implemented by means of simple circuit configurations. To achieve this, phase differences between a carrier and modulated signals are detected, the modulated signals having been obtained by modulating the phase of the carrier with an analog signal. Analog-to-digital conversion is then performed by applying binary weighting to the modulation factors of the phase modulations. Alternatively, different relative delays are applied stepwise in 2.sup.n -1 stages (where n is the resolution) between the carrier and the signal that has been phase modulated by the analog signal. The phase of the signals with these delays and the phase of the signal without any delay are respectively compared in 2.sup.n -1 stages. An n-bit digital signal is formed and output on the basis of the results of these comparisons.

Abstract: A method and an arrangement for reducing the influence from distortion which is produced when an electrical signal, which is divided into two components, is converted from analogue to digital form. The signal is divided in a phase detector in which it is phase detected with respect to two reference signals, phase shifted 90.degree. with respect to each other. The two components are frequency coded by the reference signals which are provided with a periodic frequency sweep. After the conversion into digital form, each of the components are frequency decoded so that they, with respect to frequency, appear as narrow band signals while possible harmonics which are part of the distortion, are distributed over a frequency range defined by the size of the periodic frequency sweep.

Abstract: A digital time interpolation system and method for quantizing the time-difference between two digital signals. The present invention measures the time-difference between consecutive zero crossings of a user signal and a reference oscillator. The present invention outputs interpolator data, which represents this time-difference in digital form. The present invention includes a quadrature hybrid, a synchronizer, track-and-holds (T&Hs), analog-to-digital converters (ADC), an encoding circuit, and a boundary detector. The present invention also includes a system for deskewing the recorded coarse time count and the fine time value. According to the present invention, the reference oscillator is a continuous, two-phase signal having a unique pair of output values at any given instant of its period. By using this reference oscillator, the present invention accelerates conversion. The present invention uses a novel boundary detection scheme.

Abstract: A phase compensation circuit for use with a resolver circuit that compensates for resolver angle measurement error without the use of special compensation windings on the resolver or the buffer amplifier associated with the compensation windings. With the present invention, primary windings from a plurality of resolvers may be reduction over conventional circuits. A digital computer is employed to process integrated data indicative of the phase shift of signals generated by the resolver, and compute error correction signals that compensate sine and cosine angle data output signals of the resolver. No resolver compensation windings are necessary and no additional electronic equipment is necessary. The present invention provides increased accuracy to fulfill more stringent angle measurement specifications.

Abstract: A device comprises output device for receiving signals having predetermined phases and outputting first and second signals having different phase angles and amplitudes, conversion device for converting the first signal into a first binary signal and the second signal into a second binary signal, the conversion device being arranged so that widths of the first and second binary signals are substantially equal to each other regardless of a difference in amplitude of the first and second signals, and generating device for generating first and second pulses according to phase angles on the basis of the first and second binary signals.

Abstract: A software-based resolver-to-digital converter (RDC) (80) for computing an angle of rotation &THgr; of gimbal-mounted instrumentation (16) in a gimbal system. The RDC (80) computes the angle of rotation of the instrumentation using parameter signals received from a resolver (32) in the system. The parameter signals, along with a resolver reference signal are input into a multiplexor (60) and are multiplexed. The signals are then fed to an analog to digital converter (38) and converted to digital form. The digital signals are then input into a processor (36) associated with the system. This processor, in addition to performing numerous system computations, is programmed through appropriate software to filter the digital signals received, compute the value for the angle of rotation &THgr; and output the computed value to system circuitry (31) for processing to enhance system operation.