Abstract: Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange).

Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

Abstract: An ADC can include a plurality of time-interleaved ADCs to increase the overall sampling rate of the ADC. Such an ADC can have interleaving errors, since the time-interleaved ADCs in the ADC are not always perfectly matched. One way to calibrate for these mismatches is by observing the digital output signals of the time-interleaved ADCs in the background, or more broadly, without knowledge of the input signal to the ADC (often referred to as “blind” calibration). Due to the nature of these calibrations, the performance of the calibration would significantly degrade when the input signal has certain problematic input conditions, such as a certain coherent input frequency. To address this issue, the data being used for calibration of interleaving errors can go through a qualifying process to assess whether to update error estimates based on the data.

Abstract: An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time-skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) to provide a pseudorandom number (PN) to the switch (510), to the calibration device (530), and to the multiplier (540). In some embodiments, the calibration device (530) may include first and second offset calibration circuits (531-532) coupled in parallel between a de-multiplexer (D1) and a multiplexer (M1) that alternately route signals to the first and second offset calibration circuits (531-532) based on the pseudorandom number (PN).

Abstract: The disclosure provides a circuit. The circuit includes a zone detection block that generates a control signal in response to an input signal. An amplifier generates an amplified signal in response to the input signal and the control signal. An analog to digital converter (ADC) is coupled to the amplifier and samples the amplified signal to generate a digital signal. A digital corrector is coupled to the zone detection block and the ADC, and transforms the digital signal to generate a rectified signal based on the control signal and an error signal. An error estimator is coupled to the zone detection block and receives the rectified signal as a feedback. The error estimator generates the error signal in response to the control signal and the rectified signal.

Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M?1 sampling phases of the M sampling phases. The phase control circuit comprises M?1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M?1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.

Abstract: A headphone driver includes first and second differential driver differential driver. The first differential driver has a first positive output terminal and a first negative output terminal. The first positive output terminal is coupled to a first terminal of a first speaker. The first negative output terminal is virtually shorted to a reference voltage through a first feedback circuit in the first differential driver. The second differential driver has a second positive output terminal and a second negative output terminal. The second positive output terminal is coupled to a first terminal of a second speaker, wherein the second negative output terminal is virtually shorted to the reference voltage through a second feedback circuit in the first differential driver. The first negative terminal and the second negative terminal are connected to a common line, which is to be further connected to second terminals of the first speaker and the second speaker.

Abstract: Systems and methods are disclosed for Successive Approximation Register Analog-to-Digital Converter (SAR ADC) by coupling an ADC capacitive network coupled to a comparator; and performing binary search using a comparator output using a capacitive DAC calibration process to enhance SAR ADC linearity and performance. In one implementation, the calibration process starts with the least significant bit (LSB) capacitor calibration then proceed to higher bit capacitors until all the capacitors are calibrated. Each capacitor consists of fixed-value base capacitor and value-adjustable capacitor. The capacitor calibration logic is implemented based on the process then incorporated into SAR ADC. ADC performs capacitor calibration first before normal conversion operation. The non-ideal aspect of normal conversion operation is preserved and accounted during capacitor calibration.

Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

Abstract: A pixel of a pixel array is provided. The pixel includes a low frequency path configured to receive an input signal from a corresponding photodetector. The low frequency path includes a passive imaging circuit provided along the low frequency path, the passive imaging circuit configured to output an analog imaging signal and a flash analog to digital converter (ADC) that receives the analog imaging signal and processes the analog imaging signal to output a coarse digitized signal.

Abstract: It is described an electronic device (1) for measuring an electric quantity, comprising: an analog-digital conversion module (2) configured to digitally convert time portions of an analog signal (SM(t)) to be measured alternated with time portions of a reference analog signal (SR(t)), for supplying respective first (DSM) and second pluralities (DSR) of digital values and a digital processing module (3) configured to: calculate a first mean amplitude (A1) of the first pluralities of digital values, and a second mean amplitude (A2) of the second pluralities of digital values; the first and second mean amplitudes being proportional to a mean gain value of the analog-digital conversion module (2); supply a ratio value (VRT) of the first mean amplitude to the second mean amplitude, representative of a measured amplitude of the analog signal (SM(t)) to be measured.

Abstract: A dither is an uncorrelated signal, usually pseudo-random noise injected into the input of an ADC such that a given input value of the wanted signal becomes spread over a plurality of codes. This reduces the effect of DNL and also smooths the integral non-linearity (INL) response of the ADC. The advantages of introducing dither could be obtained without having to perturb the signal input to the ADC. This avoids the introduction of additional components in the ADC. The dither can be applied to the components used to form a residue of the ADC stage within a pipelined converter. For example, a dither can be applied solely to a DAC part or different dithers can be applied to a ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.

Abstract: An apparatus of mass flow controlling for use in an integrated gas delivery system, comprising an input terminal, an output terminal, a sensor unit, a flow rate control valve, and a control unit. The control unit comprises an A/D converter, a microprocessor, and a valve control circuit. The A/D converter converts an actual setting signal inputted by the input terminal into a first digital signal, and converts a flow rate detection signal outputted by the sensor unit into a second digital signal. The microprocessor further comprises a storage module, a setting signal calibration module and a calculation module. The valve control circuit generates, based on a control signal, an openness control signal, so as to control the flow rate control valve. It is concluded that the flow rate control quality is improved by the present invention.

Abstract: Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component.

Abstract: A comparison device includes an MSB voltage generation circuit that includes a control signal terminal to generate an MSB voltage; a comparison circuit including a first input terminal receiving a first input signal and a second input terminal receiving a second input signal modified by the MSB voltage outputted from the MSB voltage generation circuit to move to a desired voltage range by comparing the first input signal with the modified second input signal to output an MSB comparison result signal, the comparison circuit, after the first input signal has reached the desired voltage range, comparing the first input signal with a residue voltage and outputting an LSB comparison result signal; and a control circuit receiving the comparison signal and operable to detect a crossing of the first input signal and the second input signal according to the MSB comparison result signal and to output the MSB voltage control signal.

Abstract: An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.

Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Abstract: A self-calibrating Analog-to-Digital Converter (ADC) performs radix error calibration using a Successive-Approximation Register (SAR) to drive test voltages onto lower-significant capacitors. The final SAR code is corrected by performing LSB averaging on LSB averaging capacitors and then accumulated, and the measurement repeated many times to obtain a digital average measurement. An ideal radix or ratio of the measured capacitor's capacitance to a unit capacitance of an LSB capacitor is subtracted from the digital average measurement to obtain a measured error that is stored in a Look-Up Table (LUT) with the ideal radix. Radix error calibration is repeated for other capacitors to populate the LUT. During normal ADC conversion, the SAR code obtained from converting the analog input is applied to addresses the LUT, and all ideal radixes and measured errors for 1 bits in the SAR code are added together to generate an error-corrected digital value.

Abstract: A voltage generator configured to generate a plurality of voltage groups, each of the plurality of voltage groups including a plurality of reference voltages, and a decoder having an output node configured to output one of the plurality of reference voltages is disclosed. The decoder includes switch blocks that correspond to the plurality of voltage groups. Each of the switch blocks includes transistors that are turned on or off by or in response to a control signal, and each transistor in one of the switch blocks has a channel width different from a channel width of each transistor in another one of the switch blocks.

Abstract: A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output includes a first capacitor digital-to-analog (DAC) and a second capacitor DAC. One of the first capacitor DAC and the second capacitor DAC that has greater output signal is defined as a higher-voltage capacitor DAC, and the other as an un-switching capacitor DAC. In an m-th conversion phase, an (m?1)-th capacitor of the un-switching capacitor DAC is switched according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC.

Abstract: A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.

Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.

Abstract: A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.

Abstract: An image sensor is provided. The image sensor may include an active pixel electrically connected to a column line and configured to provide an output voltage to a pixel node and a bias circuit electrically connected between the pixel node and an earth terminal, and in which a first current flows through a first line electrically connected to the pixel node, wherein the bias circuit includes a first variable capacitor electrically connected to a power supply voltage, and a second variable capacitor electrically connected to the earth terminal, and the magnitude of the first current may be configured to vary based on a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor. The output voltage may be configured to be adjusted based on the magnitude of the first current.

Abstract: Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.

Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

Abstract: In an embodiment, an adaptive drive strength switching converter includes a driver and a control loop coupled to the driver. In an embodiment, the control loop includes a peak detector, a comparator coupled to an output of the peak detector, a counter coupled to an output of the comparator, and a digital-to-analog converter (DAC) coupled to an output of the comparator.

Abstract: A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

Abstract: Multiple-bit parallel successive approximation (SA) Flash analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SA Flash ADC circuit includes a digital-to-analog converter (DAC) circuit that receives reference voltage and trial bit codes, and generates DAC analog signals. The SA Flash ADC circuit includes parallel comparator stages, each including one or more comparator circuits equal to two (2) raised to a number of digital bits of the corresponding parallel comparator stage, quantity minus one (1). Each comparator circuit receives an analog input signal and corresponding DAC analog signal, and generates a digital signal. The digital signal of each comparator circuit is logic high if the analog input signal has a greater voltage than the corresponding DAC analog signal, and logic low if the analog input signal has a smaller voltage. The digital signals corresponding to each parallel comparator stage are used to generate a digital output signal.

Abstract: Various embodiments include methods and systems having a frequency-modulated continuous wave radar operable to compensate a return signal for nonlinearity in the associated radar signal that is transmitted. The radar signal can be mixed with a delayed version of the radar signal such that the mixed signal can be used to generate an estimate of the nonlinearity. The estimate can be used to compensate the return signal from an object that reflects the associated transmitted radar signal. Additional apparatus, systems, and methods can be implemented in a variety of applications.

Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.

Abstract: A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.

Abstract: Systems and methods for direct sample, extremely wideband transceivers are disclosed. An example transceiver includes an antenna, an N bit analog to digital converter a digital signal processor, a digital to analog converter, and an adder. The N bit ADC receives a wideband RF input signal from the antenna, where the input signal includes weak signals and a strong signal, oversamples the input signal and provides a digital sample signal. The digital signal processor generates a digital cancellation signal from the digital sample signal, where the digital cancellation signal is generated using M bits, M greater than N. The DAC provides an analog cancellation signal based on the digital cancellation signal, and the adder provides a residual analog signal from the addition of the input signal and the analog cancellation signal, where the strong signal is at least reduced in the residual analog signal due to the analog cancellation signal.

Abstract: A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

Abstract: Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.

Abstract: The disclosure provides a method for determining link delay. The method includes: according to a preset frequency division multiple, performing frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and, according to the second LMFC, writing respectively the data of each data lane into a corresponding buffer; and according to a SYSREF signal and a preset LMFC interval, generating a third LMFC, and, according to the third LMFC, reading respectively the data of each data lane from the corresponding buffer. The period of the second LMFC is the same as the period of the third LMFC. The disclosure also provides an apparatus, a communication device and a storage medium for implementing the method.

Abstract: A display apparatus and a driving method for the display apparatus are provided. The display apparatus includes a display panel and a first source driver. The display panel has a pixel array. The first source driver sequentially supplies a first overdrive voltage and a driving voltage to a pixel in the pixel array. The first overdrive voltage has a plurality of voltage levels according to positions of pixels in the pixel array.

Abstract: An image acquisition apparatus including: a stage on which a specimen is mounted; an objective lens that collects light from the specimen; a stage driving part that drives the stage; an image capturing unit that acquires an image by photographing the light collected by the objective lens; an image-generating unit that generates a pasted image by pasting the captured image acquired by the image capturing unit; a storage unit that stores the pasted image; a color-difference calculating unit that calculates a degree of dissimilarity between a color of the pasted image and a color of the captured image prior to pasting; and a color-difference correcting unit that corrects the color of the captured image so as to match the color of the pasted image, on the basis of the calculated degree of dissimilarity.

Abstract: The invention relates to a circuit arrangement comprising a control device, an input circuit for applying an input signal, a conditioning circuit electrically connected to the input circuit for converting the input signal into a measured signal, an analog-to-digital converter electrically connected to the conditioning circuit for converting the measured signal into a digital value, and a reference source that outputs a known reference signal. In this respect, a first switching apparatus is provided that selectively separate the input signal from the conditioning circuit or supplies it to the conditioning circuit and a second switching apparatus is provided that selectively supplies the reference signal to the input circuit or separates it from the input circuit, wherein the control device is configured to determine an offset error and to determine a gain error of the circuit arrangement.

Abstract: A method to measure and report electromagnetic radiation power includes receiving electromagnetic radiation and generating an electrical signal having a magnitude based on the power of the electromagnetic radiation. An adjustable gain may be applied to the electrical signal to generate an amplified electrical signal that may be sampled to generate a digital sample. The adjustable gain may be controlled based on the value of the digital sample and the digital sample may be associated with a gain value. One or more calibration factors may be selected based on the gain value associated with the digital sample and the selected calibration factor(s) may be used to calculate the power of the electromagnetic radiation.

Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

Abstract: An over-the-air measurement system for testing the over-the-air characteristics of a device under test is described, comprising several antenna units for receiving and transmitting radio frequency signals, several remote radio units that convert radio frequency signals into digital signals or vice versa, and a baseband unit for generating and analyzing baseband signals. The baseband unit is connected to the remote radio units, the baseband unit having at least one physical layer control unit that is configured to adapt the over-the-air measurement system with regard to the physical layer. The several antenna units are connected to the remote radio units. Further, a method for testing the over-the-air characteristics of a device under test is described.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.

Abstract: Amplifier circuitry has sampling circuitry which samples an input voltage, a quantizer which quantizes an output voltage of the sampling circuitry and outputs an output code, a differential amplifier which amplifies a differential voltage between the output voltage of the sampling circuitry and a reference voltage and performs offset adjustment according to the output code of the quantizer, and a first capacitor which is connected between an output node of the differential amplifier and an output node of the sampling circuitry.