Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

Abstract: A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.

Abstract: A test apparatus includes a motherboard including a first surface. The test apparatus further includes a handler including a second surface facing the first surface of the motherboard. The test apparatus additionally includes an adapter board disposed between the first surface of the motherboard and the second surface of the handler. The test apparatus further includes a first sensor mounted on the adapter board and senses data about temperature of the adapter board. The test apparatus additionally includes a wireless transceiver mounted on the adapter board and transmits, in real time, the sensed data.

Abstract: Demodulation circuitry includes an input terminal configured to be coupled to an analog-to-digital converter (ADC) and configured to receive a plurality of ADC outputs. The plurality of ADC outputs are generated based on resolver outputs. The demodulation circuitry also includes a rectifier configured to rectify the plurality of ADC outputs. Rectifying the plurality of ADC outputs preserves a phase of the plurality of ADC outputs. The demodulation circuitry includes amplitude determination circuitry configured to determine, based on the rectified plurality of ADC outputs, demodulated amplitude values corresponding to the resolver outputs. The demodulation circuitry further includes angle computation circuitry configured to generate position outputs based on the demodulated amplitude values.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

Abstract: A method and apparatus for calibrating a temperature sensor is disclosed. In one embodiment, a method comprises generating first and second digital values based respectively on first and second voltages applied to a portion of a temperature sensor circuit. An arithmetic circuit may derive the value of the second voltage based on the first and second digital values. The method further comprises determining an initial value of a constant based on values of the first and second voltages, and determining a final value of the constant based on the initial voltage and at least one voltage offset. The constant may then be used in determining temperature readings for the temperature sensor.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

Abstract: A temperature sensing device includes a temperature-voltage converter that outputs a first voltage, having a zero temperature coefficient that does not vary with a temperature, and a second voltage having a negative temperature coefficient varying in inverse proportion to the temperature. A multiplexer alternately outputs the first voltage and the second voltage depending on a transition signal. A temperature sensor alternately receives the first voltage and the second voltage and senses the temperature depending on a ratio of the first voltage and the second voltage.

Abstract: A regulator includes a first resistor and a second resistor that are connected between a ground node and an output node, an amplifier that outputs an amplification voltage by comparing a reference voltage to a feedback voltage between the first resistor and the second resistor, and amplifying a difference between the reference voltage and the feedback voltage, an analog-to-digital converter that converts the amplification voltage to a digital code, and a plurality of transistors that are connected between a power node supplied with a power supply voltage and the output node and which adjusts a current being supplied to the output node in response to the digital code.

Abstract: Many electronic circuits rely on the ratio of one component to other components being well defined. Current flow in component can warm the component causing its electrical properties to change, for example the resistance of a resistor may increase due to self-heating as a result of current flow. The present disclosure provides a way to reduce temperature variation between components so as to reduce electrical mismatch between them or the consequences of such mismatch. This is important as even a change of resistance of, for example, 20-50 ppm in a resistor can result in non-linearity exceeding the least significant bit value of a 16 bit digital to analog converter.

Abstract: A system for automating the growing of crops, such as grapevines. Combinations of data from sensors local to a vineyard, and from optional remote stations and sensors, is combined with a control system to accurately control the dispensing of water and chemicals such as insecticides, disease prevention fungicides and fertilizers. The materials are dispensed through a multiple channel conduit which allows conflicting, or incompatible, types of materials to be transported through a common assembly. Sensors are attached to the conduit so that the placement of sensors can occur simultaneously with the laying of the conduit. This approach also ensures correct placement and spacing of the sensors with respect to each plant, or plant area, to be monitored and treated.

Abstract: Circuits for a successive approximation register analog-to-digital converter and related methods. A global reference circuit includes a first super source follower (SSF) circuit having an input coupled to an output of a first current mirror and to a first adjustment circuit, and an operational amplifier having an input coupled to an output of the first SSF circuit and an output coupled to an input of the first current mirror. Local slices each include a second current mirror having an input coupled to the output of the operational amplifier, a second super source follower (SSF) circuit having an input coupled to an output of the second current mirror and to a second adjustment circuit. The first and second adjustment circuits may be configured to adjust a voltage at the input of the first SSF circuit and respective voltages at the input of the second SSF circuit of each local slice.

Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.

Abstract: In various embodiments, at least one analog-to-digital converter (ADC) channel circuit may be used to convert an analog input signal into an output digital signal. A comparator threshold adjustment circuit may pseudorandomly modify at least one comparator threshold. A postprocessing circuit may identify, based on outputs of the ADC channel circuits, an ADC coefficient and may modify an output digital signal based on the ADC coefficient. As a result, the ADC channel circuits may more accurately convert the analog input signal into an output digital signal, as compared to a system that uses ADC channel circuits but does not include a postprocessing circuit. Further, a similar result may be obtained, as compared to a system that uses a higher gain amplifier, a higher speed amplifier, or both, but does not modify the one or more outputs.

Abstract: A programmable temperature compensated voltage reference is disclosed. In an exemplary embodiment, an apparatus includes a digital-to-analog converter (DAC) that uses a reference voltage and a code to generate a DAC output voltage. The apparatus also includes a temperature compensator that uses a temperature measurement (T) and the DAC code to generate a temperature compensation signal. The temperature compensation signal is represented by a third order polynomial equation. The apparatus also includes a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate a temperature compensated programmable reference voltage.

Abstract: Systems for processing pixel signals generated by an image sensor to create improved images. More particularly, systems and methods are disclosed that adjust the gain on, inter alia, a pixel-by-pixel basis, to improve the dynamic range of the imaging system. The systems may include level detectors that measure the amplitude of a pixel signal and, based on that measurement, amplify that pixel signal by an amount that allows certain subsequent processing of the pixel signal to be more accurate. More accurately processed pixel signals can provide better overall images.

Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

Abstract: A high resolution data acquisition (DAQ) system is initially calibrated with a reference source having a resolution higher than the DAQ system. Measurements over the operating range of the DAQ system are taken, and characteristic calibration coefficients are determined from the measurements. Software corrections based upon the calibration coefficients are made to DAQ system measurements. A digital to analog converter (DAC) on-board the DAQ system having a lower resolution than the DAQ system is calibrated by generating a look-up table of input digital codewords and output electrical signals measured by the calibrated DAQ system. This look-up table is used to field calibrate the DAQ system using only the DAC, rather than the high resolution reference source.

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is coupled to the comparator, and receives one of an input voltage and a set of reference voltages. A set of M offset capacitors is coupled to the comparator, and receives one of a primary voltage and a secondary voltage, M is an integer. A difference in the primary voltage and the secondary voltage varies linearly with temperature.

Abstract: A programmable temperature compensated voltage reference is disclosed. In an exemplary embodiment, an apparatus includes a digital-to-analog converter (DAC) that uses a reference voltage and a code to generate a DAC output voltage. The apparatus also includes a temperature compensator that uses a temperature measurement (T) and the DAC code to generate a temperature compensation signal. The temperature compensation signal is represented by a third order polynomial equation. The apparatus also includes a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate a temperature compensated programmable reference voltage.

Abstract: A transimpedance amplifier includes a current regulator having a first current mirror of a first conduction type and a first current mirror of a second conduction type. The first current mirror stage of a first conduction type receives a reference current. The first current mirror stage of a second conduction type is connected to the first current mirror stage of the first conduction type, and receives an output current from the first current mirror stage of the first conduction type, and to generate a current to be used as a current source by a transimpedance amplifier. Each of the current mirror stages includes a first transistor and a second transistor of the same conduction type having their gate terminals connected wherein the first transistor receives an input current and the second transistor provides an output current that is a factor of the received input current.

Abstract: The measuring device with electric voltage divider comprises a first measuring resistor connected between a voltage measurement input and a common point, and a second measuring resistor connected between said common point and a reference electric ground. A measurement output is connected to the common point. An outer shielding enclosure surrounds the first and second measuring resistors and is connected to the reference electric ground. An inner capacitive electrode surrounding the first and second measuring resistors is arranged inside said outer shielding enclosure. To improve the phase difference and passband, the device comprises a phase difference compensation circuit connected between said inner capacitive electrode and said common point.

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.

Abstract: The influence of a jitter of a sampling clock of an analog-to-digital converter is digitally corrected at low power consumption. The sampling clock of the analog-to-digital converter is generated by a phase locked loop (PLL) using a reference clock, which has a lower frequency and lower jitter than the sampling clock, as a source oscillation. A time-to-digital converter (TDC) converts a timing error at a timing where the sampling clock and the reference clock are synchronized with each other into a digital value. A timing error at a sampling timing where the reference clock is not present is generated by interpolating a detected timing error. Thus, a jitter value of the sampling clock at each sampling timing is obtained. A sampling voltage error is calculated from the jitter value and the output of the analog-to-digital converter is digitally corrected.

Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.

Abstract: An analog-to-digital conversion circuit includes an analog-to-digital conversion unit configured to analog-to-digital convert an input voltage and generate a digital signal, a resolution control unit configured to: set a resolution of the analog-to-digital conversion unit to N (N is the natural number) bits, in a case where the input voltage is smaller than a first voltage, and set the resolution of the analog-to-digital conversion unit to N?M (1?M<N, M is the natural number) bits in a case where the input voltage is larger than the first voltage, and a signal correction unit configured to: generate a corrected digital signal based on a boundary value and the digital signal, in a case where a value of the digital signal is larger than the boundary value and the input voltage is smaller than the first voltage.

Abstract: An analog-digital conversion circuit includes a comparator that receives an analog input signal. A controller generates an N1-bit first signal and an N2B-bit second signal in accordance with an output signal from the comparator. A first digital-analog converter generates a first reference signal from the first signal. A second digital-analog converter generates a second reference signal from the second signal. A correction circuit corrects the first and second signals to generate a digital output signal. The N2B-bit second signal is acquired by adding a Kbit correction signal to an N2A-bit signal. The controller sequentially sets bit values of the first signal and bit values of the second signal in accordance with the output signal of the comparator. The correction circuit generates the (N1+N2A)-bit digital output signal based on a sum of a value acquired by multiplying the N1-bit first signal by 2^N2A and a value of the N2B-bit second signal.

Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.

Abstract: During operation of the device, a drive circuit may provide a drive signal having a fundamental frequency to two electrothermal filters (ETFs) having different temperature-dependent time constants. In response to the drive signal, the two ETFs may provide signals having the fundamental frequency and phases relative to the drive signal corresponding, respectively, to the time constants of the ETFs. Then, phase-shift values of the phases may be measured using a phase detector, and a signal may be output based on the phase-shift values. Note that the signal may correspond to a value that is a function of a temperature of the device.

Abstract: A successive approximation register analog-to-digital converter and a conversion time calibration method thereof are provided. The successive approximation register analog-to-digital converter includes a conversion circuit and a conversion time calibration apparatus. The conversion circuit has a conversion time under a process, voltage, and temperature (PVT) variation. The conversion time calibration apparatus is configured to detect a conversion time condition and adjust the conversion time of the conversion circuit according to the conversion time condition.

Abstract: A measurement signal correction apparatus includes an analog/digital converter, a correction factor providing unit, and a measurement signal correction unit. The analog/digital converter is configured to convert an analog measurement signal read in using an interface into a digital measurement signal using a reference frequency signal. The correction factor providing unit is configured to provide a correction factor determined on the basis of the reference frequency signal. The measurement signal correction unit is configured to multiply the digital measurement signal by the correction factor in order to obtain a corrected measurement signal.

Abstract: An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.

Abstract: A system for minimizing variation of a voltage reference includes a voltage reference generator and a power converter. The voltage reference generator is configured to generate a voltage reference from a supply voltage. The power converter, such as a flyback converter, is configured to supply an adjustable supply voltage to the voltage reference generator. The voltage reference generator generates the voltage reference from the adjustable supply voltage.

Abstract: A calibration control circuit is provided for calibrating a stage in a pipeline analog-to-digital converter (ADC). The stage includes an analog-to-digital subconverter (ADSC) and a multiplying digital-to-analog converter (MDAC). The calibration control circuit includes circuitry coupled to comparators in the ADSC to force the comparators to output a predetermined digital output signal set by a calibration control signal when the ADC is in a calibration mode to thereby control reference switches in an analog multiplexer (AMUX) to selectively apply reference voltages to capacitors in the MDAC to obtain a predetermined stage residue signal.

Abstract: A system and method can be used for scaling an output of a modulator of a sigma-delta analog to digital converter and systems and a method can be used for compensating temperature-dependent variations of a reference voltage in a sigma-delta analog to digital converter. In accordance with one embodiment, a system can be used for scaling an output of a modulator of a sigma-delta analog digital converter (ADC). A decimation filter has a decimation length that is adjustable by a decimation length value received as an input to the decimation filter. The decimation filter is configured to receive the output of the modulator of the sigma-delta ADC and to decimate the received output of the modulator of the sigma-delta ADC using the received decimation length value.

Abstract: The invention provides a testing apparatus. In one embodiment, the testing apparatus receives a plurality of bit signals output by an analog-to-digital converter, and comprises a plurality of frequency counters and a comparison module. The frequency counters respectively calculate a plurality of transition frequencies of the values of the bit signals. The comparison module respectively compares the transition frequencies with a plurality of ideal transition frequencies to obtain a plurality of error frequencies. The performance analysis module estimates a performance value of the analog-to-digital converter according to the error frequencies.

Abstract: A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.

Abstract: Disclosed are methods and apparatus for sampling rate conversion in a wireless transceiver. The methods and apparatus achieve agile setting of sampling rates or resampling by adaptively setting a sampling rate of a signal based on at least one performance requirement of the transceiver. In particular, the methods and apparatus perform sampling of an input signal at a first sampling rate to gain one or more input signal samples. The input signal samples are then filtered using parallel or polyphase filtering operating at a second sampling rate lower than the first sampling rate. The filtered samples are then interpolated at the second sampling rate to achieve resampling of the input signal. Polyphase filtering affords an effectively high input sampling rate for good spectrum image rejection, while allowing the second sampling rate to be effectively much lower than the first rate, thereby reducing the complexity of multiplier operations for interpolation.

Abstract: A system and method can be used for scaling an output of a modulator of a sigma-delta analog to digital converter and systems and a method can be used for compensating temperature-dependent variations of a reference voltage in a sigma-delta analog to digital converter. In accordance with one embodiment, a system can be used for scaling an output of a modulator of a sigma-delta analog digital converter (ADC). A decimation filter has a decimation length that is adjustable by a decimation length value received as an input to the decimation filter. The decimation filter is configured to receive the output of the modulator of the sigma-delta ADC and to decimate the received output of the modulator of the sigma-delta ADC using the received decimation length value.

Abstract: Nonlinearity correction in a device that performs analog-to-digital conversion on received analog signals, may be calibrated by generating correction-parameters estimation which when applied to the total spectral content reduces distortion resulting from said nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity calibration may be performed during reception and handling of said analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction.

Abstract: A combined digital output system includes two quantization modules, a common mode counter, a differential mode counter, and a summing module. The quantization modules provide two digital signals, the common mode counter generates a common mode signal according to the digital signals, the differential mode counter generates a differential mode signal according to the two digital signals, and the summing module obtains the common mode signal and the differential mode signal, so as to generate a summing signal.

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract: An ADC code given in response to input of an analog input value to an A/D converter circuit is measured at a site where an A/D converter unit is used to measure a user-measured value. A user-set value calculating part calculates a user offset value and a user gain value on the basis of one user-measured value, a factory offset value, and a factory gain value, and stores the calculated user offset value and the user gain value in a nonvolatile memory.

Abstract: A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.

Abstract: Systems and methods are provided for converting analog data to digital data that can include performing N successive analog subtractions from an initial data charge Qin. The analog subtractions are performed using an amplifier coupled to a discharge capacitor and a divider circuit coupled to an input of the amplifier. The divider circuit includes a first capacitor, a second capacitor, and a switch to alternately divide a remaining charge Q by 2N between the first and second capacitors until the remaining charge Qin at the amplifier is below a threshold value. A compensating circuit compensates for fluctuations in the charge held by the first and second capacitors due to operation of the switch.

Abstract: A voltage converter for converting an analog input signal into a digital signal is provided. The pulse width of the digital signal is relative to the voltage level of the analog input signal. The voltage converter includes a comparator and a feedback module. After comparing the analog input signal and an analog feedback signal, the comparator generates the digital signal. When the analog input signal is higher than the analog feedback signal, the digital signal has a first voltage level. When the analog input signal is lower than the analog feedback signal, the digital signal has a second voltage level, which is different from the first voltage level. Based on the digital signal, the feedback module adjusts the analog feedback signal toward the analog input signal.

Abstract: A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.