Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

Abstract: The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.

Abstract: A method for fingerprint sensing of an electronic module capable of fingerprint sensing, the electronic module for being coupled to a plurality of fingerprint sensing pixels, the electronic module including an analog front-end stage for being coupled to the fingerprint sensing pixels, the method comprising the following steps. A first scanning operation is performed on at least a first portion of the fingerprint sensing pixels by using a first reference signal being applied to a reference terminal of the analog front-end stage to obtain a level of a second reference signal which is based on a sensing result of the first scanning operation and is different from the first reference signal. A second scanning operation is performed on at least a second portion of the fingerprint sensing pixels by using the second reference signal being applied to the reference terminal of the analog front-end stage.

Abstract: Transforming a voice of a speaker to a reference timbre includes converting a first portion of a source signal of the voice of the speaker into a time-frequency domain to obtain a time-frequency signal; obtaining frequency bin means of magnitudes over time of the time-frequency signal; converting the frequency bin magnitude means into a Bark domain to obtain a source frequency response curve (SR), where SR(i) corresponds to magnitude mean of the ith frequency bin; obtaining respective gains of frequency bins of the Bark domain with respect to a reference frequency response curve (Rf); obtaining equalizer parameters using the respective gains of the frequency bins of the Bark domain; and transforming the first portion to the reference timbre using the equalizer parameters.

Abstract: One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.

Abstract: An analog to digital converter temperature compensation system comprising a comparator configured to compare an analog input signal to a compensated feedback signal and generate a comparator output. A SAR module processes the comparator output to generate a digital signal. A digital to analog converter, biased by a biasing signal having temperature change induced error, is configured to convert the digital signal to a feedback signal and a detector is configured to detect a signal that is proportional to temperature. A look-up table is configured to receive and convert the signal that is proportional to temperature to a compensation signal such that the compensation signal compensates for the temperature change induced error in the biasing signal. A summing node combines the feedback signal with the compensation signal to create a compensated feedback signal.

Abstract: An AD converter is provided with a control unit including a calibration control unit that controls an operation for calibrating the control unit and a conversion control unit that controls an operation for converting a target input voltage into a digital signal; a reference voltage unit that outputs a reference voltage; and an integrating converter unit including an integrating unit that generates an integrated voltage by integrating a predetermined unit voltage, a comparator that has two inputs and compares the integrated voltage and an input voltage or a reference voltage Vref, and a crossbar switch that switches connections between the case where the integrated voltage is inputted to one of the inputs of the comparator and the input voltage or the reference voltage Vref is inputted to the other input and the case where the input voltage or the reference voltage Vref is inputted to one of the inputs of the comparator and the integrated voltage is inputted to the other input.

Abstract: A time-interleaved sampling system includes an input signal having a time-varying analog value and a plurality of samplers. Each sampler is operable in a hold mode and a track mode. In the track mode, the samplers track the analog value of the input signal. In the hold mode, each sampler holds a respective analog value of the input signal that a respective sampler tracked immediately before entering the hold mode. The samplers enter the track mode in a predetermined sequence. After a last sampler in the predetermined sequence enters the track mode, the predetermined sequence is repeated in a loop. At random intervals, a skipped sampler in the predetermined sequence is bypassed from entering the track mode.

Abstract: An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ith pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline.

Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

Abstract: A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors.

Abstract: According to various embodiments of the disclosure, a display may include a display panel including a first region in which first group subpixels are disposed and a second region in which second group subpixels are disposed, a converter group including converters respectively connected to subpixels included in the first group subpixels and the second group subpixels to transfer image data for output of specified content to the subpixels, a first group gamma circuit selectively connected to the converters to output a first grayscale voltage whose intensity is determined based on a plurality of binary bits, a second group gamma circuit selectively connected to the subpixels to output a second grayscale voltage whose intensity is determined based on a single binary bit, and a controller that controls selective connections between the first group gamma circuit and the converters and selective connections between the second group gamma circuit and the subpixels.

Abstract: An optical sensor arrangement comprises a photodiode (11) and an analog-to-digital converter (12). The analog-to-digital converter (12) comprises an integrator (13) having an integrator input (15) coupled to the photodiode (11), a comparator (14) having a first input coupled to an output of the integrator (13) and a digital-to-analog converter (39) coupled to a control terminal of the comparator (14).

Abstract: A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.

Abstract: The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample.

Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Abstract: A reference analog-to-digital converter (ADC) samples an input signal in parallel with sub-converters of a time-interleaved ADC. For each sub converter and for each of a plurality of output samples from the sub-converter, a calibration circuit determines whether the output sample from the sub-converter indicates an input signal polarity opposite that indicated by the reference ADC. For each such instance, a DC-offset sample is calculated as a difference between the output sample from the sub-converter and a target zero-crossing value for the sub-converter output. For each sub-converter, a series of DC-offset samples is filtered, to produce an average zero-crossing error for each sub-converter. This filtering may comprise a simple average, for example, or a moving average, a decaying filter, etc. Finally, a zero-crossing correction is applied for each of one or more of the sub-converters, based on the respective average zero-crossing error.

Abstract: The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.

Abstract: A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

Abstract: A method and an apparatus for determining and compensating respective harmonic distortions of digital to analog and analog to digital conversions are described. A signal from a digital to analog converter is passed through a plurality of calibration paths. Output signals from each calibration path, converted by an analog to digital converter, are analyzed in order to determine the harmonic distortions introduced by each side of the chain separately. One embodiment represents a digital sine generator which has harmonic distortions of its analog output continually compensated. Another embodiment compensates harmonic distortions introduced by an analog to digital converter in order to measure harmonic distortions of an analog signal precisely. Other embodiments are described and shown.

Abstract: An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the apparatus may include multiple, independent circuits to reduce or remove DC offset voltages from differential signals.

Abstract: An audio device is adapted to receive and process a digital audio signal and output an analog audio signal. The audio device includes an adder, a digital-to-analog conversion circuit, an amplifying circuit, a voltage detecting circuit and an offset compensating circuit. The voltage detecting circuit detects a supply voltage received by the amplifying circuit. The offset compensating circuit generates a DC offset compensation value according to the supply voltage. The adder adds the digital audio signal and the DC offset compensation value to output an added signal. The digital-to-analog conversion circuit converts the added signal into a converted analog audio signal. The amplifying circuit amplifies the converted analog signal to output an amplified analog signal. Accordingly, the audio device can reduce pop noise caused by a DC offset.

Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form.

Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

Abstract: Circuitry and techniques are described herein for performing accurate and low power conversion of an analog value into a digital value. According to some aspects, this disclosure describes a successive approximation register (SAR) analog to digital converter (ADC). According to some aspects the SAR ADC comprises an active integrator between a sample and hold stage and a comparator stage. The active integrator operates differently dependent on whether the SAR ADC is operated in a sample phase or a conversion phase. According to other aspects, the SAR ADC utilizes a ring oscillator-based comparator to compare a sampled analog input value to a plurality of reference values to determine a digital value representing the analog value.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

Abstract: A receiver circuit for an antenna array system (AAS) is disclosed. The receiver circuit (10) comprises a set of receivers (151-15p). Each receiver (151-15p) comprises a first TI-ADC (351) in a receive path of the receiver. The first TI-ADC (351) comprises a plurality of sub ADCs (A1-AM+N). Each receiver (151-15p) comprises a control circuit (40) configured to select which sub ADC (A1-AM+N) is to operate on what input sample based on a first selection sequence. The control circuits (40) in the different receivers (151-15p) in said set of receivers (151-15p) are configured to use different first selection sequences.

Abstract: An offset compensated differential amplifier employing a multi-tan h circuit comprising differential pairs coupled in parallel to compensate for an offset voltage of the output voltage in the offset compensation calibration mode is disclosed. The differential pairs each include a compensation transistor coupled to the positive internal node and a reference transistor coupled to the negative internal node. Each compensation transistor receives the compensation control voltage and each reference transistor receives a different reference voltage. The multi-tan h circuit generates an offset compensation voltage on the positive and negative internal nodes based on a difference between the compensation control voltage and the different reference voltages. The multi-tan h circuit comprises a larger linear range than a hyperbolic tangent current transfer function of a single differential pair.

Abstract: A measurement circuit for monitoring at least one parameter of an input signal received from an external signal source includes at least one first measurement element coupled to the input signal and configured to provide an initial measurement signal indicative of a respective one or more of the at least one parameter of the input signal. An analog to digital converter is coupled to receive a signal indicative of the analog output signal and a reference voltage and configured to generate a digital output signal representative of the analog output signal. A compensation circuit is responsive to an output of at least one second measurement element and to a reference signal to generate a compensation signal indicative of a difference between the output of the at least one second measurement element and the reference signal. A voltage level of the reference voltage is adjusted in response to the compensation signal.

Abstract: A system and method for suppressing aperture noise resulting from clock jitter associated with a Nyquist analog-to-digital converter (ADC) using self-referred time measurements are provided. The system comprises of a clock, a delay element, a time subtractor, a time-to-digital converter, a filter element, a first digital subtractor, an integrator, a differentiator, and a multiplier. Each of the delay element, time subtractor, time-to-digital converter, filter element, first digital subtractor, integrator, and multiplier is electrically connected in parallel with the ADC, which allows the clock to generate a clock signal that advances into the system and the ADC in order to isolate and suppress the noise aperture associated with the ADC. As such, the architecture of the system is configured to isolate and suppress aperture noise resulting from clock jitter associated with an analog-to-digital converter (ADC) to allow the output signal of the system be independent of the aperture noise.

Abstract: Techniques for use with an implantable medical device (IMD) reduce how often a first receiver of the IMD wakes up a second receiver thereof to reduce power consumption. A received message and/or a channel over which messages can be received is/are examined, and a value is adjusted based on results thereof. After being adjusted, the value is compared to a first threshold if the IMD is in a normal state, or compared to a second threshold if the IMD is in a noise state. If in the normal state, there is a determination whether to stay in the normal state or switch to the noise state. If in the noise state, there is a determination whether to stay in the noise state or switch to the normal state. At least the second receiver is temporarily put to sleep, if the IMD is maintained in or switched to the noise state.

Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.

Abstract: An asynchronous FIFO circuit of the present invention generates a write clock and a read clock from the same input clock, and generates a write control signal in synchronization with the write clock and a read control signal in synchronization with the read clock. The asynchronous FIFO circuit includes a data read-write unit having a plurality of data holding units. The data read-write unit writes data into one of the data holding units for each write clock on the basis of the write control signal, and reads data from one of the data holding units for each read clock on the basis of the read control signal.

Abstract: A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.

Abstract: The present invention includes a current integrator for an organic light-emitting diode (OLED) panel. The current integrator includes an operational amplifier, which includes an output stage. The output stage, coupled to an output terminal of the current integrator, includes a first output transistor, a second output transistor, a first stack transistor and a second stack transistor. The first stack transistor is coupled between the first output transistor and the output terminal. The second stack transistor is coupled between the second output transistor and the output terminal.

Abstract: Systems, apparatuses, and methods for performing hybrid non-linearity correction for a digital-to-analog converter (DAC) are described. A circuit includes two correction LUTs, an edge-trim DAC, and a DAC core. A lookup of a first correction LUT is performed using a portion of the most significant bits (MSBs) of a received digital input value. A first correction value, retrieved from the first correction LUT, is applied to the digital input value to generate a corrected value. The corrected value is provided to the DAC core and to a second correction LUT. A second correction value, retrieved from the second correction LUT, is compared to the first correction value. If the second correction value is different from the first correction value, the difference is provided to the edge-trim DAC to generate an analog correction which is applied to an analog output of the DAC core.

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

Abstract: This analog-to-digital converting device comprises: an input terminal for receiving the analog input signal; an output terminal for issuing the digital output signal; a first successive approximation register analog-to-digital conversion module, called first SAR ADC module, connected to the input terminal; a first feedback module associated to the first SAR ADC module; a second successive approximation register analog-to-digital conversion module, called second SAR ADC module, connected in a cascaded manner to the first SAR ADC module; a second feedback module associated to the second SAR ADC module; and a multiplexing module connected to the first and second SAR ADC modules, to deliver the digital output signal.

Abstract: A first calibration measures capacitor array mis-match and updates a Look-Up Table (LUT) with calibrated weights that are copied to both a positive LUT and a negative LUT, and then adjusted for non-linearity errors by a second calibration using a Least Mean-Square (LMS) method. The binary code in the Successive-Approximation Register (SAR) is complemented to generate a complement code with a sign bit. When the sign bit is positive, entries for complement code bits=1 are read from the positive LUT and summed, a first offset added, and the sum normalized to get a corrected code. When the sign bit is negative, entries for complement code bits=0 are read from the negative LUT and summed, a second offset added, and the sum normalized to get the corrected code. A Multi-Variable Stochastic Gradient Descent method generates polynomial coefficients that further correct the corrected code.

Abstract: A resampling circuit converts first data updated synchronously with a first clock signal into second data updated synchronously with a second clock signal asynchronous with the first clock signal and outputs the second data. The resampling circuit measures a first time interval between a plurality of successive edges of the first clock signal, and a second time interval between one of the plurality of edges of the first clock signal and an edge of the second clock signal, with a third clock signal having a higher frequency than the first clock signal and the second clock signal. The resampling circuit calculates and outputs the second data updated at the edge of the second clock signal, based on the first time interval and the second time interval, and a plurality of the first data updated at the plurality of edges of the first clock signal.

Abstract: An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.

Abstract: An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which utilizes a filtered output of the analog-to-digital converter that has less distortion errors than the unfiltered output of the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.

Abstract: An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Abstract: To detect air in a fluid delivery line of an infusion system, infusion fluid is pumped through a fluid delivery line adjacent to at least one sensor. A signal is transmitted and received using the at least one sensor into and from the fluid delivery line. The at least one sensor is operated, using at least one processor, at a modified frequency which is different than a resonant frequency of the at least one sensor to reduce an amplitude of an output of the signal transmitted from the at least one sensor to a level which is lower than a saturation level of the analog-to-digital converter to avoid over-saturating the analog-to-digital converter. The signal received by the at least one sensor is converted from analog to digital using an analog-to-digital converter. The at least one processor determines whether air is in the fluid delivery line based on the converted digital signal.