Abstract: Provided is a sensor terminal including a sensor element, the sensor terminal further including: an ADC that converts an analog signal output from a sensor element into a digital signal; a storage device in which a plurality of first storage setting numbers being information for controlling the ADC and a plurality of pieces of first characteristic information including description of operation of the ADC are stored in association with each other; and a communication device that receives a first reception setting number from the outside of the sensor terminal, and transmits the first characteristic information corresponding to the first storage setting number that coincides with the first reception setting number, to the outside of the sensor terminal.

Abstract: An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion inter

Abstract: There are provided: a table memory to store a relation between a control code and gains of variable gain amplifiers; a gain controller to apply the gains to the variable gain amplifiers; an amplitude phase detector to detect amplitude and a phase from an output signal of the vector sum phase shifter; an amplitude phase recorder to record, when the gains are applied by the gain controller, a combination of a control code corresponding to said gains and the amplitude and the phase detected by the detector; and a table calibrator to find a phase shift characteristic of a vector summed part from records of the amplitude phase recorder and calibrate the relation between a control code and gains recorded in the table memory by using the phase shift characteristic.

Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.

Abstract: A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.

Abstract: Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.

Abstract: A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

Abstract: A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

Abstract: The invention relates to a digital amplifier for providing a desired electrical output power, the amplifier comprising a power source (100) for generating the electrical output power, the amplifier further comprising: a digital input adapted for receiving a digital input signal (112), the digital input signal (112) representing the desired electrical output power level, a reference power generator (124) for generating an analogue reference power controlled by the digital input signal (112), a power measurement component (142; 128) adapted for measuring the power differential between the electrical output power provided by the power source (100) and the analogue reference power, an analogue-to-digital converter (130) adapted for converting the power differential into a digital power differential value (132), a combiner adapted for providing a combined digital signal (136) by adding the digital power differential value (132) to the digital value input to the reference power generator (124) for generating the

Abstract: Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a gradient-based optimization approach or other such optimization approach to determine optimized gain error calibration data to compensate for gain mismatch in and between individual parallel time-interleaved ADCs and to determine time-offset calibration data to compensate for timing errors in and between individual parallel time-interleaved ADCs. For example, once a calibration signal is applied to an ADC, the output of the ADC can be analyzed to determine a spectrum of the calibration signal. One or more images (e.g., phasors) of the spectrum can be determined and used to determine initial values of the optimization.

Abstract: Methods and devices are provided where a first current and a second current are provided selectively to a semiconductor component, and times for charging a capacitor to a voltage at the semiconductor component are provided.

Abstract: Disclosed herein are systems for calibrating an analog-to-digital converter (ADC) device, as well as related devices and methods. In some embodiments, a system for calibrating an ADC device may include an ADC device, wherein the ADC device includes an ADC and a dither source, and wherein the ADC device is to apply a set of calibration parameters to generate digital outputs. The system may also include calibration circuitry, coupled to the ADC device, to determine which of multiple sets of values of calibration parameters results in the digital outputs having the lowest amount of noise, and to cause the ADC device to apply the calibration parameters associated with the lowest noise.

Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

Abstract: A temperature sensor is disclosed. The temperature sensor includes an analog core having at least first and second circuit nodes and configured to provide a temperature dependent output, a multiplexer coupled to the first and second circuit nodes and configured for at least first and second states in each of which the first circuit node couples to a different circuit element and in each of which the second circuit node couples to a different circuit element, and a controller coupled to the analog core and configured to provide a temperature measurement that is an average of at least first and second readings of the temperature dependent output of the analog core, the first reading taken while the multiplexer is in the first state, and the second reading taken while the multiplexer is in the second state.

Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.

Abstract: A voltage regulator has a comparator and a reference voltage coupled to a first input of the comparator. An output voltage of the voltage regulator is coupled to a second input of the comparator through a resistor. A current source is coupled to the second input of the comparator. The first current source can be a first digital-to-analog converter (DAC). A second current source can be coupled in parallel with the first DAC. The second current source can be a second DAC. The voltage regulator can include a boost topology.

Abstract: Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and in combination with a sensor array, forms a digital focal plane array.

Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Abstract: A calibration method includes the following: providing a first charge quantity to a first input terminal of a comparator; providing a second charge quantity to a second input terminal of the comparator by one of multiple switch capacitor groups, and providing a compensation charge quantity to the second input terminal of the comparator by at least another one of the switch capacitor groups; comparing a voltage value received by the first input terminal and a voltage value received by the second input terminal, and outputting a voltage comparison result to a controller; and if the controller determines the charge quantity provided to the second input terminal approximates to the charge quantity provided to the first input terminal based on the voltage comparison result, recording a calibration charge quantity in a lookup table stored by the controller. An analog-to-digital converter and a calibration apparatus are also provided.

Abstract: An integrated circuit includes a digital logic circuit having a first transistor and a second transistor, a replica circuit having a first transistor and a second transistor which replicate the first transistor and second transistor of the digital logic circuit, and a storage circuit configured to store a static state indicator. The circuit also includes a comparison circuit configured to compare threshold voltages of the first and second transistor of the replica circuit, and having an output coupled to provide the static state indicator to the storage circuit, and a selection circuit configured to provide the state indicator to an input of the digital logic circuit and an input of the replica circuit during a lower power mode and to provide a run mode signal instead of the state indicator to the input of the digital logic signal and the input of the replica circuit during a high power mode.

Abstract: The present invention relates to a system for acquisition of at least one physical variable, in particular for a critical on-board avionics system, comprising a sensor for measuring the physical variable; an acquisition channel receiving an analog signal corresponding to the physical variable measured by the sensor and transforming this analog signal into a corresponding digital signal, at least some of these transformations being able to be carried out with loss of accuracy; self-test unit for checking the integrity of the acquisition channel and generating a self-test result. The system further comprises an analyzer analyzing the self-test result in order to determine an operating mode of the acquisition channel, and for activating the operation of means for correcting the signal delivered by the channel.

Abstract: Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component.

Abstract: An example apparatus includes a windowing component. The windowing component may set a first voltage level as an upper bound for a voltage window and set a second voltage level as a lower bound for the voltage window. The windowing component may modulate an input signal to have a maximum magnitude less than the upper bound for the voltage window and a minimum magnitude greater than the lower bound for the voltage window.

Abstract: Disclosed are circuits for automatic calibration of the gain of electronic amplification and digitization systems for use with X-ray detectors. The calibration is based on injecting predetermined pulses into the electronic system and deriving a calibration ratio based the digital value of their amplitude with the digital value of the same pulses, unamplified and digitized with a high accuracy reference ADC. All ADCs, as well as the DACs used to control the pulser amplitude are referenced to a single common reference voltage. Calibration for non-linearity of the gain is disclosed with an alternative embodiment for the same circuits.

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

Abstract: A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

Abstract: A method that includes deriving a first power spectral density function of a signal input to a ripple cancellation filter; deriving a second power spectral density function of a signal concurrently output from the ripple cancellation filter; frequency shaping the first power spectral density according to a spectral rejection image of the ripple cancellation filter to obtain a test power spectral density; and indicating a degraded performance of the ripple cancellation filter in the event that the test and second power spectral density functions fail to match within pre-determined criteria.

Abstract: Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

Abstract: The invention relates to a method for processing high speed analog signals in real time, characterized in that it comprises the following steps: a) high speed analog signals are provided to the microprocessor (1), b) using a high speed ADC converter (2) integrated in said microprocessor (1), these signals are quantized and converted to digital form without further processing, c) the digital data thus acquired is sent via an interface (3), in particular a high speed interface, and an input data busbar (4), to a high speed signal processing unit (5), d) said digital data is processed in the high speed signal processing unit (5) in line with the processing feature (6) implemented in said unit (5), e) the processing result is sent via an interface (7), in particular a high speed interface, and an output data busbar (8), to the microprocessor (1), f) the microprocessor (1) is used to perform operations on the processed data received in line with the program (9) implemented in this microprocessor (1).

Abstract: Systems, methods, and circuitries are provided to control a gain setting in an analog-to-digital converter (ADC) that converts an analog signal to a digital signal based on a reference voltage. Temperature compensation circuitry includes a temperature gain correction circuitry and a combination circuitry. The temperature gain correction circuitry is configured to determine a correction term based on a temperature that affects the reference voltage. The combination circuitry is configured to combine the correction term with a calibration gain value to generate a corrected calibration gain value and provide the corrected calibration gain value to the ADC to control the gain setting.

Abstract: Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

Abstract: A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA comprises a USB accessory port. The ACA bridge circuit comprises detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller that, if not ignored, would cause the PHY to drive the VBUS pin.

Abstract: An analog video signal supply circuit includes a processing circuit that supplies first and second digital video signals. First and second digital-to-analog converters convert digital signals to analog signals. A control circuit controls operation in a first configuration where the first digital video signal is applied to an input of the first digital-to-analog converter and the second digital video signal to an input of the second digital-to-analog converter. The control circuit further controls operation in a second configuration where the first digital video signal is simultaneously applied to the inputs of the first and second digital-to-analog converters.

Abstract: A delta-sigma modulator circuit comprising: an integrator circuit configured to produce an integrator output signal that represents an integration of an analog input signal, a comparator output signal and a periodic signal; a comparator circuit configured to produce the comparator output signal in response to a comparison of the integrator output signal with a first reference signal; and a periodic signal generation circuit configured to produce the periodic signal.

Abstract: A method involving a serial interconnection system having a first node, a second node, a plurality of calibration nodes that are electrically connected in series by the serial interconnection system, and a plurality of connection nodes corresponding to the plurality of serially connected calibration nodes and electrically connected in series by the serial interconnection system, the method involving: for each of the plurality of calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, determining a summation of the phases of signals appearing at the first and second nodes; from the determined phase summations for the plurality of calibration nodes, computing phase corrections for each of the plurality of calibration nodes; and applying the phase corrections to the corresponding plurality of connection nodes.

Abstract: A four-level pulse amplitude modulation transmitter and corresponding method are provided. The transmitter includes a most significant bit processing section and a least significant bit processing section. The transmitter further includes at least one termination resistor connected to respective outputs of the processing sections to provide a transmitter output. Each of the processing sections include a set of retiming latches arranged in a parallel for aligning input parallel data and providing parallel aligned latched outputs responsive to one phase of a quarter-rate four-phase quadrature clock. Each of the processing sections further includes a serializer for serializing the parallel aligned latched outputs to provide a serialized output using quarter-rates of the quarter-rate four-phase quadrature clock. Each of the processing sections also include an output driver for driving the serialized output.

Abstract: A method for measuring a voltage using a capacitive voltage divider (CVD) and an analog-to-digital converter includes the steps of measuring a bandgap or reference voltage and determining a first code value of the bandgap or reference voltage, charging a first capacitor to a voltage to be measured and determining a second code value of voltage of the first capacitor, charging a second capacitor to a second known voltage and determining a third code value of voltage of the second capacitor, and determining the voltage to be measured by applying the first, second, and third code values.

Abstract: A control system easily adjusts devices. In a control system, an input unit included in a PLC system obtains actual sampling data. An output unit outputs an output signal based on output instruction data including a designated output timing and a designated output signal value. A task execution unit included in a controller repeatedly executes a task in a predetermined period. A sampling unit obtains variable sampling data. A same time-series data generation unit included in a development support apparatus generates same time-series data. A same time-series data display unit displays the same time-series data on the same time axis.

Abstract: Methods and systems are provided for spreading spectral density of digital-to-analog conversion output signals. A spreading circuit may spread a digital-to-analog converter (DAC) output signal over a particular frequency spectrum, with the spreading circuit receiving the DAC output signal; generating a plurality of internal control signals; and generating based on the DAC output signal and the one or more internal control signal a corresponding spread output signal. The Internal control signals may comprise at least a first control signal, generated based on sequences meeting at least one particular criterion, a second control signal, generated based on a feedback corresponding to an intermediate output generated within the spreading circuit. The spreading circuit may generate the first control signal based on zero-sum sequences. The spreading circuit may generate a stream of pulses based on the intermediate output, and may generate the feedback signal based on the stream of pulses.

Abstract: An online gamma adjustment system of liquid crystal panel is disclosed. The system includes a port receiving a gamma encoding for adjusting from an external gamma adjustment device, and generating an enable signal; a storage device storing the gamma encoding for adjusting received by the port according to a voltage level status of the enable signal; a controller selectively reading the gamma encoding from the storage device according to voltage level status of the enable signal; and a gamma register receiving the gamma encoding read by the controller, outputting a gamma voltage corresponding to the gamma encoding read by the controller in order to drive a liquid crystal panel.

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

Abstract: A transceiving circuit, which comprises: a transmitting circuit, configured to transmit a test signal; a receiving circuit, comprising a mixer configured to receive a plurality of predetermined DC bias voltage groups, wherein the receiving circuit generates a plurality of output signals according to the test signal while the mixer operates at the predetermined DC bias voltage groups; a frequency domain analyzing circuit, configured to transform the output signals to a plurality of frequency domain signals; and a DC bias voltage generating circuit, configured to generate a function according to the frequency domain signals and the predetermined bias voltage groups, and configured to generate a first DC bias voltage group to the mixer according to the function.

Abstract: Embodiments of the present invention may provide a receiver. The receiver may include an RF section, a local oscillation signal generator to generate quadrature local oscillation signals, and a quadrature mixture, coupled to the RF section, to downconvert a first group of wireless signals directly to baseband frequency quadrature signals and to downconvert a second group of wireless signals to intermediate frequency quadrature signals. The receiver may also include a pair of analog-to-digital converters (ADCs) to convert the downconverted quadrature signals to corresponding digital quadrature signals. Further, the receiver may include a digital section having two paths to perform signal processing on the digital baseband frequency quadrature signals and to downconvert the digital intermediate frequency signals to baseband cancelling a third order harmonic distortion therein.

Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

Abstract: A low order filter circuit having a frequency correction function, a frequency correction method for a low order filter circuit, and a high order filter circuit are provided. An analog to digital converter (ADC) may detect a peak of a signal processed by a second order filter unit, and after comparison and determination are performed by a digital correction unit, a frequency control signal is outputted as a feedback to a notch filter or a band-pass filter in the second order filter unit where frequency adjustment is performed. The high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.

Abstract: Systems and method for increasing current monitor accuracy are disclosed. The systems and methods may include receiving a run-time load value from a current monitor, determining a component parameter value associated with the run-time load value, and communicating the component parameter value to the current monitor.

Abstract: Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.

Abstract: A method for adjusting a sensor, continuous sensor or automatic measuring system in an interstitium including the steps of adjusting the steepness of a measuring curve and a standard offset (standard axis intercept) prior to the use of the sensor, continuous sensor or measuring system, and adapting the offset by a point calibration by using a reference measure or value during the use. The present invention encompasses sensors, continuous sensors or automatic measuring systems calibrated or adjusted in accordance with the method, and in some embodiments, the offset adjusted prior to use is rectified according to the difference between a value determined by the sensor, continuous sensor or measuring system taking into account the standard steepness and the reference value.

Abstract: A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler's number as the base, and in a further phase has a profile of a falling exponential function with Euler's number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.