Abstract: A circuit for digital-to-analog conversion includes a first digital-to-analog converter (DAC), a second DAC, and an output node. The first DAC provides charges from multiple first charge sources segmented into a first group for most significant bits of a digital input to the first DAC and a second group for least significant bits of the digital input. Dither is both added to the digital input to the first DAC and used as sole digital input to the second DAC. Analog output from the second DAC is subtracted from analog output of the first DAC at the output node so as to cancel the dither added to the first DAC.

Abstract: A self-capacitance input device with hovering touch includes a sensing electrode layer, a reflection and deflection electrode layer, an insulation layer, and an amplifier with a gain greater than zero. The sensing electrode layer has a plurality of sensing electrodes on one side for sensing a touch or approach of an external object. The reflection and deflection electrode layer is disposed on the other side of the sensing electrode layer and has at least one reflection and deflection electrode. The insulation layer is disposed between the sensing electrode layer and the reflection and deflection electrode layer. The amplifier has an output coupled to the reflection and deflection electrode layer.

Abstract: A method of processing an input voltage. The method includes, during a sampling phase, using a digital-to-analog converter (DAC) capacitor to sample a reference voltage. The method includes, during a charge redistribution phase, using an input voltage to charge the DAC capacitor.

Abstract: A processing system, and associated input device and method are disclosed suitable for reducing a receiver size within the input device. The processing system comprises a delta-sigma modulator comprising one or more input nodes configured to receive a signal based on a sensor signal received from at least a first sensor electrode of the plurality of sensor electrodes. The delta-sigma modulator further comprises an integrator coupled with the one or more input nodes and configured to produce an integration signal, a quantizer coupled with an output of the integrator and configured to quantize the integration signal, and a feedback digital-to-analog converter (DAC) controlled based by the quantizer. The processing system further comprises a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

Abstract: A D/A converter converts digital audio data DIN into analog differential audio signals VP and VN. A differential to single-ended conversion circuit converts the differential audio signals VP and VN into a single-ended audio signal VSE. A volume circuit receives the single-ended audio signal VSE, and amplifies the single-ended audio signal VSE with a gain that corresponds to a volume value. A reference voltage source generates a reference voltage VREF commonly referred by the differential to single-ended conversion circuit and the volume circuit. In a calibration operation, a calibration circuit controls the D/A converter so as to shift at least one from among the differential audio signals VP and VN such that the difference between the output voltage VSE of the differential to single-ended conversion circuit and the reference voltage VREF approaches zero.

Abstract: A circuit (100) comprises an input terminal (141) which is configured to receive an analog input signal (142). The circuit (100) also comprises a combination element (601) which is configured to combine a number of time-displaced signal values of the input signal (142) to form an analog combination signal (144). The circuit (100) also comprises a quantizer (131) having a converter core which is configured to receive the combination signal (144) via passive charge redistribution from the combination element (601) and to convert it into a digital output signal (145). Such techniques can thus provide for an analog/digital conversion with filtering in the analog domain.

Abstract: Disclosed herein are systems and methods for compressing data and for estimating sparsity of datasets to aid in compressing data. A device receives a plurality of samples of the sensor data from the sensor and determine a plurality of bits, in which each bit has a substantially equal probability of being determined as a 0 bit or of being determined as a 1 bit. The device estimates a sparsity value of the sensor data based at least in part on the sequence of bits. The device compresses the received samples of the sensor data based at least in part on the determined sparsity value to provide compressed data and transmits the compressed data via the transmitter to a receiver. Sparse data other than sensor data may also be compressed based at least in part on an estimated sparsity value.

Abstract: In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures.

Abstract: In an analog-to-digital converter (ADC) having storage capacitors, active, top-plate, n-type, switch circuitry has an n-type transistor and gate-voltage control circuitry that generates the gate voltage to turn on and off the transistor. The control circuitry turns off the transistor by generating the gate voltage at a level that limits the gate-to-source voltage difference, thereby limiting GISL leakage current through the transistor that can otherwise jeopardize the accuracy of the ADC digital output value. In one implementation, when the transistor is to be off (for example, during the ADC conversion phase), the control circuitry generates the gate voltage to be at ground if the source voltage is below a reference voltage, and above ground if the source voltage is above the reference voltage. The switch circuitry can also be implemented using a p-type device or a transmission gate instead of the n-type device.

Abstract: A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub-ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

Abstract: Distortion in a combined sample and hold circuit and multiplexer can be reduced by dividing the sample and hold circuit and the multiplexer up into main and compensation signal channels, and considering the total error signal that arises during an acquire phase across both the switches of the multiplexer and the input switches of the sample and hold stage as a single error signal that has to be compensated. This compensation is then achieved by causing the same error voltages to be induced in both the main and compensation channels of the whole MUX and sample and hold circuit, such that errors can be made to cancel, thus improving the performance of the stage.

Abstract: A method, apparatus, and system for measuring and analyzing the effects of dynamics modifying processors on a signal. This new approach utilizes statistical analysis techniques to provide a direct comparison and evaluation between the processed signal and the unprocessed signal's dynamic characteristics. The method identifies and quantifies Effective Dynamic Range, Clip Tolerance, Lower Limit Tolerance, Crest Factor, and Diminuendo Factor, using either peak or r.m.s values. In an alternative embodiment, the invention allows for user adjustment and control of the relative relationship of Crest Factor and Diminuendo Factor, which the user may perceive as loudness.

Abstract: A method for testing a DAC comprising controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

Abstract: A layout method for a current source array. A digital-to-analog converter (DAC) includes a plurality of complementary metal-oxide-semiconductor (CMOS) devices. Current sources for the CMOS devices are uniformly arranged in a one-dimensional array. The spacing between the current sources in the one-dimensional array is determined using a golden ratio.

Abstract: A digital to analog converter convert digital data in binary format to thermometer bit vectors. A first set of the thermometer bit vectors corresponds to most significant bits of the digital data and a second set of the thermometer bit vectors corresponds to least significant bits of the digital data. Connections of first current sources corresponding to the first set of the thermometer bit vectors and second current sources corresponding to the second set of the thermometer bit vectors are dynamically and randomly alternated to a first output line and a second output line. Calibration current is applied to the second current sources so a total current of the second current sources and the calibration current is within a predetermined range of an average current of the first current sources.

Abstract: A method of detecting whether a foreign object is near a transmit coil in a wireless power transfer system (WPTS), the method involving: applying a pseudo-random signal to the transmit coil; while the pseudo-random signal is being applied to the transmit coil, recording one or more signals produced within the WPTS in response to the applied pseudo-random signal; by using the one or more recorded signals, generating a dynamic system model for some aspect of the WPTS; and using the generated dynamic system model in combination with stored training data to determine whether an object having characteristics recognizable from the stored training data as characteristic of the foreign object is near the transmit coil.

Abstract: A passive radiometric system for thermally imaging objects in a scene. The system includes a digital square-law quantizer circuit including a plurality of comparators and a voltage divider network having a plurality of resistors. Each comparator receives a different reference signal generated by the voltage divider network and a common power signal from an antenna and outputs a high or low digital bit signal. The system also includes a delta-sigma circuit having a weighting table responsive to the digital bit signals from the comparators that converts the digital bit signals to a normalized bit word. The delta-sigma circuit also includes an accumulator that receives the digital bit words from the weighting table and provides an average of the digital bit words. The system also includes a digital-to-analog converter that converts the averaged bit words to an analog signal that is provided as a feedback signal to the quantizer circuit.

Abstract: A radio frequency (RF) transmit system includes an observation receiver coupled to receive a portion of an RF signal propagating along an RF transmit signal path and a digital pre-distortion (DPD) system coupled to the observation receiver and configured to receive one or more signals from the observation receiver and in response thereto, to adapt one or more DPD values of the RF transmit system over a period of time and a range of operating conditions of the RF transmit system and to provide one or more adapted DPD values to said controller.

Abstract: Digital to analog converters (DAC) are used to convert digital signals to analog values. The digital system providing data to the analog converter may be highly tasked. A DAC is provided with some in built logic to assist in reducing the load on the devices driving the DAC. The DAC may include a library of functions that it can apply to the input words to modify transitions in the analog output words. The DAC may further include a health checking system for monitoring the digital words being supplied to the DAC and raising a concern, and taking action if required, if the sequence of words is unlikely to be correct or beyond the target operating range.

Abstract: Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.

Abstract: A method of determining Integral Non-Linearity (INL) of an Analog-to-Digital Converter (ADC) is provided. The method includes providing an input signal to the ADC, phase-locking a clock signal of a clock of the ADC to the input signal, generating a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, applying averaging to the plurality of samples for each sampled phase to generate a reconstructed ADC output signal, and determining the INL of the ADC based on a comparison of the reconstructed ADC output signal to a theoretical ADC output signal.

Abstract: A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data.

Abstract: A method includes receiving a plurality of temperature measurements from temperature sensors of an aircraft. The method includes determining whether a first count of one or more first temperature metrics that are within a temperature range is greater than a first threshold. The one or more temperature metrics are derived from the plurality of temperature measurements. The method includes initiating generating an icing output signal when the first count is greater than or equal to the first threshold.

Abstract: A digital-to-analog converter includes an adder having a plurality of inputs and an output coupled to the output of the converter. The converter further includes a plurality of digital-to-analog (DAC) elements, each DAC element has an output coupled to an input of the adder, and each DAC element has a DAC element input. A plurality of comparators have outputs coupled to a DAC element input. A first input of each comparator is coupled to the input of the converter. A second input of each comparator is selectively coupled to one of a predetermined voltage and a pseudo-random bit sequence (PRBS[n]).

Abstract: An analog-to-digital converter (ADC) circuit including error correction circuitry for correcting offset drifts in an ADC, such as a successive approximation register (SAR) ADC. The offset drifts can be reduced, such as by sampling the offset following an analog-to-digital conversion and subsequently providing an error correction signal based on the sampled offset.

Abstract: A four-level pulse amplitude modulation transmitter and corresponding method are provided. The transmitter includes a most significant bit processing section and a least significant bit processing section. The transmitter further includes at least one termination resistor connected to respective outputs of the processing sections to provide a transmitter output. Each of the processing sections include a set of retiming latches arranged in a parallel for aligning input parallel data and providing parallel aligned latched outputs responsive to one phase of a quarter-rate four-phase quadrature clock. Each of the processing sections further includes a serializer for serializing the parallel aligned latched outputs to provide a serialized output using quarter-rates of the quarter-rate four-phase quadrature clock. Each of the processing sections also include an output driver for driving the serialized output.

Abstract: A charge-redistribution successive approximation ADC includes: a comparator, generating a comparison result; a register, storing a digital output code, determining a bit value of the digital output code according to the comparison value; a control unit, generating a control signal according to the digital output code; a plurality of first capacitors, each including a first end and a second end, the first end coupled to a first input end of the comparator; at least one second capacitor, including a third end and a fourth end, the third end coupled to the first input end of the comparator. Before the voltages of the second end of each first capacitor and the fourth end of the second capacitor are switched, the second end is coupled to a first voltage and the fourth end is coupled to a second voltage different from the first voltage.

Abstract: A method and system of an analog to digital conversion having an exponential result are provided. An analog input signal is received by the ramp ADC. The analog input signal is converted into an N-bit digital signal having a linear relationship with the analog input signal. An internal gated clock signal is generated based on the received first clock signal. The gated clock signal is used as an input to an M-bit register. An output of the M-bit register is multiplied by a predetermined factor. The product of the multiplication is provided as an input to the M-bit register. The output of the M-bit register provides an M-bit output having an exponential relationship with the analog input signal.

Abstract: A measurement device according to one aspect of the present invention includes a first controller configured to output a control signal and a second controller configured to perform a first control and then to perform a second control based on the control signal output from the first controller. The control signal designates both an input signal and a calibration signal to be converted into a digital input signal and a digital calibration signal, respectively. The input signal is input from an outside of the measurement device. The calibration signal is previously prepared. The first control is for selecting the input signal and converting the selected input signal into the digital input signal.

Abstract: Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.

Abstract: A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.

Abstract: A digital to analog conversion, DAC, device for converting digital signals to analog signals comprises a RF output for outputting the analog signals, a thermometer segment comprising a first number of data slices and a second number calibration slices, and a calibration controller, which electrically disconnects one of the data slices from the RF output and at the same time connects one of the calibration slices to the RF output as replacement slice for the respective data slice and performs a calibration of the disconnected data slice.

Abstract: A system comprising a processor is programmed to receive, from a plurality of vehicles, sets of diagnostic test data relating to a performed diagnostic test. Each set of diagnostic test data includes a test output value and one or more corresponding test condition values. The processor is further programmed to select some of the test output values based on selecting a function to relate the test output value to test output values from different sets of diagnostic data. The processor is further programmed to provide the test output value and the corresponding test conditions values as input to the selected function to obtain a plurality of scaled test output values; and generate an adjustment to the diagnostic test based at least in part on the scaled test output values.

Abstract: A capacitive sensing system operates according to a method which uses an ADC. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L?1, of the quantization step size of the ADC. The saw-tooth or triangular signal has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M?N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.

Abstract: A method for use in testing an analog-to-digital converter. The method includes providing a set of bins, varying a voltage, taking samples of the voltage, providing a selection flag, associating each sample with one bin of the set of bins, and observing a number of samples associated with the bins. An apparatus includes an analog-to-digital converter configured to convert a voltage at an input node to a digital representation provided at an output node. The input node is configured to be coupled to a voltage generator. A sample select unit is configured to determine if a voltage at the input node at least equals a first threshold level and does not exceed a second threshold level. The apparatus is configured, based on the determining, to selectively associate the digital representation with a bin of a set of bins.

Abstract: Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

Abstract: A self-healing data converter system including a data converter; a parametric function module coupled to the data converter to receive a target performance requirement for a data converter and produce a set of function values to the data converter; an assistant module that captures data converter performance under one or more stress conditions; and a processing module coupled to the data converter to stress the data converter in accordance with one or more predetermined parameters and based on the target performance requirement and data converter performance, the processing module determines new parameters based on a self-healing method and applies the new parameters to produce a new set of function values for the data converter until a predetermined threshold is met to adaptively self-heal the data converter to changed conditions.

Abstract: A measurement device for detecting a material level and a temperature has a cable, a level sensing module, a thermal sensing module, a processing module, and a power module. The measurement device detects difference of currents between an electrode of the cable and the earth, and calculates a material level of a material stored in a silo according to the RF admittance. The cable comprises a plurality of thermal sensing units for detecting a temperature of the material. The measurement device further calibrates a material capacitance of the material with the temperature for avoiding an error caused by an inaccurate parameter.

Abstract: The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

Abstract: A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M ADCs, operating in a time-interleaved fashion, can increase the sampling speed several times compared to the sampling speed of just one ADC. The time-interleaved ADC can be programmed and reconfigured to trade one performance metric for another. For example, more time can be given to comparator to improve bit error rate or more time can be given to an amplifier for improved settling which improves SNR, SFDR etc. If the time-interleaved converters are randomized, then the amount of ‘color’ in the noise floor shape can also be traded for other performance metrics.

Abstract: Methods and apparatus for magnetic sensors and integrated calibration. In an example arrangement, a system includes a magnetic sensor configured to output a signal corresponding to magnetic fields; a calibration trace disposed proximal to the magnetic sensor; a controlled current source coupled to the calibration trace and configured to output a current resulting in a magnetic field output from the calibration trace; and a comparator coupled to the output signal from the magnetic sensor and to an expected signal. In the example arrangement, the comparator outputs a signal indicating whether the output signal from the magnetic sensor corresponds to the expected signal. Methods are also disclosed.

Abstract: A method may include processing an analog input signal with a first processing path configured to generate a first digital signal based on the analog input signal; processing the analog input signal with a second processing path configured to generate a second digital signal based on the analog input signal, and adapting a response of an adaptive filter configured to generate a filtered digital signal from the second digital signal to reduce a difference between the filtered digital signal and the first digital signal. The method may additionally or alternatively include determining nonlinearities present in the second processing path based on comparison of the first digital signal and the second digital signal, and applying a linear correction to the second digital signal to generate a corrected second digital signal with decreased nonlinearity from that of the second digital signal.

Abstract: This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.

Abstract: A successive approximation register analog-to-digital converter includes a capacitance digital-to-analog converter (CDAC) having, a voltage storing circuit connected to an output terminal of the CDAC and including a plurality of capacitors connected in parallel, an output voltage of the CDAC being stored in a selected one of the capacitors, a selector configured to output a voltage stored in the selected one of the capacitors, a comparator configured to compare a voltage input to an input terminal thereof, which is connected to an output terminal of the CDAC, with a reference voltage, and a successive approximation register configured to control the CDAC based on an output of the comparator, and cyclically control the voltage storing circuit and the selector, such that the output of the selector is output to the output terminal one or more cycles after the output voltage was stored in the selected one of the capacitors.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a ring oscillator configured to determine a frequency based on a sampling clock signal and a first control code, and generate an output clock signal having the determined frequency. The SAR ADC further includes a controller configured to generate the first control code based on a count value indicating a number of times of toggling the output clock signal.

Abstract: A method of detecting whether a receiver coil is near a transmit coil in a wireless power transfer system (WPTS), the method involving: applying a pseudo-random signal to the transmit coil; while the pseudo-random signal is being applied to the transmit coil, recording one or more signals produced within the WPTS in response to the applied pseudo-random signal; by using the one or more recorded signals, generating a dynamic system model for some aspect of the WPTS; and using the generated dynamic system model in combination with stored training data to determine whether an object having characteristics distinguishing the object as a receiver coil is near the transmit coil.

Abstract: In accordance with an embodiment, a method of operating an oversampled data converter having a switched-capacitor (SC) integrator includes operating the oversampled data converter in a gain calibration mode; applying a first voltage to a feedback port of the SC integrator to form a feedback voltage, and during a first clock phase the method further includes applying the first voltage to a first series capacitor via the input port when an output of the oversampled data converter is in a first state; applying a bypass voltage to the first series capacitor when the output of the oversampled data converter is an a second state and applying the first voltage to a second series capacitor via the feedback port with a polarity based on the output of the oversampled data converter, and during a second clock phase the method includes integrating charges of the first series capacitor and the second series capacitor.

Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

Abstract: A method is provided for calibrating a device under calibration (DUC) for optimizing performance of the DUC.