Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.

Abstract: A multi-input analog to digital converter (“ADC”) to accept and process multiple inputs. The analog multiplexer is integrated with an amplifier chopper circuit to form a high precision, temperature stable, ADC circuit with multiple inputs.

Abstract: There is provided a signal processor with a plurality of antennas connected for transmitting and receiving wireless signals, including a plurality of analog reception processing units, AD converters, DA converters, and analog transmission processing units, wherein each of the analog reception processing units converts the wireless signal received through the antenna into an analog baseband signal and outputs the signal to the AD converter, each of the DA converters converts the digital baseband signal into analog format and outputs the signal, and each of the analog transmission processing units shifts the frequency band of the analog baseband signal output from the DA converter to the high frequency side. The signal processor further includes a transmission switch which switches among the DA converters respectively connected to the analog transmission processing units and a reception switch which switches among the AD converters respectively connected to the analog reception processing units.

Abstract: A physical layer (PHY) device includes a first encoder that receives a first data stream at a first data rate, that encodes the first data stream using a first type of encoding, and that outputs first encoded data. A second encoder receives a second data stream at a second data rate different than the first data rate, encodes the second data stream using a second type of encoding different than the first type of encoding, and outputs second encoded data. An output selector outputs the first encoded data to a serializer of the PHY when the PHY transmits at the first data rate, and outputs the second encoded data to the serializer when the PHY transmits at the second data rate.

Abstract: An A/D conversion circuit includes an amplifier circuit that includes a plurality of amplifiers that are cascaded, a selector that selects one of output signals output from the plurality of amplifiers and outputs the selected output signal as a selector output signal, an A/D converter that A/D-converts the selector output signal output from the selector, a determination circuit that determines whether or not a voltage of the output signal output from each of the plurality of amplifiers is within a determination voltage range specified by a high-potential-side determination voltage and a low-potential-side determination voltage, and a control circuit that instructs the selector to select one of the output signals output from the plurality of amplifiers based on the determination result of the determination circuit.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Abstract: To avoid the measurement disturbances occurring in a conventional, multi-channel measurement data acquisition apparatus there is proposed a multi-channel measurement data acquisition apparatus which includes at least one analog input assembly having a plurality of analog inputs, a controllable electronic analog signal switch device (12) and a central controllable analog-digital converter, wherein the channels of the analog inputs can be successively switched through by means of the analog signal switch device so that the analog signals at the inputs of the individual channels are successively applied as input signals to the central analog-digital converter, and wherein the electronic analog signal switch device and/or the analog-digital converter have control inputs connected to associated control lines.

Abstract: Systems and methods for processing a plurality of input signals are provided. A plurality of selection signals are received. Each of the plurality of selection signals is representative of one of a plurality of input signal characteristics. Each of the input signal characteristics is associated with one of the plurality of input signals. The plurality of input signals are converted into at least one digital waveform. A plurality of signal values may be extracted from the at least one digital waveform based on the plurality of input signal characteristics. An output signal may be generated based on each of the plurality of signal values.

Abstract: The present invention relates to an electronic device for analog-to-digital conversion including a sigma-delta modulator (SD), a digital filter (FIL) for digital post processing of the output signal of the sigma-delta modulator (SD), a multiplexer (MUX) for switching the input (INSD) of the sigma-delta modulator between a first input signal (IN1) and a second input signal (IN2), a memory (MEM) adapted to hold the register content of the digital filter relating to the first input signal while the second input signal (IN2) is processed in the digital filter, and a controller (CNTL) to retrieve the register contents from the memory (MEM) when processing of the first input signal (IN1) in the digital filter is resumed.

Abstract: A mixed signal integrated circuit device, e.g., digital-to-analog converter (DAC), has a serial interface communication protocol that accesses volatile and/or non-volatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered-up. However, unlike conventional DACs, DACs with non-volatile memory may need special interface communication protocols for effective operation of the DAC and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non-volatile memories of the DAC so that the MCU may access the DAC's memories (non-volatile and/or volatile memories). The mixed signal integrated circuit device has a user programmable address.

Abstract: An amplifier for amplifying a pulse-like signal output from a secondary side of an isolating transformer, a capacitor connected to a negative feedback loop across the input and output of the amplifier, and a timing control circuit for controlling an FET into a closed state, then controlling a switch into a closed state, and after that controlling the switch into an open state at timing simultaneously with the FET or earlier than the FET are provided, and when the switch is controlled into the open state, an AD converter converts the output signal of the amplifier to a digital signal.

Abstract: Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak.

Abstract: A method reading bank register values is provided. Register values are stored in a readback bank. The register values are output sequentially from the serial bank. An indicator is received by the serial bank. A determination is then made as to whether the indicator was received by the serial bank prior to completion of the outputting of the register values. If the indicator was received prior to completion of the outputting of the register values, the register values are loaded into the serial bank from the readback bank.

Abstract: The manufacturing yield of an A/D converter semiconductor chip is significantly increased by utilizing a number of A/D converter circuits that include a group of redundant A/D converter circuits. As a result, the semiconductor chip can be wired to form a “good” A/D converter semiconductor chip as long as the number of “bad” A/D converter circuits does not exceed the number of redundant A/D converter circuits.

Abstract: A method for operating a time-interleaved analog-to-digital converter for converting an analog input to a digital output using a time-interleaved analog-to-digital converter, wherein the time-interleaved analog-to-digital converter comprises an array of M sub ADCs (ADC1, ADC2, . . . , ADCM), where M is an even integer, and each row of the array comprises one of the M sub ADCs. The method comprises the step of, for every sampling instant n, where n is an integer in a sequence of integers, converting the analog input by means of the sub ADC in row k(n) of the array, wherein 1?k(n)?M. A value between 1 and M is assigned to k(n) for the first sample instant, and k(n+1) is selected such that a) k(n+1)>M/2 if k(n)?M/2, otherwise k(n+1)?M/2; b) M/2?1?|k(n+1)?k(n)|?M/2+1; and c) k(n+1)=k(m+1) if and only if n?m is an integer multiple of M. A time interleaved analog-to-digital converter operating in accordance with the method is also disclosed.

Abstract: There is provided a demodulator system comprising a first input to receive a first analog signal at a first rate; a second input to receive a second analog signal at the first rate; a MUX coupled to the first input and the second input to receive the first analog signal and the second analog signal, and to multiplex the first analog signal and the second analog signal to generate a multiplexed analog output; an ADC to receive the multiplexed analog output and generate a multiplexed digital output, the ADC operating at a second rate, the second rate substantially equal to the first rate multiplied by a total number of input analog signals; a DEMUX to receive the multiplexed digital output and generate a first digital output having a first bitstream and a second digital output having a second bitstream corresponding to the first analog signal and the second analog signal.

Abstract: A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Abstract: A data converter includes multiple analog to digital converters (ADCs) and uses a reduced number of data ports at the digital interface for transferring signal samples. The bits of the signal samples generated in parallel by the ADCs are multiplexed into fewer data streams than the number of ADCs. The data ports transfer the data streams at a higher data transfer rate than the bit rate of the samples output from the ADCs. Unused data ports are powered down, decreasing power consumption and system complexity. A host device receives the data streams using fewer input data ports and demultiplexes the received data streams to reproduce the signal samples. Efficient data transfer to a data converter including multiple digital to analog converters (DACs), from a source device generating multiple digital signals can also use fewer data ports having higher data transfer rates.

Abstract: A system for multi-channel analog-to-digital conversion has a plurality of sampling modules, wherein each of the modules includes an input node and an output node; multiplexing circuitry configured to selectively route at least one of a plurality of electrical signals present on the output nodes to an analog-to-digital converter; and control circuitry in communication with the multiplexing circuitry, wherein the control circuitry is programmatically configured to control a sequence in which the electrical signals are routed to the analog-to-digital converter.

Abstract: A system comprising an radio frequency (RF) signal input; a plurality of time-skewed, undersampled analog to digital converters (ADCs); a plurality of complex finite input response (FIR) filters in parallel, wherein each complex FIR filter receives the output beam and/or band provided by the plurality of ADCs and generates a corresponding output beam of a given frequency.

Abstract: A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.

Abstract: An A/D converter performs successive A/D conversion operations that are synchronized with respective periods of an externally supplied clock signal. A set of output digital data produced from the A/D converter, following each A/D conversion, is acquired a plurality of times in succession within an interval that extends to the start of the next A/D conversion operation. If identical sets of data are not obtained in the successive acquisitions, then it is determined that there is failure of the A/D converter due to loss of the external clock signal.

Abstract: A selection circuit is used for detecting analogue signals from different inputs. For the detection of a signal switched through by means of the selection circuit, a delay time during the detection of the switched-through signal is set depending on the occurrence of a setting operation in the selection circuit. The selection circuit can have a plurality of switches each having an assigned delay time and the detection can be controlled in such a way that it does not take place until after the elapsing of the delay times of all the involved in switching through the analogue signal to be detected.

Abstract: The present invention comprises a circuit for transferring N inputs, wherein N is greater than or equal to 2, across a capacitive coupling media comprising a line circuit, a coupling capacitor, and a neutral potential circuit. The line circuit comprises: (1) a data converter for each input, for sampling and converting the N inputs; (2) a multiplexer for combining the outputs of the N data converters and a synchronization signal to generate an unencoded composite bit stream; (3) a data encoder for encoding the composite bit stream. The capacitor couples the encoded composite bit stream to a data decoder. The neutral potential circuit comprises: (1) the data decoder for decoding the coupled composite bit stream, and generating a recovered data stream and a recovered clock; (2) a synchronization recovery, control logic, and de-multiplex function for providing a set of digital outputs that correspond to the inputs to the data converters.

Abstract: A current-steering type digital-to-analog converter (DAC) is disclosed. The DAC includes a first sub-DAC, a second sub-DAC and a controlling device. Both the first sub-DAC and the second sub-DAC are configured to receive input signals. The controlling device selectively and periodically sends output signals of either the first sub-DAC or the second sub-DAC to a resistive load while sending output signals of the remaining one of the two sub-DACs to a dummy resistive load. An output of the DAC is provided at the resistive load.

Abstract: The present invention comprises a circuit for transferring N inputs, wherein N is greater than or equal to 2, across a capacitive coupling media comprising a line circuit, a coupling capacitor, and a neutral potential circuit. The line circuit comprises: (1) a data converter for each input, for sampling and converting the N inputs; (2) a multiplexer for combining the outputs of the N data converters and a synchronization signal to generate an unencoded composite bit stream; (3) a data encoder for encoding the composite bit stream. The capacitor couples the encoded composite bit stream to a data decoder. The neutral potential circuit comprises: (1) the data decoder for decoding the coupled composite bit stream, and generating a recovered data stream and a recovered clock; (2) a synchronization recovery, control logic, and de-multiplex function for providing a set of digital outputs that correspond to the inputs to the data converters.

Abstract: An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.

Abstract: An A/D conversion apparatus performs motor current detection in an A/D conversion period corresponding to two phases out of three phases of a sinusoidal drive motor, using reduced register resources while minimizing the number of A/D converters. The A/D conversion apparatus includes: a selection unit selecting one of a plurality of input channels; an A/D converter converting an analog signal from the selected input channel to a digital signal; a start register holding a start channel number of sequential conversion; an end register holding an end channel number of the sequential conversion; a prohibition information holding unit holding prohibition information indicating an input channel to be excluded from the sequential conversion; and a control unit causing the selection unit to select, in channel number order, input channels corresponding to channel numbers from the start channel number to the end channel number except the input channel indicated by the prohibition information.

Abstract: A method for configuring a circuit for providing a power OK (POK) signal is described. The method includes identifying a voltage range and voltage interval, dividing the voltage range into a plurality of segments, selecting a reference voltage for each segment, and selecting resistor values for a plurality of voltage dividers for dividing an output voltage from a precision voltage reference into each of the reference voltages. A power OK signal generator and method for generating a power OK signal are also described.

Abstract: A signal-processing unit according to the present invention comprises: an input line provided with a plurality of analog input signal lines; a multiplexer circuit transmitting the plurality of analog signals from this input line to one signal line in the subsequent stage in a desired sequence; an analog-digital conversion circuit that converts an analog signal into a digital signal and outputs it; and a cross talk compensation circuit that with respect to each of signals having been sequentially outputted from the analog-digital conversion circuit, a coefficient of an effect level between this signal and the other plural signals interfering with each other is calculated, and data obtained by multiplying the signals by these coefficients are added up.

Abstract: A time-interleaved analog-to-digital conversion apparatus is disclosed. The time-interleaved analog-to-digital conversion apparatus is applied for a television system and includes an input multiplexing module, a gain multiplexer and an analog-to-digital converter. The input multiplexing module receives a plurality of image signals, and samples the image signals according to a clock signal to generate a sample multiplexing signal. The gain multiplexer receives a plurality of gain signals and selectively transmits one of the gain signals corresponding to the sample multiplexing signal according to the clock signal, so as to generate a gain multiplexing signal. The analog-to-digital converter receives the sample multiplexing signal, the gain multiplexing signal and the clock signal. The analog-to-digital converter amplifies and converts the sample multiplexing signal to a digital signal according to the gain multiplexing signal and the clock signal.

Abstract: A measurement processing apparatus is disclosed for processing plurality of physiology signals. The measurement processing apparatus includes a multiplex device, an analog-to-digital conversion module and a control signal generator. The multiplex device generates a multiplex signal composed of the physiology signals with output sequence controlled by a first control signal. Furthermore, the multiplex device dispenses each physiology signal with one corresponding multiplex density based on the first control signal. The analog-to-digital conversion module converts the multiplex signal into a digital multiplex signal based on at least one adjustable bias voltage under control of a second control signal. The control signal generator generates the first control signal based on the feature values of the physiology signals. Also, the control signal generator generates the second control signal based on the voltage swing ranges of the physiology signals.

Abstract: Interface unit for voltage input signals comprising two or more input channels. The input signals of these two or more input channels are connected alternately by an analog multiplexer to an analog-to-digital converter. The A/D converter comprises an integrated sigma-delta modulator circuit which generates a digitized 1-bit signal representing the input signal voltage level for a control unit irrespective of whether the input channel signal is digital or analog. By means of the invention all input voltage channels are made similar such that the input channels of the interface unit can receive an analog or digital signal irrespective of each other.

Abstract: A method of converting a plurality of input signals on first and second converters, such that the first and second converters are both used when the plurality of signals comprises two signals, characterised in that said method comprises: selecting more than two input signals; determining the type of each selected signal; combining any signals having the same type to form a combined signal; converting one type of signal with the first converter; converting a second type of signal with the second converter wherein the first or second type signals is a combined signal.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit.

Abstract: A multi-channel sample and hold circuit includes an operational amplifier, plural electric charge setting channels. Each of the electric charge setting channels includes an input terminal, an electric charge setting capacitor, an electric charge setting switch connected between the input terminal and the electric charge setting capacitor, a channel separating switch connected between the electric charge setting capacitor and the input terminal of the operational amplifier and a holding switch and a control circuit for selecting one of the electric charge setting channels to hold a signal that is inputted to the input terminal thereof.

Abstract: A data converter includes multiple analog to digital converters (ADCs) and uses a reduced number of data ports at the digital interface for transferring signal samples. The bits of the signal samples generated in parallel by the ADCs are multiplexed into fewer data streams than the number of ADCs. The data ports transfer the data streams at a higher data transfer rate than the bit rate of the samples output from the ADCs. Unused data ports are powered down, decreasing power consumption and system complexity. A host device receives the data streams using fewer input data ports and demultiplexes the received data streams to reproduce the signal samples. Efficient data transfer to a data converter including multiple digital to analog converters (DACs), from a source device generating multiple digital signals can also use fewer data ports having higher data transfer rates.

Abstract: There are provided in a scanning mode: a conversion sequence setting register (12) that sets the sequence in which analogue signals are to he converted; a multiplexer (1) that selects a single analogue signal (AI) sequentially from a plurality of analogue signals (AI0) to (AIn-1), in accordance with the order that is set in this conversion sequence setting register (12); an A/D converter (2) that converts the analogue signal (AI) selected by this multiplexer (1) to a digital signal (DO); a conversion result register (3) having a plurality of result registers (RR0) to (RRn-1), that stores the digital signal (DO) obtained by conversion by the A/D converter (2) in these storage regions in the order in which conversion was effected; and a back-up register (21) having result registers (BRR0) to (BRRn-1) respectively corresponding to this plurality of result registers (RR0) to (RRn-1).

Abstract: An integrated circuit includes at least one analog input. A sample/hold circuit is coupled to the at least one analog input. A reconfigurable delta-sigma ADC is coupled to the sample/hold circuit. A field programmable gate array is coupled to the reconfigurable delta-sigma ADC. A configurable on-chip clock source is coupled to the reconfigurable delta-sigma ADC providing control and reprogrammable oversampling ratio.

Abstract: An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section.

Abstract: A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.

Abstract: An analog-to-digital conversion apparatus includes an interleaving section that aligns the digital data respectively output from a plurality of analog-to-digital conversion sections and generates a data sequence, and a correction arithmetic section that corrects a data value error caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, in which the correction arithmetic section includes: a data partitioning section that generates a plurality of partition data by partitioning the data sequence, a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data, an arithmetic section that sequentially outputs data after correction made by sequentially performing correction arithmetic on the partition data, and a data connecting section that adds sequentially connects the data after correction and the data after correction following the data aft

Abstract: A data converter (10) for digitizing an analog input signal and providing digital output data at one or more conversion cycles includes a logic circuit (28) for generating a data conversion diagnostic bit (38) having first and second logical states. The data conversion diagnostic bit toggles from one logical state to the other logical state when a conversion cycle is completed and when the digital output data from the previous conversion cycle has been read. The data conversion diagnostic bit remains at the same logical state when no conversion cycle has been completed or when no reading of the digital output data has been carried out.

Abstract: An analog to digital converter (ADC) structure and method includes a photonic filter bank having at least two filters. The at least two filters are configured to create a corresponding spectral tributary from an input signal at a target rate, and the at least two filters are configured to exhibit orthogonality properties between respective tributaries. An optical/electrical (O/E) converter is coupled to each of the at least two filters in a respective spectral tributary to convert an optical input to an electrical output. An analog to digital converter (ADC) is coupled to each of the O/E converters in a respective spectral tributary to sample the electrical output at a fraction of a target rate and to convert a sampled analog electrical output into a digital signal. A synthesis filter is coupled to each of the ADCs in a respective spectral tributary to reconstruct the input signal digitally at the target rate.

Abstract: A signal processing system having different power domains is provided. The signal processing system has a first amplifier circuit operating under a first power domain; a second amplifier circuit operating under a second power domain and having a feedback configuration; a first impedance unit, coupled between an output node of the first amplifier circuit and a first input node of the second amplifier circuit; and a bias current generating circuit, coupled to the first input node of the second amplifier circuit, for providing a bias current to thereby reduce a DC current flowing through a feedback path of the second amplifier unit.

Abstract: An A/D conversion processing circuit includes: a switch sequentially switching over multiple inputs to select each thereof according to input bandwidth of the multiple inputs or fixedly selecting a single input; an A/D converter obtaining a digital signal through sampling on a switch output with a sampling frequency according to a necessary signal bandwidth; an interpolation section performing on each signal from a separation section which separates signals included in an A/D converter output, an interpolation processing according to a sampling timing deviation in the A/D converter, to obtain a signal where the multiple inputs are digitally converted at the same sampling timing; and an output section outputting as-is an output of the A/D converter if a signal of the single input is inputted to the A/D converter from the switch, thereby allowing commonly using a single A/D converter for multiple inputs, restraining increased circuit scale and power consumption.

Abstract: A mixed signal device, e.g., digital-to-analog converter (DAC) device has a serial interface communication protocol that accesses volatile and/or nonvolatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered-up. However, unlike conventional DAC devices, DAC devices with non-volatile memory may need special interface communication protocols for effective operation of the DAC device and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non-volatile memories of the DAC device so that the MCU may access the DAC device's memories (non-volatile and/or volatile memories).

Abstract: According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

Abstract: The invention relates to an integrated circuit (1) which comprises a novel bidirectional mixed signal single-wire interface (6) via which the circuit receives command information from a host and transmits conditioned analog signals to the host. In order to implement the mixed signal interface, the integrated circuit is provided with means for analog signal conditioning (2), command detection (3), and digital control (4). In a preferred embodiment of the invention, current detectors are used for command detection and respond to the current flowing through the interface connection (6) so that commands can be given even when analog signals are present on the bus. The invention relates to several methods of operation, especially methods for operating a plurality of the integrated circuits on the same mixed signal bus, and methods for the compatible operation with conventional integrated circuits.

Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.