Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs; and by a delay of 1/fs. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.

Abstract: Techniques for reducing precision timing message uncertainty are described herein. A method includes resetting an elastic buffer of a first device in response to a second device linked with the first device sending SKIP (SKP) ordered sets to the first device. The method also includes initiating a PTM handshake with the second device in response to resetting the elastic buffer. Additionally, the method includes sending PTM messages to the second device immediately after receiving the SKP ordered sets.

Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

Abstract: There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.

Abstract: A controller for controlling a power converter includes an analog-to-digital converter (ADC) configured to output, based on a received analog voltage, a first digital value defined by a first resolution. The controller also includes a digital filter configured to adjust, based at least in part on the first digital value, a second digital value, wherein the second digital value is defined by a second resolution different from the first resolution. The controller further includes a pulse modulation device configured to output, based on a sum of the first digital value and the second digital value, a pulse modulated signal, wherein a frequency of the pulse modulated signal is defined by the second resolution.

Abstract: An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.

Abstract: A method and apparatus for processing an audio/video file. By determining an audio/video file to be processed and then determining loadable audio/video promotion information for the audio/video file according to at least one of attribute information about a target user and attribute information about the audio/video file, the disclosed embodiments can carry out a merge operation on the audio/video file and the audio/video promotion information.

Abstract: An apparatus for combining input signals produced by a plurality of electric musical devices includes a plurality of audio buses and a plurality of segments. Each segment includes input circuitry configured to receive at least one input signal from at least one electric musical device and to deliver the at least one input signal to one of the plurality of audio buses; a plurality of variable adjustment devices each associated with a corresponding one of the audio buses and each configured to change at least one property of an input signal received by another of the plurality of segments and carried on the corresponding one of the audio buses independent from input signals carried on other of the plurality of audio buses; and a mixer configured to combine the input signals carried on each of the plurality of audio buses into an output signal.

Abstract: An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.

Abstract: A touch display module, a driving method thereof and a source driver are provided. The touch display module includes a touch display panel and at least one source driver. The source driver is coupled to a plurality of data lines of the touch display panel. In a display mode, the source driver respectively outputs a plurality of pixel driving signals to the data lines for driving the touch display panel to display a corresponding image. In a touch mode, the source driver clusters the data lines into multiple groups, and respectively outputs a plurality of touch driving signals to the groups. The data lines belonging to a same group are provided with a same touch driving signal in the touch mode.

Abstract: A current sense circuit for a PWM driver comprises: a PWM control circuit comprising: a first switching device arranged to receive a PWM signal from the PWM driver whose current is to be sensed; and a second switching device whose supply current is arranged to track the sensed current of the PWM driver. An ADC is operably coupled to the first and second switching device. The ADC comprises: a DAC arranged to provide a current sense to the second switching device that tracks the current passing through the PWM driver; a first comparator arranged to receive and compare an output current from the DAC and an output current from the first switching device; and a first successive approximation register arranged to receive an output from the comparator and provide: a first output to the ADC; and a second output that provides a representation of the sensed current.

Abstract: A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.

Abstract: An example programmable multichannel data converter includes a multiplexer having a plurality of input channels, an output and a channel selector input, a converter having an input coupled to the output of the multiplexer, and a controller having a user-configurable memory stack and control circuitry, the controller having a channel selector output coupled to the multiplexer.

Abstract: A switch circuit includes: a sampling transistor including a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.

Abstract: A method and apparatus are configured to receive at a control input of an analog to digital converter (ADC) circuit, from a control output of a control circuit, a first instance of control information that indicates a conversion characteristic of the ADC, wherein the conversion characteristic is one of a first conversion rate and a first conversion resolution, to provide at a status output of the ADC status information regarding the conversion of a first analog signal by the ADC circuit, to receive at the control input of the ADC a second instance of the control information that adjusts the conversion characteristic to allocate a first portion of an ADC circuit bandwidth of the ADC circuit to continuing receiving the first analog signal and to allocate a second portion of the ADC circuit bandwidth to receiving a second analog signal.

Abstract: The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.

Abstract: Systems and techniques for digital processing of FM stereo signals are described. According to an aspect, a method includes determining whether a received digital signal is a mono signal or a stereo signal, using a digital signal processor to process the received digital signal based on stereo transmission when the received digital signal is determined to be a stereo signal, and using the same digital signal processor to process the received digital signal based on mono transmission when the received digital signal is determined to be a mono signal.

Abstract: A system includes an analog to digital converter (ADC) that samples an analog input signal as received by a first channel of a plurality of channels, samples the analog input signal as received by at least a second channel of the plurality of channels, and outputs a plurality of digital samples including a first set and a second set of digital samples of the analog input signal corresponding to the first channel and the second channel, respectively. A filter receives the first and second sets of digital samples, up-samples each of the first and second sets of digital samples, filters the up-sampled first set of digital samples and the up-sampled second set of digital samples, and outputs a first digital output signal and at least a second digital output signal based on the filtered first set of digital samples and the filtered second set of digital samples, respectively.

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract: A method for reading the state of a plurality of contact variables (Var-1, Var-i, Var-n) of a motor vehicle by a read module (MOD) including a plurality of read ports (P1, Pi, Pn) connected by an electric circuit to the plurality of contact variables, each read port being configured to read the state of a contact variable, the read module being configured to order periodically the reading of the contact, a period including a read interval (Ton) and a sleep interval (Toff), includes a step of detecting a current (?i=1nIinj_i) injected via the electric circuit across at least one of the read ports during a sleep interval and a step of adapting the period in which the contact variables are read by the read module, such that the detected current (?i=1nIinj_i) injected during a sleep interval is consumed by the read module during the consecutive read interval.

Abstract: A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation.

Abstract: A method implemented by an electronic entity including a nonvolatile rewritable memory and a read-only memory, the method comprising: reception of at least one write command for writing to the nonvolatile memory, and en response to the command, writing configuration data to the nonvolatile memory, wherein the configuration data are obtained based on so-called prerecorded data read in the read-only memory.

Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

Abstract: A CMOS image sensor includes a plurality of pixel elements arranged in a two-dimensional array, analog signal multiplexers, over-sampling A/D converters and an activation code generator. The sensor is configured to construct an image by using less number of A/D conversions, thereby reducing the power consumption of the sensor. The activation code generator generates a bit stream of random binary sequences which determine which A/D converter is activated. The image sensor offers digitally compressed data, the number of which is significantly less than the total number of pixels. Further, the image sensor not only reduces the power consumption of the A/D converters (by reducing the number of A/D conversions) but also reduces the I/O power consumption. An original image focused on the sensor is recovered from the compressed data by using principles of compressed sensing.

Abstract: A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and has an output terminal to output an output signal. The output buffer circuit receives the gray level voltage and the output signal, and compares the gray level voltage and the output signal to generate a comparison result. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal to the output terminal of the output buffer circuit according to the comparison result and a pre-charge enable signal.

Abstract: Certain embodiments herein describe filtering signals or channels using a programmable bandwidth filter. Each channel may be filtered according to a different bandwidth such that noise may be removed from each channel without the need to increase the complexity of an anti-aliasing filter, for example. In one embodiment, the programmable filter may be a decimation filter that may be coupled to a delta sigma modulator, which may sample an analog channel according to a programmable sampling rate to generate a digital representation of the analog channel. In one embodiment, multiple analog channels may be multiplexed and subsequently sampled and filtered by the delta sigma modulator and decimation filter, respectively. According to various embodiments, the above processing may be performed by an application specific integrated circuit (ASIC), a microcontroller, or a computing device including one or more software programs and/or modules.

Abstract: The various technologies presented herein relate to generating copies of an incoming signal, wherein each copy of the signal can undergo different processing to facilitate control of bandwidth demands during communication of one or more signals relating to the incoming signal. A signal sharing component can be utilized to share copies of the incoming signal between a plurality of circuits/components which can include a first A/D converter, a second A/D converter, and a comparator component. The first A/D converter can operate at a low sampling rate and accordingly generates, and continuously transmits, a signal having a low bandwidth requirement. The second A/D converter can operate at a high sampling rate and hence generates a signal having a high bandwidth requirement. Transmission of a signal from the second A/D converter can be controlled by a signaling event (e.g., a signal pulse) being determined to have occurred by the comparator component.

Abstract: A method for minimizing an inrush current in a power supply selector and a power supply selector system is provided. The power supply selector includes a plurality of power input nodes, a power output node, a first transistor and a second transistor. Each of the power input nodes may be coupled to a first switch having a first on-resistance and to a second switch having a second on-resistance. The second on-resistance is greater than the first on-resistance. The first switch and the second switch are preferably coupled in parallel. The power supply selector may be configured to couple a selected one of the power input nodes to the source of the first transistor and to the gate of the second transistor so as to sense a sense voltage at the selected power input node.

Abstract: A voltage supply circuit is provided. The voltage supply circuit includes a voltage amplifier and a power selecting circuit. A power terminal of the voltage amplifier receives an operation power and outputs a gain voltage for driving an output device. The power selecting circuit receives a plurality of supply voltages and supplies one of the supply voltages to the power terminal of the voltage amplifier as the operation power according to a volume level of an audio signal. An audio output apparatus and a voltage supplying method thereof are also provided. The audio output apparatus includes the voltage supply circuit and a speaker.

Abstract: A time-to-digital converter includes a first gated ring oscillator, a second gated ring oscillator, a phase adjusting unit, and a digital converter unit. The first gated ring oscillator includes a plurality of first delay cells connected in a cyclic structure and operating in response to an enable signal. The second gated ring oscillator includes a plurality of second delay cells connected in a cyclic structure and operating in response to the enable signal. The phase adjusting unit adjusts a phase of a second circulation signal circulating in the second gated ring oscillator so as for the second circulation signal to have a predetermined phase difference with respect to a first circulation signal circulating in the first gated ring oscillator. The digital converter unit samples output signals of the first delay cells and the second delay cells to output a digital value corresponding to duration of the enable signal.

Abstract: An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.

Abstract: There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Abstract: A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

Abstract: The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a conversion range and is small in conversion error.

Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs.

Abstract: Methods and systems are provided for performing sampling sequences using a control module. One exemplary method involves transferring sampling configuration information for a sampling sequence from memory to a conversion module. The conversion module performs the sequence in accordance with the configuration information by performing sampling processes at a plurality of sampling times to obtain a plurality of samples, and transferring results corresponding to the plurality of samples from the conversion module to the memory. At least some sampling times of the plurality of sampling times are nonperiodic with respect to the other sampling times of the plurality of sampling times. In exemplary embodiments, the sampling configuration information includes a sampling mode criterion, and the conversion module either automatically performs a sampling process or performs the sampling process in response to a trigger signal based on the sampling mode criterion for that sampling process.

Abstract: A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output.

Abstract: The present invention is applicable to the field of communication, and provides an analog digital data conversion method, an analog digital data convertor and an analog digital conversion chip. The method includes: converting multiple groups of analog data to multiple groups of digital data; performing frequency shift on the multiple groups of digital data, wherein the multiple groups of frequency shifted digital data are independently distributed within a first preset bandwidth; filtering the multiple groups of frequency shifted digital data to remove outband information; and distributing without overlap the filtered multiple groups of digital data within a second preset bandwidth. The method substantially reduces pressure of data transmission between the converter and an FPGA or ASIC, and effectively simplifying the design of a multiband receiver.

Abstract: Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

Abstract: The disclosure relates to analog to digital converters, in particular to logical circuit blocks, a system and a method, which provide functionality of an additional analog to digital converter. In accordance with an aspect of the disclosure, there is provided a logical circuit block, which is configured to be connected to a plurality of ADCs each including a plurality of input pins connected to a plurality of analog input channels. The logical circuit block is further configured to cause one ADC of the plurality of ADCs to perform an ADC conversion of an analog input signal received via a particular analog input channel of the plurality of analog input channels to which an input pin of the one ADC is connected.

Abstract: The present invention is applicable to the field of communication, and provides an analog digital data conversion method, an analog digital data convertor and an analog digital conversion chip. The method includes: converting multiple groups of analog data to multiple groups of digital data; performing frequency shift on the multiple groups of digital data, wherein the multiple groups of frequency shifted digital data are independently distributed within a first preset bandwidth; filtering the multiple groups of frequency shifted digital data to remove outband information; and distributing without overlap the filtered multiple groups of digital data within a second preset bandwidth. The method substantially reduces pressure of data transmission between the converter and an FPGA or ASIC, and effectively simplifying the design of a multiband receiver.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.

Abstract: A system can include a first section with an ultra high speed digital sampler configured to sample at a first rate, a scrambler connected to the sampler, and a set of ultra high speed serial data outputs. The system can further include a second section with a set of ultra high speed serial data inputs, a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate, a descrambler having inputs connected to the reduced speed data outputs, and a set of parallel outputs configured to output the serial data. The set of ultra high speed serial data outputs of the first section are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.

Abstract: An A/D converter has an analog multiplexer stage which selects one of a plurality of first analog signals as a second analog signal, an amplifier stage which amplifies the second analog signal to generate a third analog signal, an A/D conversion stage which converts the third analog signal into a digital signal, and a sequencer which controls those stages. The sequencer performs input switching processing in the analog multiplexer stage on completion of sample hold processing by the A/D conversion stage, when performing a plurality of times of A/D conversion processing sequentially, without waiting for completion of the A/D conversion processing.

Abstract: A system for processing data streams or signals includes a wave-front multiplexer configured to process first and second input signals into first and second output signals each carrying information associated with the first and second input signals, a first processing unit configured to process a third input signal carrying information associated with the first output signal into a third output signal, a second processing unit configured to process a fourth input signal carrying information associated with the second output signal into a fourth output signal, and a wave-front demultiplexer configured to process fifth and sixth input signals into fifth and sixth output signals each carrying information associated with the fifth and sixth input signals. The fifth input signal carries information associated with the third output signal, and the sixth input signal carries information associated with the fourth output signal.