Abstract: A method and apparatus wherein raw video and audio are captured and digitized and stored at a frame rate different from the playback stand frame rate. The audio and the video are separated, the video as a frame and the audio as a data stream wherein there are time links to the video frame. The playback entails multiplexing the video and the audio, and where the multiplexer is operating at the standard frame rate synchronization is not maintained. The present invention discloses modifications of the audio header and/or data to accommodate the differences in the multiplexing frame rate and the original capture frame rate. If the originating frame rate is one half the standard then the audio header information is changed to indicate that twice as much audio information exists, whereupon the multiplexer will take the video frames and properly multiplex the proper and therefore synchronized audio data.

Abstract: A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A semiconductor device for receiving analog input signals includes a microprocessor for processing signal information. The microprocessor is put in a sleep mode when not called upon to process signal information, and is either left in that mode or awakened depending on the level of a continuously variable analog input signal relative to a programmed threshold level. If the relative levels of the analog input signal and the programmed threshold level result in the microprocessor being awakened, information contained in the analog input signal is processed to initiate a selected action. In typical applications, the semiconductor device performs a control function, such as to control the operation of an external circuit in response to information from at least one continuously variable analog input signal derived from the external circuit. The microprocessor, when awakened, assists in controlling the external circuit to restore that analog input signal to a predetermined level distinct from the threshold level.

Abstract: A digital-to-analog converter (200) has a first portion (208) which receives a digital input signal X (201') and has serially coupled a second portion (209) which provides an analog output signal Y (202'). The first portion (208) is a delta-sigma modulator with integrators (210 and 215), adders (203 and 205), a comparator (220) and delay stages (230 and 235). The second portion (209) comprises a commutator (260), unit converters (280-n) and an analog adder (290). In the second portion, the unit converters (280-n) can be mismatched. The first portion (208) provides a noise-shaped intermediate signal V (221') which has substantially zero noise at that frequencies where the mismatches would lead to unwanted spectral tones.

Abstract: Various sensor signals of an engine are A/D-converted by an A/D converter of a sub-microcomputer by an A/D conversion request from a main microcomputer. The A/D conversion is executed a plurality of times within one packet for important parameters in the various sensor signals in the A/D conversion request timing per constant time with a longer time interval than a time required for the A/D conversion by an A/D conversion request timing asynchronous to the A/D conversion request. Thereby, normal ones among a plurality of A/D-converted values A/D-converted by the A/D conversion request of the main microcomputer even if the preceding A/D conversion request is issued asynchronously to the A/D conversion request of the main microcomputer.

Abstract: A method of processing audio input signals comprising 1-bit, Sigma-Delta Modulated (SDM) signals is disclosed including the steps of combining the audio input signals to form a combined audio input signal; and utilising a Sigma-Delta Modulator to convert the combined audio input signal to a corresponding Sigma-Delta Modulated output signal. The method can include a linear mix of the audio input signals and each audio input signal can multiplied by a corresponding gain factor before being added together with other of the audio input signals. The Sigma-Delta Modulator can include a noise shaping filter designed to amplify components of the audio input signals below a predetermined threshold frequency and the combining step can include utilising a negative feedback of the combined audio input signal. The noise shaping filter can utilise a series of integrating circuits as a means to decrease the sensitivity of the filter to errors in its coefficients.

Abstract: Multi-channel recording system for audio signals comprising a general purpose computer (13) having a sound card (18) with two analog-to-digital converters (20, 22) for receiving two analog audio signals and recording these signals into digital form into a memory, and comprising an analog multiplexer (10, 12) arranged to combine a plurality n of input audio signals in analog form and to supply two resulting multiplexed signals (14, 16) to the analog-to-digital converters (20, 22), the computer (13) being arranged to function as a digital de-multiplexer (28, 30) for recovering the input audio signals in digital form and recording them into memory.

Abstract: An analog/digital converter where input analog signals are successively converted into digital signals under a time sharing control system; the analog/digital converter includes an integrating portion, a plurality of integrated calculus memory portions, a signal digitalizing portion, a feedback analog signal generating portion, and a switching portion. According to the disclosed analog/digital converter, input analog signals for a plurality of channels or input analog signals for highly-ordered integrating processes can be converted into digital signals without making the size of the circuit large.

Abstract: A high speed and low power D/A converter which is capable of accurately outputting an analog value and implementing a high speed operation by reducing noise and errors during the conversion. The converter includes an upper current cell plate for forming analog voltages from a 126th level to a 255th level in accordance with decoding of inputted digital values by a first column decoder and a first row decoder, a lower current cell plate for forming analog voltages from a 0th level to a 125th level in accordance with decoding of the inputted digital values by a second column decoder and second row decoder, and a multiplexer for selectively outputting the analog voltage from the upper current cell plate or the lower current cell plate in accordance with a binary bit value of a most significant bit (MSB) of the inputted digital signal.

Abstract: A radio selective call receiver includes an instruction input device which produces an analog input signal and a radio receiver which receives a radio signal and demodulating it to produce an analog demodulated signal whose amplitude varies in a symbol period. A selector selects one of the analog input signal and the analog demodulated signal and is connected to an A-D converter. The A-D converter is shared between the analog demodulated signal and the analog input signal. An A-D conversion of the analog demodulated signal is performed at intervals synchronizing with the analog demodulated signal. An A-D conversion of the analog input signal is performed within a time period during which the analog-to-digital conversion of the analog demodulated signal is not performed.

Abstract: A capacitively-coupled successive approximation analog-to-digital converter utilizes a capacitively coupled multiplying digital to analog converter to generate a succession of voltages which are compared to the input voltage to be digitized. The capacitively coupled multiplying digital to analog converter generates the required succession of analog voltage levels utilizing very low power in response to digital signals. A double-sided version of the invention processes differential inputs with improved common-non-ideality mode rejection.

Abstract: An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis.

Abstract: In a semiconductor device, one ends of capacitors connected via switching elements to multiple-input terminals, the other ends of the capacitors being connected in common to an input terminal of a sense amplifier. A first power source is provided for supplying a power to the switching elements, and a second power source is provided for supplying a power to the sense amplifier. The first and second power sources are independent and separate.

Abstract: A current mode track and hold(T/H) circuit is provided having a high degree of accuracy. The current mode T/H circuit includes an input node, and output node, a voltage controlled current source, and a switched integretor circuit. The input node is configured to receive an input analog current signal and a feedback current provided by the voltage controlled current source. The output node is configured to receive an output analog current signal generated by the voltage controlled current source. The feedback current is equal to the output current, and both are proportional to a control voltage generated by the switched integrator circuit. The switched integrator circuit operates in either a tracking mode or a holding mode in accordance with a received binary T/H control signal. In the tracking mode, charge produced by a difference between the feedback current and the input analog current is integrated by the switched integrator circuit.

Abstract: A multi-range analog-to-digital converter for encoding rundown times into a single channel of pulse width encoded data which may be conveyed to a remote equipment room over a single inexpensive, low quality digital cable. An input charge pulse is divided into multiple charge pulses and rundown times of the divided charge pulses are combined and encoded into a single channel of encoded data. A digital value representation of the input charge pulse is derived from the most accurate rundown times selected from the single channel of encoded data.

Abstract: A reduction in circuit size, an increase in operation speed, and a reduction in power consumption can be attained by a semiconductor device, in which capacitors are connected to multiple input terminals through switch, one terminal of each capacitance is commonly connected, and the common connection terminal is connected to a sense amplifier, including a reset at a floating point which is the contact between the common connection terminal of the capacitors and the input of the sense amplifier. In addition, an increase in yield can be realized by reducing the manufacturing cost.

Abstract: A digital signal processing method and apparatus in which no noise is produced when switching between an original sigma-delta modulated signal and a sigma-delta re-modulated signal obtained on sigma-delta modulation of the original sigma-delta modulated signal. In a digital signal processing device 1a, delay line 3 delays the original sigma-delta modulated signal from an input terminal 2 by a pre-set number of samples. A sigma-delta modulator 6 sets the first-stage feedback loop to next stage feedback loop gain ratio to an integer and outputs a sigma-delta re-modulated signal. A bit length converter 5 matcthes the amplitude level of the original sigma-delta modulated signal entering the sigma-delta modulator 6 to the amplitude level of a feedback signal to a first-stage integrator employed in the sigma-delta modulator 6. On reception of a switching control signal S.sub.

Abstract: A multi-channel integrated circuit, which includes N processing channels and a functional circuit which is time-shared between each of the N channels for processing data in accordance with a first clock strobe. Also included is a time-division multiplexed bus for providing synchronized data to and receiving synchronized data from said circuit in accordance with a second clock strobe. The data are thereby processed within said shared circuit in synchronization with said first and second clock strobes.

Abstract: A/D and D/A converters are effectively utilized in a mobile phone, for example, by multiplexing the signals before the conversion. Both time division multiplexing and frequency division multiplexing can be used. When frequency division multiplexing is used, the IF signal (D) coming from the radio part and the baseband signal (A) coming from the microphone are summed (30) before the A/D conversion (31). The converted signal (K, L) is directed through filters (32, 34) in separate branches to digital signal processing (28). After that, the coded microphone signal (I, Q) is modulated (41, 42) to the intermediate frequency and added to the received, decoded baseband signal (M). The summed signal is directed to a D/A converter (45) and thereafter the signals are again separated by means of filters (46, 47). When time division multiplexing is used, the arrangement can also be used for measuring other signals of the mobile station.

Abstract: A digital-to-analog converter for converting a multiple bit digital input signal into multiple representative analog output signals includes a pulse density modulator, a logic controller, signal selection logic circuits and resistive-capacitive lowpass output filters. The pulse density modulator receives the N-M least significant bits of an N-bit digital input signal and in accordance therewith generates a pulse density modulated digital signal with a pulse density corresponding to a digital count of such N-M least significant bits. The logic controller receives the M most significant bits of the N-bit digital input signal and in accordance therewith generates multiple pairs of digital control signals. Each of the signal selection logic circuits receives the pulse density modulated digital signal and a respective pair of the digital control signals and in accordance therewith provides a respective one of a number of digital output signals.

Abstract: An analog-to-digital (A/D) converting device which substantially increases the number of input channels without increasing the number of input terminals. When an external channel selecting circuit is asserted "low", switches are selected to deliver a 3-bit control word to a decode circuit. The decode circuit delivers a corresponding analog signal to a multiplexer in accordance with the control word. An A/D converter converts the analog signal to a digital signal. When the external channel selecting circuit is asserted "high", switches deliver a 3-bit channel control word to an output terminal. Simultaneously, the "high" signal from the external channel selecting circuit is applied to an OR gate, which in turn is applied to a multiplexer. An externally inputted analog signal is also applied to the multiplexer. The inputted analog signal is applied to an A/D converter, via the multiplexer, and the analog signal is converted to a digital signal.

Abstract: An audio codec capable of handling complex control and routing of numerous sound inputs is described. The complex control and routing is obtained by weighting various sound inputs in accordance with weighting values and then digitally mixing the weighted sound inputs together. The invention facilitates construction of the audio codec with mainly fixed gain amplifiers, instead of variable gain preamplifiers, thereby saving a large amount of die space and reducing time needed for testing.

Abstract: A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry including a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The slope A/D converter includes a digital-to-analog converter (DAC) for providing a programmable charging current to generate a voltage across a capacitor, a precision comparator having inputs for receiving a selected analog input and the capacitor voltage, a counter and a capture register. After a reset is performed, the capacitor is charged while the counter begins counting such that when the capacitor voltage exceeds the selected analog input voltage, the comparator switches logic states thereby causing the obtained count of the counter to be stored in the register.

Abstract: An analog-to-digital (A-D) conversion device includes a channel selector for selecting a plurality of analog signal input terminals. The analog-to-digital converter converts an analog signal selected and supplied by the channel selector into a digital signal. A control device controls the channel selector to operate in either a scan mode in response to a starting trigger for scan conversion or a single mode in response to receiving a starting trigger for single conversion.

Abstract: The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using it.The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts the operation state of the AD converter into the low power consumption state.

Abstract: In a circuit at least one of the signals (u?t! or i?t!) is transmitted to a signal input of a sigma-delta modulator operated at a first clock frequency (1/T.sub.S) the output of which is connected to at least one of two signal inputs of a multiplication/addition element (3). The arrangement is used for example in electricity counters and makes it possible to calculate sums of products by means of simple shift and algebraic adding operations while maintaining closely the precision achievable with a classic multiplication. The arrangement is especially advantageous if the multiplications are done on a semiconductor chip.

Abstract: In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

Abstract: A multiplexed analog-to-digital converter to accept multiple dissimilar analog input signals and convert each analog input signal to a digital code that represents the ratio of the magnitude of the analog input signal to the difference of an upper reference voltage source and a lower reference voltage source is disclosed. The upper reference voltage source is selected by an analog multiplexer from a set of voltage reference sources that include the power supply voltage source of the analog-to-digital converter for analog input signals that are reference to the power supply voltage source, and a precision reference voltage source that is referenced to the band-gap of silicon to provide an absolute measurement of the analog input signal. The lower reference voltage source is selected by a multiplexer from such references as a ground reference source.

Abstract: Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.

Abstract: An analog data acquisition system in an integrated circuit automatically processes and stores analog data without sequencing support from a processor. The analog data acquisition system converts each analog input signal into digital data. The digital data are stored in registers in the integrated circuit that are directly readable by a digital signal processor without data moves and are directly usable by the digital signal processor without further processing or conversion. Consequently, the analog data acquisition system minimizes the use of both the digital signal processor and the digital signal processor program memory and leaves capacity, i.e., both processing time and instruction memory locations, for use in other activities. The analog data acquisition system includes an analog input multiplexer and an analog-to-digital (A/D) converter that has an input line that is connected to the analog input multiplexer output line.

Abstract: A high-speed multiplexing technique employs diode bridges to multiplex the outputs of two or more digital-to-analog converters (DACs) together. Like prior art techniques, the diode bridges isolate the DAC outputs from one another and are activated by forward biasing the bridges, one at a time in a staggered-phase, sequential fashion with sequenced biasing currents, to effectively connect the DACs, one at a time to an output signal. Unlike prior art techniques, however, the low capacitance diodes are inserted in series with the sequenced biasing current driving each diode bridge, one on each side of the bridge. The low capacitance diodes are oriented to pass current in the direction of forward bias of the diode bridges. Voltage mode switching is employed to limit the effect of parasitic capacitances on output amplitude. One embodiment is directed to a pair of back-to-back diode bridges driven by a single transformer secondary winding.

Abstract: An A/D converter wherein data obtained by A/D converting an analog signal in an A/D converting unit is stored in a first register, the data in the first register and the data in a second register are compared to each other by a comparator, and when the data in the first register is larger (or smaller) than that in the second register, a first switching means is closed so that the data in the first register is stored in the second register. In the second register, a maximum value (or a minimum value) of the A/D-converted data hitherto obtained is stored.

Abstract: An instrumentation system according to the present invention which automatically demultiplexes multiplexed data received from multiple analog channels. The system includes a plurality N of analog channels that are multiplexed into an A/D converter. The A/D converter in turn supplies the multiplexed or interleaved digital data to an external computer where the data is stored in memory. The external computer includes direct memory access (DMA) demultiplexing logic according to the present invention which automatically reads the multiplexed data and rewrites the multiplexed data into a non-interleaved or demultiplexed format. Once all the multiplexed digital data has been received and stored in the computer system, the demultiplexing logic of the present invention performs DMA transfers to demultiplex or de-interleave the data into N independent buffers or memory spaces which are no longer interleaved.

Abstract: In a demultiplex circuit and an analog-to-digital converter using the demultiplex circuit, since the reset means for controlling the phase of the second clock output from the frequency divider circuit is provided, it is possible to establish the phase of the second clock to establish the output timing of the demultiplex circuit. In addition, since the reset means for controlling the phase of the second clock output from the frequency divider circuit, it is also possible to establish the phase of the second clock to establish the output timing of the analog-to-digital converter.

Abstract: A analog-to-digital converting device includes an analog-to-digital converting operation control unit for temporarily stopping an analog-to-digital converter in response to a trigger signal applied thereto and for restarting the analog-to-digital converter by imposing the operation conditions, which have been initially set up, on the analog-to-digital converter again. The device can forcefully terminate a scanning operation and restart analog-to-digital converting operations in a scan mode under the initially set up operating conditions without having to use an interrupt program executed by a CPU.

Abstract: Apparatus for time multiplexed oversampled analog to digital modulation is provided. Embodiments generally include a plurality of energy collection elements coupled to individual pixel processors preferably mounted proximate to each energy collection element. Each pixel processor shares a common block of conversion logic to form a plurality of integration loops to process the signal generated by each energy collection element. Specific embodiments are shown using CCD, CID, FET, and charge well technologies.

Abstract: A variable length code(VLC) decoding apparatus for simultaneously decoding two different VLC bit streams includes two storage units, in response to each read signal, for storing fixed length segments contained in each of the VLC bit streams; a first switch for selecting the fixed length segments from a first or a second storage unit, and for selecting a first or a second window control signal; a barrel shifter in response to selected window control signal for forming a decoding window on the selected segments in order to produce a decoding window output sequence thereof; a memory for producing a decoded word in response to a variable length codeword and for producing a codeword length output; a second switch, in response to a second selection signal, for producing the decoded word and the codeword length output as a first decoded word and a first codeword length or a second decoded word and a second codeword length output; two accumulators, in response to each of the codeword lengths, for generating the two w

Abstract: A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.

Abstract: Referring to FIGS. 2, 13, and 14, the tag value transferred by timebase select signals (50) indicates which timebase is presently available on timer bus (71). In one embodiment, each channel (61, 62, 80, 81, and 86) compares the tag value of the timebase select signals (50) with a user programmed tag value stored in a register portion (264). If the stored tag value matches the tag value being driven on the timebase select signals (50), then the match signal (263) is asserted to indicate that the channel is either to provide a timebase value to the timer bus (71) for timebase channels (80, 81), or to receive the timebase value from the timer bus (71) for work and other channels (86). FIG. 15 illustrates examples of how timebase values (namely TB1-TB8) may be selectively provided during the different time slots of a timer bus (e.g. 71).

Abstract: A multiplexed delta-sigma modulator for performing analog to digital conversion on a plurality of input analog signals. These input analog signals are input to a multiplexer, where the input analog signals are converted into a single, time-division multiplexed analog signal. The time-division multiplexed analog signal is then received by the delta-sigma modulator, which oversamples the input signal and outputs a time-division multiplexed digital signal. The time-division multiplexed digital signal is then sent to a decimator which outputs a time-division multiplexed digital signal at a rate corresponding to the Nyquist rate of the input analog signals.The signal is sent from the decimator to a first down-sampler, and then to a demultiplexer, where the time-division multiplexed, decimated signal is sent to the appropriate output port of the demultiplexer at a sequential rate corresponding to the sequential rate utilized by the input multiplexer.

Abstract: An analog/digital converter has a register which stores data for selecting an analog voltage to be scanned from analog voltages of plural channels, another register which stores data for selecting an analog voltage to be temporarily scanned, and a counter which is set to count a predetermined number of scanning cycles of the analog voltages. In the converter, analog voltages of plural channels can adequately be scanned by a simple configuration, and, in the course of continuously conducting the scan operation, analog voltages of channels other than the currently scanned channels can temporarily be scanned, so that the analog voltages are converted into digital values.

Abstract: A sigma delta convertor 20 has a number of time slots that are programmable connectable to the input channels 200 via a multiplexer 205. Conversion throughput of any one input channel is increased by connecting two or more time slots to the input channel. For an eight input channel embodiment 800 the throughput of conversion of one input can be increased 2.times., 4.times. or 8.times. by connecting, respectively, 2, 4 or all 8 time slots to the selected input channel.

Abstract: In a control circuit including an A/D converter, a parallel-to-serial input buffer, a parallel input buffer, a serial-to-parallel output buffer and a parallel output buffer which are built in a chip, provided with a microcomputer, an A/D conversion is carried out by controlling a time of an A/D conversion conducted by the A/D converter correspondingly to a condition of an output port of the output buffer, thereby preventing an A/D converted value from being affected by an inversion in the output of the buffer.

Abstract: In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the bus which changes with the transmission of successive code words is minimized. A switching code, comprising one or more bits, defines a plurality of napping codes and a data word to be transmitted is mapped by use of the mapping codes to a plurality of code words. One of the plurality of code words differing from a previously transmitted code word in the least number of bit positions is selected. The selected code words is transmitted, together with a switching code, identifying the mapping from which the transmitted code word was generated. At the receiving end of the bus, the switching code is decoded to identify the mapping used in creating the code word. Using the identified mapping, the original data word is recovered.

Abstract: A method and circuit for improved digitization of waveforms having a large dynamic range, including selecting a signal threshold value which partitions the dynamic range of the waveform into a small signal region and a large signal region; sampling the waveform to obtain a sampled signal therefrom at a given sampling frequency; for each sampled signal, comparing the sampled signal with the signal threshold value to determine whether the sampled signal is within the small signal region or the large signal region; and directly digitizing the sampled signal if the sampled signal is within the small signal region or differentially digitizing the sampled signal if the sampled signal is within the large signal region, wherein differentially digitizing the sampled signal includes digitizing a value representing the difference between the sampled signal at a present sampling instant and a previous sampling instant.

Abstract: An analog-to-digital converter for converting a multitude of analog input signals into a corresponding multitude of digital signals comprises a series arrangement of an analog multiplexer (2), an oversampling sigma-delta modulator (8), a decimator-cum-low-pass filter (10), a digital demultiplexer (12), an interpolator (14) and a digital matrix (16), which are all operated in synchronism.

Abstract: The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using the same. The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts an operation state of the AD converter into a low power consumption state.

Abstract: The device comprises a first input (E1) and a first output (S1) which are capable respectively of receiving and delivering a plurality of analog signals and corresponding digital signals having different predetermined types of transmission specifications and associated with substantially homothetic predetermined elementary frequency attenuation templates. A second input (E2) and a second output (S2) are also provided, capable respectively of receiving and delivering a plurality of digital signals and corresponding analog signals having different predetermined types of transmission specifications, associated with different, substantially homothetic predetermined elementary frequency attenuation templates, as well as first and second signal conversion means arranged respectively between the first input and output and between the second input and output and including a single digital filter (6) in common, having a single frequency attenuation template which is compatible with all the elementary templates.

Abstract: An A/D conversion control apparatus includes a control circuit for controlling various actuators and an A/D converter having a plurality of signal input channels. The control circuit and the A/D converter are packed in different IC packages and perform communication of a handshake system therebetween. Because the control of the A/D converter is performed based on channel start signals which are sequentially transmitted from a time synchronous register, complicated control such as schedule control in software is not required. A start signal stored in an asynchronous register is transmitted in response to a signal generated at an asynchronous timing and therefore can be processed at a different timing.

Abstract: To implement a high-speed, high-resolution A/D (or D/A) converter, a differential waveform of an analog (or digital) waveform signal is generated by a differential waveform generating part 10, the differential waveform is distributed to N integrators 14.sub.1 through 14.sub.N in a repeating cyclic order at the timing of a clock CK.sub.0, N being an integer equal to or greater than 2, and the integrator outputs are converted by converting parts 15.sub.1 through 15.sub.N to digital (or analog) signals. These converted outputs are added together by an adder 16, whose output is provided as a digital (or analog) waveform signal.