Abstract: An integrated circuit chip for interfacing a digital computer to sensors and controlled devices can be configured to accept and provide a variety of analog and discrete input and output signals. The circuit includes a plurality of signal conditioning cells, a plurality of signal conversion cells, and input and output signal multiplexors.

Abstract: A bandpass analog to digital converter includes M single channel delta sigma modulators having N-bit quantizer outputs arranged in a parallel configuration and operated at a predetermined sample frequency (fs). The modulator outputs are time interleaved and digitally combined in a manner that provides performance characteristics comparable to a modulator with a sample frequency of Mfs. Thus, bandpass center frequencies that are much higher than conventional single channel architectures are achievable. Single channel first order modulator bandpass center frequencies are restricted to fc=fs/4. However, a range of center frequencies approaching Mfs/2 is supported. This increased frequency capability is obtained while maintaining the delta sigma noise shaping near the higher bandpass center frequencies to reduce the effects of quantization noise. This results in a high signal to noise ratio with a corresponding high resolution at the much higher center frequencies.

Abstract: A digital pixel driver that operates in response to an M-bit digital input value defining the apparent brightness of the pixel. The pixel driver generates a pixel drive signal having a duty cycle that sets the apparent brightness of the pixel. The pixel driver comprises a memory, a digital sequence generator and a comparator. The memory receives and stores an N-bit word that represents the digital input value. The digital sequence generator generates a digital sequence of P-bit digital values that defines the temporal duration of the pixel drive signal and includes a first P-bit word that represents at least part of the digital input value at a location temporally corresponding to the duty cycle of the pixel drive signal as defined by the at least part of the digital input value. The comparator is connected to receive the digital sequence from the digital sequence generator and a second P-bit word from the memory. The second P-bit word constitutes at least part of the N-bit word.

Abstract: A data conversion device for converting analog data to digital data, or digital data to analog data, is composed of a data converter. and a mediator. Plural data groups are fed to the data converter that coverts the data, group by group, upon receipt of a request for converting a particular data group. If plural requests are simultaneously made, the mediator makes mediation among the plural requests to select a data group to be first converted and to set a priority order. A function uniquely corresponding to a combination of the plural requests is generated in the mediator, and the mediation is performed based on the generated function with reference to a preinstalled table showing a relation between the function and the request to be selected.

Abstract: A circuit and method is provided that allows for communication of digital to analog data over more that one channel employing a single current switching DAC and a current switching multiplexer. The current switching multiplexer is an output stage circuit that is used to steer the current from one output channel to another. The data rate of the data transmitted to the DAC is increased by the number of channels that the data is being transmitted over. The data is then switched from one channel to the other by employing a current switching multiplexer, such that the device provides for the same functionality that conventional devices utilizing a single DAC for multiple channels as opposed to a single DAC for a single channel.

Abstract: A mixed signal CODEC including an improved sigma-delta ADC (20) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. Additionally, it avoids overshoot and settling problems. This sigma-delta analog-to-digital converter (20), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (21), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (21) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

Abstract: A method for practice in a pipelined analog to digital converter. The method converts an analog signal to a sequence of digital words, while converting capacitor mismatch in the stages of the ADC into white noise. In the method, for each of one or more of the pipelined stages, first, the plurality of capacitors therein is coupled at a sample time between the stage input port and ground. Second, during an amplifying period following the sample time, one or more of the plurality of capacitors are coupled between a reference voltage and the input port of the amplifier, while the remainder of the plurality of capacitors are coupled between the input port of the amplifier and the output port of the amplifier, such that different ones of the plurality of capacitors are selected, according to a predetermined procedure uncorrelated with the analog signal, for coupling between the stage input port and ground.

Abstract: A converter continuously converts an input signal (110) to an output signal (112) even during correction and compensation. A primary converter (124) converts the signal along a forward primary path (104). A feedback converter (140) along a feedback path (106) outputs a feedback signal (116). A reference device (136) employs reference indicator (134) to provide a digital reference signal (135). A selection device (132) passes the digital reference signal (135) to an element (204) of the feedback converter (140) for outputting reference portion (208) of the feedback signal (116). The passing of the digital reference signal (135) to the element (204) is contemporaneous with the converting of the input signal (110) to the output signal (112). The evaluator (142) determines a conversion characteristic of the element (204) by employing a characteristic of the reference indicator (134).

Abstract: A programmable priority encoder having a plurality of request inputs and a corresponding plurality of acknowledge outputs. A configurable priority encoder subunit implements one of a plurality of priority schemes in response to a priority control word corresponding to the priority scheme. The configurable priority encoder subunit acknowledges, on a corresponding one of the acknowledge outputs, a request having a highest priority, in the priority scheme, of all current requests on the plurality of request inputs.

Abstract: A serial-deserializer converts a high speed serial data input to a lower speed parallel output. By including this circuit on a chip, connections to the chip are made more easily. A gated voltage controlled oscillator provides clock signals to sample the data input at a high rate. The output signals are thus provided at a slower rate.

Abstract: A multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A first stage receives the sampled analog signal as the analog input signal. Each stage provides a residue output, which is the analog input signal to a subsequent stage. The residue is the analog input signal to the stage, less the analog equivalent of the partial digital output from the stage, possibly with a gain change. A voltage range over which a sample of an analog signal can vary is defined by a lower limit and an upper limit. A lower comparator threshold is established within the voltage range. An upper comparator threshold is established within the voltage range, between the lower comparator threshold and the upper limit. The analog input to the stage is quantized based on the lower and upper comparator thresholds to generate a quantized sampled analog signal.

Abstract: A digital-to-analog conversion circuit (105) includes a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.

Abstract: In a parallel Analog-to-Digital Converter (ADC) device a number of ADCS work in parallel, the conversion processes in each ADC overlapping the processes in the other ADCs. The number of ADCs and the sampling period at which samples arc taken and new conversion processes are periodically started in the ADCs are selected so that at each instant, at least one ADC is idling not performing any conversion. After the conversion is made by one of the ADCs, a choice is made whether the next sampled value is to be converted by this ADC or by the idling ADC. This choice can be made in a random or a pseudo-random way. Undesired tones existing in the composite output signal of parallel ADC devices having no such extra ADC are transferred to noise, as the error in the output signal caused by differences in the conversion characteristics of the ADCs is distributed in the frequency domain.

Abstract: An interface module includes a high density analog interface (HAI) for electrical interconnection between a programmable logic controller (PLC) and an analog to digital converter (ADC) or a digital to analog converter (DAC). The HAI includes a single application specific integrated circuit having a data scaling function block, a diagnostics function block configured to verify functionality of said scaling function block, a self-calibration function block configured to compensate for drift in said ADC, and a shared interface function block configured to electronically connect said module with a programmable logic controller (PLC).

Abstract: An analog computation system which forms a hybrid between analog and digital computation. The analog signal is divided into a plurality of separated analog signals, each of the different analog signals collectively representing the original analog signal, and each having less resolution then the total desired resolution. A number of different analog computation elements carry out a mathematical function on the separated signal. Different stages may be provided, and a signal restoration device may be provided between the different stages.

Abstract: A pair of internal signals are generated by halving a 3-bit 5-valued input signal, neglecting the least significant bit LSB. If the input signal shows the value of an odd number, 1 is added to either of the pair of internal signals to generate first and second signals. “1” is added to either of the pair of internal signals in an alternating way each time an input signal having the value of an odd number. Signal processing circuits selects a number of output terminals corresponding to the value of the first signal or the second signal out of a plurality of output terminals. All the output terminals are selected with a same probability.

Abstract: The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal.

Abstract: Several delta-sigma modulator circuits and a single quantizer provide analog-to-digital conversion for multiple frequency bands. A wideband mode is provided by coupling an analog signal to be digitized directly to a quantizer. Narrowband modes are provided by switching the analog signal to be digitized into one of several delta-sigma modulator circuits. Noise shaping and filtering by the delta-sigma modulator circuits result in improved signal-to-noise-and-distortion performance and increased resolution. Performance is further enhanced by feeding back multiple bits output by the quantizer to the delta-sigma modulator circuits. The delta-sigma modulator circuits can be either continuous time or discrete time delta sigma modulators.

Abstract: A gain stage using switched capacitor architecture and suitable for a pipelined analog to digital converters provides for three pairs of switched capacitor banks whose use may be alternated so as to provide simultaneous sampling of two input channels for sequential gain operation without the interposition of additional circuitry in the signal chain from input to output of the gain stage.

Abstract: An apparatus for signal processing discrete-time values for signal-sampling systems, such as digital/analog converters, switched capacitor filters, direct digital synthesizers, sample-and-hold circuits and the like, having means for producing discrete-time values and means for processing discrete-time values into analog values, is distinguished in that at least one group of at least two signal-sampling systems, which, in particular, have the same input signals applied to them, is of parallel-connected design, means are provided for producing sampling frequencies with a shifted phase angle and for driving the respective sampling system with a shifted phase angle for the particular frequency produced, means are provided for summing the signals from the signal-sampling systems, and means are provided for further processing/converting the summed signals from the sampling systems into analog signals.

Abstract: A circuit and method is provided that allows for communication of digital to analog data over more that one channel employing a single current switching DAC and a current switching multiplexer. The current switching multiplexer is an output stage circuit that is used to steer the current from one output channel to another. The data rate of the data transmitted to the DAC is increased by the number of channels that the data is being transmitted over. The data is then switched from one channel to the other by employing a current switching multiplexer, such that the device provides for the same functionality that conventional devices utilizing a single DAC for multiple channels as opposed to a single DAC for a single channel.

Abstract: An apparatus for an integrated circuit comprising a thermal sensor (41-44), an A-D converter (58) coupled to the thermal sensor, wherein the thermal sensor provides an input to the A-D converter, and the A-D converter converts the input to a digital value representative of the thermal environment of the thermal sensor. A method for an integrated circuit comprising the steps of collecting a data value at a location on an integrated circuit wherein the data value has a predetermined functional relationship to the temperature at the location; converting the data value to a value representative of the thermal environment of the location on the integrated circuit.

Abstract: A technique to suppress idle tones in any mismatch-shaping encoder for use with a unit-element digital-to-analog converter. The arbitrary mismatch-shaping encoder provides a first set of signals which normally are intended to control directly the unit elements. A scrambler is used to interchange the first set of signals, thereby generating a second set of signals which are used to control the unit elements. The scrambler interchanges the signals as a function of a selector signal. A detecting circuit is used to evaluate in which clock cycles the unit elements have been used equally often. When this occurs, the selector signal is randomly assigned a new value in the following clock cycle.

Abstract: A data conversion device for converting analog data to digital data, or digital data to analog data, is composed of a data converter and a mediator. Plural data groups are fed to the data converter that coverts the data, group by group, upon receipt of a request for converting a particular data group. If plural requests are simultaneously made, the mediator makes mediation among the plural requests to select a data group to be first converted and to set a priority order. A function uniquely corresponding to a combination of the plural requests is generated in the mediator, and the mediation is performed based on the generated function with reference to a preinstalled table showing a relation between the function and the request to be selected.

Abstract: There is provided an A/D converter such that a successive approximation register has a plurality of A/D registers each corresponding to one of A/D inputs, and that a capacitor in a comparator is charged by a voltage determined based on a value held in an A/D register corresponding to an A/D input to be A/D converted before starting A/D conversion of the A/D input, thereby reducing noise generated at the time of selecting A/D inputs to enhance A/D conversion accuracy.

Abstract: In order to prevent spurious signals from being generated in an electronic circuit executing an interleaving operation, a plurality of substantially similar electronic circuits 101, 102, 103 are arranged in parallel and operated in an interleaved manner. When each operating frequency of the electronic circuit is f, in order to obtain a Nf frequency (N is 2 in FIG. 1), more than N pieces (3 in FIG. 1) of electronic circuits are arranged in parallel and used, and electronic circuits 101, 102, 103 are selected for output in an at least pseudo-random manner.

Abstract: An image signal processing circuit (102) includes a phase-expansion circuit (103), a digital polarity-inversion circuit (104), first to sixth D/A converters (111 to 116), and first to sixth operational amplifiers (151 to 156). The resistance value of the first to sixth amplitude adjusting resistors (121 to 126) which cause the output amplitude of an analog signal output from the first to sixth D/A converters (111 to 116) to be fixed is adjusted by laser trimming. First to sixth gain setting resistors (161 to 166) are connected to the first to sixth operational amplifiers (151 to 156). The first gain setting resistor (161) includes a first resistor (131) and a second resistor (141), and the gain of the operational amplifier (151) is set by the resistance ratio (R2/R1) thereof. In order that this resistance ratio (R2/R1) is fixed for each set, the first resistor (131) and the second resistor (141) are formed on the same substrate by undergoing the same manufacturing process.

Abstract: A low power integrated circuit having analog to digital conversion circuitry capable of receiving a plurality of analog signals and converting them to a digital value. The digital value is then transmitted, upon request, over a single wire bus. The accuracy of the analog to digital conversion circuitry can be calibrated via trim codes stored in an onboard EPROM.

Abstract: An analogue frontend, such as is used, for example, in receivers for communications equipment, comprises a plurality of analogue components (1-3) which are connected upstream of an analogue/digital converter (4). In order to control the drive level of the individual analogue components (1-3) precisely, the input of the analogue/digital converter (4) can optionally be connected via a switch-over device (8) to the output of any one of the analogue components (1-3) and a drive level control signal for the respective analogue component (1-3) can be generated by a digital control device (5) by evaluating the sampled value which is then supplied by the analogue/digital converter (4).

Abstract: An A/D converter system includes a regular A/D converter (10) with calibration means. Included is also a lower performance, as compared to the regular A/D converter, auxiliary A/D converter (20). Means (22, 24) are provided for temporarily switching, at a switching rate that is lower than the sampling rate of regular A/D converter (10), A/D conversion from the regular A/D converter (10) to the auxiliary A/D converter (20) during short time intervals used for calibration of the regular A/D converter (10).

Abstract: A delta-sigma modulator comprises a 1-bit quantizer located for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal, a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal, a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer, and an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by a delay element from an input analog signal input to the delta-sigma modulator, and one integrator at a final stage outputting its output to the 1-bit quantizer. A multiple-bit quantizer quantizes an analog output of the subtracting circuit and outputs a second quantized digital signal.

Abstract: In audio-decoder apparatus, a circuit substrate 12 common to a 2-channel model and a 5.1-channel model, on which a decoder 3 and a D/A converter 4 with built-in PLL are installed, and which has installing portions 5a and 6a for enabling installation of D/A converters without built-in PLL. The line connection modes of signal lines connecting the output terminal of the decoder 3 to the input terminals of each D/A converter can be changed by a switching apparatus 13, corresponding to the channel model, thus it becomes possible to realize D/A converters without built-in PLL having better audio performance under a line connection mode desired for an improved audio performance. Therefore, a good audio performance can be secured, while a common circuit substrate can be used for a variety of channel models, which is advantageous in view of fabrication cost.

Abstract: Disclosed is a method in a disk drive that allows the functionality of a single high-resolution DAC to be replicated with a pair of lower-resolution DACs that are operated in a unique manner that provides monotonic behavior and reduces both differential and integral non-linearity. The two lower-resolution DACs take up substantially less space that one higher-resolution DAC when implemented in a semiconductor die. The method combines coarse values from one DAC with fine values from the other DAC to form a combined analog output signal within operational segments that collectively span a range of N-bit demands. The method operates such the operational segments overlap one another by 50 percent, with an endpoint of each operational segment ending near a center of an overlapped operational segment.

Abstract: An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

Abstract: A method of forming an aggregation of N>1 band-limited time signals, each with a bandwidth of ≦B, which are present as analog and/or digital sampling values, with a respective sampling frequency of fA>2B, is characterized in that the sampling values of all N time signals are offset in time and superimposed on each other, and are jointly input to a low-pass filter (12) with a bandwidth of B′>B, and that a composite signal is tapped off from the output of the low-pass filter (12). This allows the aggregation to be performed in a considerably shorter calculation time, a number of slow and expensive aggregation elements can possibly be saved, and the damping of the signals during processing can be minimized, as well as the corresponding loss of information.

Abstract: A system for a providing addresses to each one of a plurality of addressable integrated circuits. The system includes a plurality of address select circuits, each one thereof being coupled to a corresponding one of a corresponding plurality of addressable integrated circuit. Each one of such integrated circuits has an address select pin adapted to receive a signal from the corresponding one of the address select circuits. The signal is indicative of an address for such one of the plurality of addressable integrated circuits. Each one of such address circuit includes a signal source connected to the pin and a circuit for coding such signal source into a selected one of more than three predetermined signal levels.

Abstract: A dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system includes a 2-bit ADC for extending the dynamic range of the imager device, which enhances the dynamic range of a 10 bit ADC to 13 bits.

Abstract: A mixed signal codec includes: a multiplexer amplifier 24 having an analog output signal; a sigma-delta analog to digital converter 26 having an input coupled to the analog output signal; and a clipping circuit 40 and 42 coupled to the input of the analog to digital converter for clipping the analog output signal.

Abstract: Mixed-signal circuitry comprises analog (14) and digital (100, 200) circuitry and is operative repetitively to perform a series of processing cycles. The analog circuitry (14) is operable in each processing cycle to receive a set of digital signals TCK1˜n and to produce one or more analog signals (OUT A, OUT B) in dependence upon the received digital signal TCK1˜n. The digital circuitry (100, 200) is connected to the analog circuitry (14) for applying such a set of digital signals TCK1˜n thereto in each processing cycle. The digital circuitry comprises a first circuitry portion (100) which provides the set of digital signals in first processing cycles of the series and a second circuitry portion (200), separate from the first circuitry portion (100), which provides the set of digital signal in second processing cycles of the series different from, and interleaved with, the first processing cycles.

Abstract: A signal generation circuit comprises a memory operable to store a digital signal comprising a stream of one-bit samples that were generated using sigma delta modulation. The signal generation circuit further comprises a signal modification circuit coupled to the memory and operable to receive the digital signal from the memory and to introduce a DC level shift to the digital signal, wherein the output of the signal modification circuit can be filtered to produce an analog signal.

Abstract: A device and method for converting an analog signal into a digital signal using an interleaving sampling operation is described. The device and method includes generating multiple clock signals of the same frequency but with different phases. An input analog signal is compared against multiple reference voltages. For each phase, comparison results are transmitted and decoded into a binary representation of the input analog signal. The decoding also includes the value of the clock phase of the comparison.

Abstract: Matched digital-to-analog conversions are performed in which, in each of N parallel channels, a digital input word is converted into a corresponding analog output. A digital sequence is generated, a time-varying analog signal having a predetermined relationship to the digital sequence is generated in response to the digital sequence, and the digital sequence and the time-varying analog signal are distributed to the N parallel channels. In each of the N parallel channels, the digital input word is digitally compared with the digital sequence, and, when the digital sequence is numerically equal to the digital input word, the time-varying analog signal is sampled to provide the analog output. The single time-varying analog signal derived from the single digital sequence at an operational speed at which high accuracy and low power consumption can be easily attained enables well-matched digital-to-analog conversions to be performed in any number of channels ranging from a few to many thousands.

Abstract: A parallel to serial converter comprising a parallel word latch for receiving a series of words comprised of parallel data words, a shift register for receiving the parallel data words and for storing bits of a parallel data word in a series of shift register stages upon receipt of a first enable signal, and for providing a serial stream of bits at a serial clock rate, a circuit for receiving a serial clock signal and for providing the serial clock signal to the shift register to enable shifting of the stored bits to an output as the serial stream of bits, and a controller for generating the enable signal and for applying the enable signal to the shift register and parallel word latch, said controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A D/A converting apparatus for converting a digital signal into an analog signal, wherein the reference signals of the maximum value and the minimum value of a main D/A converter are generated by the other two D/A converters, whereby the output voltage can be digitally adjusted and the accuracy of the output signal is improved.

Abstract: A parallel pipelined analog-to-digital converter for use with chips containing large arrays of detectors is described. In these A/D converters, the degree of parallelism decreases between earlier and later pipeline stages. That is, there are fewer instances of at least one of the later stages than there are instances of at least one of the earlier stages. Thus, the instances of the earlier stages are responsible for processing a fewer number of pixels than are instances of the later stages. Viewed another way, the parallel pipelined analog-to-digital converter architecture of this invention assumes a tree or branched arrangement in which the earlier stages correspond to leaves and the later stage condense to branches. In an extreme example, the later stages coalesce to a single route.

Abstract: A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width.

Abstract: Briefly, in accordance with one embodiment of the invention, a complementary metal-oxide semiconductor (CMOS) integrated circuit includes: a CMOS image sensor. The integrated circuit further includes an analog-to-digital (A/D) converter, at least one analog signal storage circuit, and control circuitry to multiplex the application of signals to the A/D converter from the image sensor and the at least one analog signal storage circuit.

Abstract: An apparatus for wide bandwidth analog to digital and digital to analog signal conversion is disclosed. An input/output stage (40) is coupled to an external analog system and includes reference voltages for calibration of the analog to digital (A/D) conversion process. A conversion stage (46), comprising a plurality of A/D converters (ADC) (48, 50) and a digital to analog converter (52), is coupled to the input/output stage and to a digital signal conditioning stage (54) which is coupled to an external digital system. Offset and gain errors in the outputs of each ADC are corrected by the application of appropriate correction parameters in the digital signal conditioning stage. The sampling intervals for each ADC are phased to allow the digital outputs of the ADCs to be interleaved and form a resulting digital data stream with a sampling rate a multiple of that of any one ADC.

Abstract: An arrangement and method for producing a plurality of pulse width modulated outputs, comprising: receiving values representative of durations of pulses to be generated at the outputs (210); producing values representative of the time differences (230) between transitions of pulses to be produced; and producing transitions in the pulses in the plurality of channels at times corresponding to the time Difference values.

Abstract: A switching device for switching between a 1-bit digital signal .SIGMA..DELTA. modulated by a first sampling frequency and a 1-bit digital signal .SIGMA..DELTA. modulated by a second sampling frequency lower than the first sampling frequency. The 1-bit digital signal .SIGMA..DELTA. modulated by the second sampling frequency is transiently converted to the 1-bit digital signal .SIGMA..DELTA. modulated by the first sampling frequency. The converted 1-bit digital signal or the 1-bit digital signal .SIGMA..DELTA. modulated by the first sampling frequency is switched by cross-fading processing for realizing switching with suppressed noise generation at the time of switching.