Abstract: Apparatus for time multiplexed oversampled analog to digital modulation is provided. Embodiments include modulators (60, 300 and 450) and focal plane optical imagers (100, 160 and 200). Embodiments generally include a plurality of storage elements (70) to hold modulation residues. Multiplexor and demultiplexor structures (72, 74) enable residues to be updated and stored for a plurality of modulated signals. Specific embodiments (500, 600) are shown in CMOS and mixed CMOS-CCD technologies.

Abstract: A facsimile apparatus in which a single A/D converter used for analog image signals is shared efficiently with other analog sensors. The facsimile apparatus has an image scanner for outputting an analog image signal by scanning an original and at least one analog sensor for outputting an analog detection signal. A multiplexer is provided for selecting one of the analog signals including the analog image signal and the analog detection signal. An analog/digital converter converts the analog signal selected by the multiplexer into a digital signal. A primary scanning counter counts the number of pulses of a pixel clock signal indicating a reading timing of each pixel so as to output a count value, the count value being reset each time a line synchronization signal indicating a first position of each scanning line is supplied thereto.

Abstract: An electronic engine controller includes a central processing unit (CPU) which controls the operations of the controller and an analog-to-digital (A/D)converter chip which receives analog signals generated by sensors which transmit signals indicative of vehicle and engine operating parameters. The A/D converter chip automatically performs a conversion on certain signals indicative of critical engine operating parameters to generate corresponding digital values upon each engine revolution. These digital values are stored for retrieval by the CPU. Digital values corresponding to other signals are generated and transmitted upon request by the CPU. The A/D converter chip and the CPU are coupled by a serial link which operates under one of several protocols to transmit digital values from the A/D converter chip to the CPU.

Abstract: A digital/analog conversion apparatus with a color palette RAM for a multimedia, comprising a first latch circuit for inputting a pixel address signal, a pixel mask register for selectively masking the pixel address signal from the first latch circuit in response to a control signal from a microprocessor interface circuit, a second latch circuit for storing digital color information temporarily, and first to third digital/analog converters for converting the digital color information from the second latch circuit into analog R, G and B color information. The palette RAM stores digital color information from the microprocessor interface circuit and outputs the digital color information stored in its location corresponding to the pixel address signal from the pixel mask register to the second latch circuit.

Abstract: An A/D circuit to convert an analog signal to a digital signal. The circuit includes a low noise analog-to-digital conversion chip and a precision voltage reference source. The voltage reference source includes a diode with two terminals and a passive attenuation circuit. The attenuation circuit and the diode are coupled in parallel between the two terminals to provide a voltage reference signal for use by the analog to digital conversion chip. The analog to digital chip uses the voltage reference signal to set the full scale input range for the signal conversion, and the voltage reference signal is attenuated to correspond to the full scale range of the analog signal. The A/D converter circuit has a passive temperature compensation feature to substantially eliminate or reduce the effects of thermal drift and of operating at different temperatures.

Abstract: A microprocessor-based system includes a central processing unit (CPU) and a CPU memory coupled by a CPU bus. A DMA sampler is coupled to the CPU, the CPU memory and the CPU bus. The DMA sampler includes sampling circuitry which is implemented as a finite state machine to maintain a substantially exact sampling rate on at least one analog input signal provided to the DMA sampler. The DMA sampler also includes DMA circuitry implemented as a data flow machine, which requests bus mastership from the CPU when samples obtained by the DMA sampler are available for transfer to the CPU memory. In response to the request, the CPU relinquishes bus mastership to the DMA sampler which provides the sample to the CPU memory and returns bus mastership to the CPU.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: Adverse visual effects on a video display caused by switching operations in a digital-to-analog converter of the video subsystem and by parasitic impedance loading the DAC are minimized. Current cells associated with the DAC generate discrete currents for the video display. Each current cell has a current source for providing a current continuously and first and second switching mechanisms. The first switching mechanism is actuated by a select signal for switching the current to a current sink having a dummy resistance R.sub.d, and the second switching mechanism is actuated by an nselect signal for switching the current to the video display. The select and nselect signals, are generated from input data. A first feedback loop combines the select signal with the data to derive the nselect signal so that the nselect signal is generated after the select signal decreases to a predefined threshold, preferably zero.

Abstract: An appparatus for receiving signals from any of a plurality of sensor types is provided and includes pull-up circuitry connected to a circuit input; data edge conditioning circuitry having a digital output and an input connected to said circuit input; and an analog output connected to said circuit input and said pull-up circuitry.

Abstract: A digitizer suitable for digitizing input signals having a high dynamic range. The digitizer is microprocessor controlled and comprises an input stage, a multi-channel attenuator or amplifier bank, a multiplexer and a analog-to-digital (A/D) converter. The function of the multi-channel bank is to move the input signal within the range of the A/D converter. The input signal to be digitized is fed through the input stage to each of the channels in the attenuator bank. The signal is scaled by each respective channel in the attenuator bank. The multiplexer is used to switch the scaled signal which is within the range of the A/D converter for digitizing. The digitized sample is then corrected according to the attenuation or gain factor of the scaled channel. The digitizer includes a comparator bank which is used to determine the channel with the widest signal range within the range of the A/D converter. The digitizer also includes a channel calibrator for calibrating the actual gain or attenuation of each channel.

Abstract: An interface circuit for use with process controllers permits analog signals to be input to a process controller through a binary interface of the process controller and permits analog signals to be output from the process controller through the binary interface. The input analog signal is converted to a digital sample of N bits. An identification pulse and the N bits of the digital sample are transmitted to the process controller at a rate selected for compatibility with the scan time of the process controller. The process controller includes a software routine for recognizing the identification pulse and the N bits of the digital sample. An equivalent approach is used for outputting analog signals through a binary interface of a process controller. The interface circuit can include multiple channels for inputting or outputting multiple analog signals.

Abstract: The present invention relates to a circuit for converting a plurality of analog electrical measurement signals into corresponding digital signals. To realize such a circuit with relatively few circuit elements, input-side antialiasing filters are linked on the output side to at least two multiplexers, which have at least two downstream sample-and-hold circuits connected to them. At least two analog-digital converters are linked on the input side to the output of a sample-and-hold circuit. An evaluation device is arranged downstream from the at least two analog-digital converters and acquires in one evaluation interval (0 through T1) digital values corresponding to several sampling values of an electrical signal, and produces the corresponding digital signal through mean value generation.

Abstract: Base station equipment of a digital mobile communication system includes a digital audio signal processing apparatus provided for each message channel for low bit rate coding and decoding a digital audio signal. Each digital audio signal processing apparatus includes a plurality of memories that store a plurality of low bit rate coding/decoding programs differing from each other to comply with different low bit rate coding/decoding methods. A system control circuit determines the low bit rate coding/decoding method of an applied digital signal for controlling a selector to select a memory that stores the corresponding low bit rate coding/decoding program. As a result, the digital audio signal processing apparatus perform digital to digital conversion of the applied digital signal according to the low bit rate coding/decoding program stored in the selected memory.

Abstract: A folder circuit maps an analog input voltage to an analog output voltage in accordance with a folding function having at least one folding point. The folder circuit includes a power supply node and at least one input differential stage. Each input differential stage has a first input node to which is applied the input voltage, a second input node to which is applied a first reference voltage corresponding to that stage's folding point, and two differential output nodes. A resistive network is connected between the power supply node and the two differential output nodes, and a current source draws a predefined current from each input differential stage. An output network generates an analog output voltage as a function of the highest voltages on the differential output nodes of all the stages of the folder circuit. A current injection circuit provides a level-shifting current to each input differential stage through the two differential output nodes.

Abstract: Disclosed herein is a microcomputer having a test circuit for an A/D converter of a C/R type. This converter includes a resistor circuit having a plurality of resistors connected in series between reference potential points to generate a changeable reference voltage and a capacitor circuit having a plurality of capacitors for storing electrical charges relative to an analog input voltage and to the changeable reference voltage, and the test circuit is coupled to the resistor circuit and the capacitor circuit and further to first and second terminals and activated in a test mode to transfer the changeable reference voltage to the first terminal and another reference voltage, which is produced outside the microcomputer, to the capacitor circuit.

Abstract: An A/D circuit to convert an analog signal to a digital signal. The circuit includes a low noise analog-to-digital conversion chip and a precision voltage reference source. The voltage reference source includes a diode with two terminals and a passive attenuation circuit. The attenuation circuit and the diode are coupled in parallel between the two terminals to provide a voltage reference signal for use by the analog to digital conversion chip. The analog to digital chip uses the voltage reference signal to set the full scale input range for the signal conversion, and the voltage reference signal is attenuated to correspond to the full scale range of the analog signal.

Abstract: An analog-digital converting device is designed such that when an operation of converting a special analog signal into a digital signal and an operation of converting another analog signal into a digital signal are instructed concurrently, priority is given to the conversion operation of the special analog signal, The analog-digital converting device includes an analog multiplexer having a main channel and a sub channel, a sample holder, an AD converter, a conversion result register having a plurality of storage areas, and an AD control circuit for controlling the drive of the individual components according to an instruction of a CPU. When the analog signals input to the channels are converted into digital signals in sequence, priority is given to AD conversion of the analog signal input to the main channel over AD conversion of the analog signal input to the sub channel.

Abstract: An analog to digital converter includes first and second folder circuits that map an analog input voltage into first and second folder output voltages, using two different voltage transfer functions. First and second flash circuits generate first and second digital representations of the first and second folder output voltages. An MSB conversion circuit generates a set of most significant bits representative of the analog input voltage input, and a multiplexer selects one of the first and second digital representations in accordance with the least significant bit of the output from the MSB conversion circuit. The analog to digital converter further includes first and second decoder circuits for decoding the first and second digital representations from the two flash circuits, and the multiplexer selects one of the two decoded digital values. The selected decoded value represents the least significant bits of a digital representation of the analog input value.

Abstract: To accept a plurality of starting factors without the use of a CPU and improve the real-time processing speed of A/D conversion, the same number of channel selection registers, mode registers and conversion result storage registers as the number of starting factors are provided and divided into groups according to the types of starting factors, and a control circuit for specifying a register group for a starting factor when the factor is generated is also provided.

Abstract: A digital signal processing automotive audio system uses an analog audio source providing stereo output signals. One of the stereo signals is mixed to a distinct frequency band and summed with the other stereo signal to form a composite signal which can be digitized in a single analog-to-digital converter. Separate digital stereo signals are recovered using digital signal processing.

Abstract: An analog-to-digital converter (ADC) generates multiple analog waveforms, preferably as voltage ramps, that progressively increase in signal value over time but at different rates of increase. The ramp with the greatest slope is initially compared with an input signal sample until the ramp exceeds the sample, at which time the system switches to the ramp with the next greatest slope for comparison with the input. The operation then repeats, with the system switching to the next lower ramp each time the current ramp exceeds the input. Both the number of ramp switching events that occur during a sample cycle, and the clock count at the time of the most recent ramp switch, are recorded and used respectively as the most and least significant bits of a digital output. The switching event count proceeds from an initial maximum value from which it subtracts at each switching event, while the clock count builds up from an initial minimum value.

Abstract: An N-bit analog to digital converter (ADC) generates an output code having J most significant bits (MSBs) and K least significant bits (LSBs). First and second folder circuits map an analog input voltage into first and second folder output voltages, each folder circuit having at least 2.sup.k +1 folding points. The folding points of the first folder circuit are located at 2.sup.k LSB+i.times.4.times.2.sup.k LSB for i=0 to 2.sup.k, while the folding points of the second folder circuit are located at 3.times.2.sup.k LSB+i.times.4.times.2.sup.k LSB for i=0 to 2.sup.k. Each folder circuit produces a folder output voltage as well as 2.sup.k +1 differential output voltages. An MSB decoder includes a comparator that compares the first and second folder output voltages to generate a second lowest MSB.

Abstract: A character processing apparatus for recognizing coordinate information expressing a character, an exterior outline, an interior outline, a horizontal line and a vertical line; classifying the coordinate information expressing a character, the exterior outline, the interior outline, the horizontal line and the vertical line, and then determining a pair of the horizontal line and the vertical line; and setting a skipping order at the time of a low pixel so as to be converted into character data for a bit map development composed of a control point coordinate for expressing the outline of the subject character, band information and coordinate value information about the control point which is not included in the band information.

Abstract: A multi-channel analog-to-digital converter includes a counter (20) and a plurality of analog-to-digital conversion cells (10), each of which contain incremental discharge means (11-16) that store a charge proportional to the voltage value of an analog input signal and discharge that charge in increments upon the occurrence of the clock signal, also producing an active signal after the charge has been stored and before the incremental discharge is complete. A register (17) receives a count signal from the counter (20) and stores its value when the active signal goes inactive. A multiplexer (18) selects among the outputs of the plurality of analog-to-digital conversion cells (10) and supplies the selected output as a digital output signal.

Abstract: A digital to analog converter employs an operational amplifier as an active summing device for summing a first analog voltage corresponding to most significant bits of a digital value and a second analog voltage corresponding to least significant bits of the digital value. In a multi-channel application, a single MSB DAC can be shared by all channels through first MUXs in each channel with each channel having an independent LSB DAC. Alternatively, a single LSB DAC can be shared by all channels through second MUXs in each channel. Gain of the voltage summing operational amplifier in each channel is determined by values of a resistor connecting the output of the LSB DAC to the inverting negative input of the operational amplifier and of a feedback resistor connecting the amplifier output to the inverting negative input.

Abstract: In a control system for peripheral devices, by operating only one device for digital-to-analogue conversion, the specific output switching corresponding to that specific device for digital-to-analogue conversion is closed and the other output switching corresponding to the other device for digital-to-analogue conversion are open so that the only the output signal of that specific device for digital-to-analogue conversion can be output. Thus, the accuracy of operation of each device for digital-to-analogue conversion can be easily evaluated.

Abstract: An analog-to-digital conversion system and method provide selectable data formats for each converted digital result value. Each digital result is stored in a register or table word. Information from a host processor is used to select a desired data format. In one embodiment the address range used to read the digital result serves to select the appropriate data format option, which may be, for example, left-justified or right-justified data, and signed or unsigned data. In another embodiment, one or more command words from the processor are used to select the desired data format.

Abstract: A data processing unit according to the present invention has a central processing unit, and an analog-to-digital converter circuit associated with a plurality of input nodes respectively supplied with analog signals. The analog-to-digital converter circuit is established in one of three modes of operations, i.e., a fixed mode of operation for focusing the A/D converting operation on one analog signal of a specified input node, a scanning mode of operation for sequentially converting the analog signals into corresponding digital signals and a mixed mode of operation for performing the fixed mode of operation once or a predetermined number of times before automatically returning to the scanning mode of operation, so that the central processing unit does not need to shift the analog-to-digital converter circuit from the fixed mode to the scanning mode if the mixed mode is selected, thereby improving the throughput of the central processing unit.

Abstract: An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value.

Abstract: There are provided 2.sup.n -number of data latches (2), 2.sup.n -number of dynamic range setting latches (7) and 2.sup.n -number of output dynamic range change circuits (8) in correspondence to 2.sup.n -number of D/A converters. Controlled by the outputs of AND gates (4), the respective dynamic range setting latches (7) output dynamic range setting data DR to the corresponding output dynamic range change circuits (8). The output dynamic range change circuits (8) change dynamic ranges for the analog outputs of the corresponding D/A converters (5) as a function of the dynamic range setting data DR to output the changed analog outputs from corresponding output terminals (26).This enables the dynamic ranges for the plurality of D/A converters to be set individually without the provision of further external terminals.

Abstract: The encoder is particularly for high speed and high resolution flash analog-to-digital converters. The number of components is drastically reduced, error correction scheme extended, the conversion speed and reliability increased. A suitable error correction can be accomplished by changing content of the decoders. The encoder comprises a register for sampling and interim storage of the input code, and providing a plurality of section codes, a plurality of section decoders for converting the section codes into a first portion of the output code, and a selective circuit for selecting one of the section codes in response to the first portion of the output code and converting the selected section code into a section portion of the output code.

Abstract: A dual range A/D converter includes means for appending a predetermined number N of random noise bits to the N least significant bits of the digital signals output from one of the dual A/D converters, thereby providing a total output bit resolution that is independent of the input analog signal.

Abstract: Apparatus for time multiplexed oversampled analog to digital modulation is provided. Embodiments include modulators (60 and 300) and focal plane optical imagers (100, 160 and 200). The apparatus includes a plurality of storage elements (70) to hold modulation residues. Multiplexor and demultiplexor structures (72, 74) enable residues to be updated and stored for a plurality of modulated signals.

Abstract: An audio/video signal combination apparatus for a digital audio tape recorder, is capable of combining 10 bit audio signal with 5 bit video signal by an automatic addressing, comprising analog/digital converters for converting audio signal and video signal into 10 bit and 5 bit digital data, a frame memory for storing digitized video signal by one frame, a digital signal processor for processing the 10 bit audio data and the 5 bit video data to one byte recording signal, and an automatic addressing unit for inputting the 5 bit video data stored in the frame memory to the digital signal processor when the digital signal processor reads the 10 bit audio data.

Abstract: An equalization method is provided for compensating for variations in the characteristics of individual analog-to-digital converters found in a time interleaved analog-to-digital converter circuit. One of a plurality of converters is chosen as a reference converter. Individual characteristics of the remaining converters are compared with the reference converter to provide differential responses therewith. The differential responses are equalized to provide compensation for variations in gain, offset, phase/frequency response, and timing found amongst the plurality of time interleaved converters.

Abstract: A digital-to-analog converter (20) includes a linear interpolator (24) and a converter (25, 26) such as a sigma-delta modulator (25) and an associated analog summing network (26). The linear interpolator (24) includes a differentiator (200), an integrator (202), and a multiplexer (201). The differentiator (200) differentiates a received signal at a first rate. The multiplexer (201) multiplexes an output of the differentiator (200) to provide a multiplexed signal having a larger number of bits than the received signal in order to support multiple interpolating ratios. The integrator (202) integrates the multiplexed signal at a second rate to present to the converter (25, 26). By connecting the multiplexer (201) between the differentiator (200) and the integrator (202), the digital-to-analog converter (20) minimizes the size of the linear interpolator (24) while relieving a critical path between the linear interpolator (24) and the converter (25, 26).

Abstract: A single analog-digital converter (either analog-to-digital or digital-to-analog) is employed to simultaneously digitize both an AC information signal and a low frequency or DC control signal. The separate signals are added prior to conversion and are separated according to their frequency after conversion. Thus, a DC control signal can be digitized without the need for a second converter and without substantially reducing the dynamic range available for converting the main information signal.

Abstract: A digital to analog conversion system includes two digital to analog converters, a selector circuit and a control circuit. Each digital to analog converter generates an output signal having a voltage level which can be varied in response to a control signal. The selector circuit is connected to the digital to analog converters for selectively coupling as a system output signal the output signal from one of the digital to analog converters in response to a selection signal.

Abstract: An A/D converter comprising a plurality of inputs, an input selection array to select one of the input signals, an A/D circuit providing a digital output and a conversion completion signal, a counter for sweeping a contiguous subset of the input channels sequentially, the counter incrementing once each time the conversion completion signal is asserted and resetting to point to the first channel in the subset after reaching the last channel in the subset, a channel memory for storing the value of the counter while an optional channel is selected for conversion without regard to the present position of the sweeping counter, a return bus, activated by the conversion completion signal, for replacing the value of the counter after the optional conversion is complete and returning to the normal sweep sequence in the previous position in the sequence, thereby avoiding useless conversion operations.

Abstract: A signal mixing apparatus utilizing digital signal processing technology for mixing digital signals comprising parallel data of plural channels include an analog addition circuit for adding, in analog, data of the same bit of parallel input data in plural channels, an analog-to-digital conversion circuit for converting added analog data of respective bits to digital data, and a digital addition circuit for adding, in digital, the converted digital data of all bits together. Since the data of the same bit of parallel input data of plural channels are added together in analog through the analog addition circuit such as a bus and an analog adder, digital input data of a large number of channels can be mixed together with a small amount of wiring.

Abstract: An infrared Fourier transformation spectrometer comprising a non-linear analog-to-digital converter device having at least one amplifier and one sample and hold circuit connected downstream thereof, as well as an an analog-to-digital converter following the latter, wherein an input signal to be converted is to be supplied to one input of the amplifier and the gain of the input signal is a function of the magnitude fo the input signal, and wherein the output signal of the analog-to-digital converter is evaluated giving regard to the respective gain, is characterized by the fact that at least two analog-to-digital converters are provided whose outputs are connected to a first controllable switching arrangement for supplying selectively the output signals of one of the said analog-to-digital converters to another evaulation means and that the input signal is supplied to each of the said analog-to-digital converters amplified by a different amplification factor.

Abstract: A partial word to full word parallel data shifter comprises 2N-1 multiplexer for selectively receiving data from the incoming current data word of width up to N, or from remainder bits of previously received data. The multiplexers output their data to 2N-1 latches, N of which output a full parallel data word and N-1 of which can recirculate up to N-1 remainder bits back to the multiplexers. If the number of remainder bits plus the number of data bits for the currently received word is less than N, the bits in the first N latches are not output but rather recirculate to the multiplexers where they are aligned for generating a full N bit output word with the most significant bit(s) of the next incoming parallel data.

Abstract: An A/D conversion apparatus includes an analog input selecting device, and A/D converter and an operation control device. The operation control unit issues an input terminal designating signal to the analog input selecting device in accordance with an optionally designated A/D conversion order. Then, the analog input selecting device successively selects the analog input terminals in the designated order. The A/D converter A/D-converts the analog signals from the input terminals selected into digital values. In this way, the A/D conversion for the analog signals can be made in any priority, or the order of scanning the input terminals can be optionally set.

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Abstract: In a communications system, input digital samples are continuously stored into a buffer and successively divided into a group of blocks of different lengths. The samples of each of the blocks are encoded into linear transform coefficients at intervals corresponding to the length of each block and each block of the linear transform coefficients is then decoded into a variable length block of decoded samples. An error between each block of decoded samples and a corresponding block of samples from the buffer is detected, and a plurality of such errors derived from each group of blocks of input samples are stored in memory. A minimum value of the errors in the memory is determined and one of the blocks of the coded symbols which corresponds to the minimum value is identified as having an optimum block length. The linear transform coefficients of the optimum block length are multiplexed with the optimum block length information into a channel for transmission.

Abstract: An analog-to-digital conversion system module comprises a pin-limited A/D converter integrated circuit (I.C.) to which at least one multiplexer I.C. may be coupled and sampled.In one embodiment, host system software involvement is minimized by providing a sequence of sample commands, implemented by a channel sequencer or a programmable control table comprising a plurality of conversion command words (CCW's). A set of CCW's defines a conversion sequence which may be initiated and performed with minimal host system software involvement, upon conclusion of which a result table storing the converted digital values may be read by an associated device, such as a CPU.In one embodiment, some I/O pins of the A/D converter I.C. function either as analog inputs or address outputs to the external multiplexer, while other analog input pins alternatively function as single input channels or as combined channels from one or more external multiplexers.

Abstract: A D/A conversion circuit is provided in which the polarities of a series of input digital data are reversed with every other data block, and the original digital data and the reversed digital data are alterntely D/A converted. An output analong signal is obtained by subtraction between the two D/A converted analog signals.With the above-mentioned arrangement, the D/A conversion circuit has a dynamic range equivalent to that using two D/A converters even with a single D/A converter.

Abstract: An n-bit DAC of the kind having at least 2.sup.n -1 sources, typically current sources, especially for use in oversampling ADC's enables a resolution accuracy in excess of 18 bits by selecting the sources in a dynamic manner. A source selection circuit typically an at least 2.sup.n -1 to 2.sup.n -1 multiplexer, connected between the digital input lines and the DAC switches selects the sources based on a predetermined cyclic algorithm which converts DAC errors into noise and shifts the noise energy into unwanted parts of the spectrum.

Abstract: A converter including an even and an odd digital-to-analog converter for converting digital signals from a successive approximation circuit and controlling the odd and even converters and the analog-to-digital converter device to alternate conversion by the even and odd converters. The odd and even converters operate in oppostie phases such that while one is in an acquisition phase the other is in a conversion phase. Each of the odd and even converters includes a separate coarse digital-to-analog converter and a common fine digital-to-analog converter. The control circuit resets the fine digital-to-analog converter during an initial portion of the conversion phase of each of the coarse digital-to-analog converters. In a two stage flash converter, the first stage includes a single analog-to-digital converter and the second stage includes a single digital-to-analog converter and alternatingly operating even and odd analog-to-digital converters.

Abstract: A circuit for converting input analog signals to output digital signals including an analog-to-digital converter having an analog input, an offset input and a digital output that represents the value of a signal at the analog input offset by an amount related to the value of the signal at the offset input, signal conditioning circuitry for receiving the input analog signal and providing it to the analog input via one of a plurality of different paths or under one of a plurality of different conditions, the different paths or different conditions providing different offsets to the input analog signal, and an offset correction memory storing offset correction characteristics for respective paths or conditions and being connected to provide an offset signal based on the characteristic for a path or condition to the offset input.