Abstract: A method and apparatus to switch between two audio streams without creating a clicking transient. A first serial audio stream is brought into a serial shift register. A series of samples of that audio stream are multiplied by reducing coefficients until a contribution of the first audio stream reaches zero. Then, a second serial audio stream is brought into the serial shift register. Increasing coefficients are applied to a series of samples until a contribution of the second audio stream is one.

Abstract: A number P of single analog inputs receive an analog signal having a frequency F from a sensor electrode. A single digital output sequentially generates a number P of first digital signals coding the amplitude values of the analog signal. A first multiplexer with a number M of multiple analog inputs with a number N of single analog inputs receives the analog signal and outputs the analog signal on a multiple analog output with a number N of second single analog outputs. A phase sensitive amplifier with a number N of single analog inputs and a number N of single analog outputs is connected to the second single analog outputs of the fist multiplexer. A second multiplexer with a number N of single analog inputs and a single analog output is connected to the single analog outputs of the phase sensitive amplifier.

Abstract: The digital signal is provided to the digital-to-analog upconverter (40) such as through digital signal processing circuitry (70). A sample rate signal and a divided sample rate signal are provided by divider chain (96) using the clock input (44). The divided sample rate signal is used to drive the decode circuit (88). The digital outputs of the decoder circuit (88) is combined with the sample rate signal in a mixer (52) which in turn generates a digitally upconverted signal which drives a plurality of switches combined together to form the analog output (46).

Abstract: A system for data transmission and communication receives a plurality of Gigabit Ethernet data packets from multiple Gigabit Ethernet links. The system bit multiplexes the data packets, on a bit by bit basis, together onto a fiber optic link. At the output of the fiber optic link, the bits are demultiplexed into data packets and transmitted onto multiple Gigabit Ethernet links. The high speed fiber optic link transmits the data at higher speed than is possible over each individual Gigabit Ethernet link.

Abstract: At least one exemplary embodiment of the present invention includes a device that comprises a microprocessor, a multiplexing analog-to-digital converter integral to said microprocessor, and a reference voltage source connected to said multiplexing analog-to-digital converter. At least one exemplary embodiment of the present invention includes a method that comprises obtaining a signal at a multiplexing analog-to-digital converter integral to a microprocessor; and comparing a digital value of the signal to a reference digital value. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An ASIC for current, voltage and temperature measurements has signal inputs (RSHH, VBAT, ETS, ETR) for receiving input signals, several choppers, an amplifier, an analog/digital converter and a digital signal output for outputting the result of the measurement and for communicating with a higher-order control unit. The invention proposes that the measuring circuit contain several differential signal inputs (RSHH-RSHL, VBAT-RSHL, ETS-RSHL, ETR-RSHL and VBAT-ETS), wherein one respective chopper/multiplexer is arranged downstream of each signal input.

Abstract: An analog-to-digital converter is provided for converting multiple analog inputs into corresponding digital values. An output interface circuit uses differential signaling to reduce noise and interference induced in the analog portions of the analog-to-digital converter.

Abstract: A digital noise-shaping filter with real coefficients for delta-sigma data converters used in a digital amplifier, 1-bit digital/analog converter, 1-bit analog/digital converter and the like, and a method for making the same. The present digital noise-shaping filter has improved noise suppression performance and system stability and reduced calculation complexity. To this end, the digital noise-shaping filter comprises a noise transfer function expressed by NTF(z)=−1+a1z−1+a2z−2+&Lgr;+aNz−N. The noise transfer function has optimum real coefficients or real coefficients approximating them.

Abstract: An A/D converter arrangement comprises an A/D converter (6) to which analog signals from a plurality of signal channels (2) can be fed for A/D conversion. With the help of an appropriate control means (8), converter parameters of the A/D converter (6) or even other operating parameters of the A/D converter arrangement, such as certain functions performed in response to an A/D conversion which has been carried out for example, are set in a channel-specific way as a function of the signal channel (2) which is to be converted at the time.

Abstract: A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.

Abstract: An integrated digital controller for controlling power electronic devices and method of its use, comprises an analog-to-digital converting scanner module for scanning analog data inputs and used to create digital data correlated with the analog inputs, a loop control module operative to receive the digital data and used for controlling at least one control loop, and a pulse sequence generator (PSG) module used for generating a variety of fast, configurable, event-driven pulse sequences in cooperation with the PSG and scanner modules. The controller comprises optionally a CPU for managing various tasks and coordinate between the modules, means to create the events, and means for configuration and reconfiguration on-the-fly. The controller is preferably integrated in a semiconductor chip.

Abstract: At least one exemplary embodiment of the present invention includes a device that comprises a microprocessor, a multiplexing analog-to-digital converter integral to said microprocessor, and a reference voltage source connected to said multiplexing analog-to-digital converter. At least one exemplary embodiment of the present invention includes a method that comprises obtaining a signal at a multiplexing analog-to-digital converter integral to a microprocessor; and comparing a digital value of the signal to a reference digital value. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method for selectively and sequentially converting digital video data signals in three formats, namely, standard definition, progressive scan and high definition formats to analogue form such that the same analogue reconstruction filter can be used for filtering the analogue forms of the signals after conversion. The digital signals prior to being converted are over-sampled at respective over-sampling frequencies for displacing image frequencies to frequencies sufficiently spaced apart from the widest band width signal so that the analogue reconstruction filter can be provided for filtering the widest band width signal as well as the other band width signals and also can be provided with a relatively low roll-off rate of attenuation.

Abstract: A system includes a transceiver having mixers, variable gain amplifiers, a modulator, a local oscillator and power amplifiers that may receive control signals generated by a Digital-to-Analog Converter (DAC). The DAC may include a multiplexer that receives digital values that are transferred to a DAC core, converted to analog values, and stored in sample-and-hold circuits. The one DAC may service multiple devices within the transceiver with control signals. A smart timer may generate select signals to the multiplexer and sample-and hold circuits to prioritize updating of the control signals.

Abstract: A multi-channel analog/digital (A/D) converter and a system includes a programmable memory on which a channel selection order is recorded, a channel selection unit which selects one of multiple channels according to the channel selection order recorded on the programmable memory, and a converting unit which converts an analog signal of the selected channel into digital data. With the A/D converter, a channel selection order and a sampling rate can be changed without changing the setup of hardware, and time delay can be reduced.

Abstract: An open-loop data recovery apparatus and method utilizing an oversampling technique is provided, by which the occurrence of data transitions is counted and a proper sampling clock phase is decided. Counters with variable thresholds are used to monitor the occurrence of phase transitions for a phase selection circuit to determine a preferred phase for recovery of sampled data. The thresholds of the counters are further adjusted in reference with the preferred phase decided by the phase selection circuit.

Abstract: A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

Abstract: The apparatus of the present invention comprises: at least one sensor, a bus line, a signal processing unit, a multiplexer, an A/D converter, a serial port interface, an optical fiber and a battery power source. The sensor is attached to the living body for sensing signals. The bus line is connected to the sensor for receiving the sensed signals. The signal processing unit has multiple signal processing circuits for generating multiple analog signals in response to the sensed signals. The multiplexer is connected to the signal processing unit for selecting one of the analog signals. The A/D converter converts the selected analog signal into a serial digital signal. The serial port interface adjusts the serial digital signal with standard serial port level. The optical fiber converter converts the adjusted digital signal into an optical signal. The battery power source provides the required power for the apparatus.

Abstract: A multiplexed signal processor is described as having an input circuit for receiving multiple input signals. A modulator processes a selected input signal to produce a representative digital output. The modulator includes an integrator that integrates the difference between the selected input signal and a feedback signal representative of the digital output. A signal control circuit selects in turn by time division multiplexing each input signal for a processing period as the selected input signal, and stores the digital output and the integrator state at the end of each processing period. After an initial processing period for each input signal, each processing period begins based on the digital output and the integrator state from the end of the previous processing period for that input signal.

Abstract: A system includes a transceiver having mixers, variable gain amplifiers, a modulator, a local oscillator and power amplifiers that may receive control signals generated by a Digital-to-Analog Converter (DAC). The DAC may include a multiplexer that receives digital values that are transferred to a DAC core, converted to analog values, and stored in sample-and-hold circuits. The one DAC may service multiple devices within the transceiver with control signals. A smart timer may generate select signals to the multiplexer and sample-and hold circuits to prioritize updating of the control signals.

Abstract: An interleaving AD conversion type waveform digitizer apparatus includes, in a case where the number of interleaving ways is N that is equal to or larger than two, N AD converters connected to a structure for interleaving. The sampling timings of the respective AD converters are predetermined timings corresponding to the interleaving structure so as to allow successive outputs. The digitizer receives a signal to be measured output from a device under test and performs quantization. The time-series data from the AD converters are subjected to Fourier Transform by a butterfly operation technique. The digitizer apparatus further includes a window function multiplier for determining a coefficient based on a phase error, and a butterfly operation unit for performing a butterfly operation by inserting a phase correction coefficient.

Abstract: The present invention provides a single analog-to-digital converter system which is capable of converting an input signal having a high dynamic range into a digital signal which is within the range of the analog-to-digital converter. Additionally, the present invention provides an analog-to-digital converter which is capable of converting an input signal having a high dynamic range into a digital signal by controlling the amplification of the signal to achieve the optimal gain that falls within the range of the analog-to-digital converter.

Abstract: A microcomputer for performing an inverter control includes three AD converters provided therein. The first and second AD converters are used for a motor control, and each receive a motor position detection signal. The third AD converter is used for a power supply control, and receives an analog signal representing the state of the power supply. Therefore, a motor control and a power supply control are performed by using separate AD converters, whereby it is possible to optimally perform each control without an AD conversion having to wait for another AD conversion to be completed.

Abstract: A multi-channel DAC having a digital input port (2) for receiving digital input codes and a plurality of analogue output terminals (OUT1 to OUTN) on channels (CH1 to CHN) on which corresponding analogue signals are outputted, comprises a primary DAC (3) which receives the digital input codes from the input port (2). Analogue signals from the primary DAC (3) are selectively and sequentially sampled onto infinite sample and hold circuits (SH1 to SHN) of the channel (CH1 to CHN) through primary switches PS1 to PSN) under the control of a primary control circuit (5). Each infinite sample and hold circuit (SH1 to SHN) comprises a secondary DAC (10) which outputs an analogue signal which closely approximates to the sampled analogue signal from the primary DAC (3) and which is held on the corresponding output terminal (OUT1 to OUTN).

Abstract: A method and device automatically convert a plurality of analog input channels using a single analog to digital conversion circuit. The device includes a multiplexer, an analog to digital conversion circuit and a configurable channel controller. The multiplexer has at least two analog input channels. The multiplexer also has control inputs and an output. The analog to digital conversion circuit is coupled to the output of the multiplexer and a clock signal. The analog to digital conversion circuit outputs a conversion value based on a voltage associated with the output of the multiplexer in successive clock cycles. The configurable channel controller outputs a control signal to the control inputs of the multiplexer to automatically select successive ones of the at least two analog input channels for conveying to the analog to digital conversion circuit.

Abstract: The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal.

Abstract: A signal to be produced, which represents a digital data stream, is generated using the currents or voltages from current or voltage sources selected from multiple current or voltage sources. The current or voltage sources whose currents or voltages are used to generate the signal which is to be produced are selected based on the contents of the elements of a shift register whose input connection has the signal which is to be filtered applied to it.

Abstract: An input delay correcting system for an interleave type A/D converter is to be provided.

Abstract: An analog switch and an analog multiplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.

Abstract: A method for selectively and sequentially converting digital video data signals in three formats, namely, standard definition, progressive scan and high definition formats to analogue form such that the same analogue reconstruction filter can be used for filtering the analogue forms of the signals after conversion. The digital signals prior to being converted are over-sampled at respective over-sampling frequencies for displacing image frequencies to frequencies sufficiently spaced apart from the widest band width signal so that the analogue reconstruction filter can be provided for filtering the widest band width signal as well as the other band width signals and also can be provided with a relatively low roll-off rate of attenuation.

Abstract: An apparatus and method for converting digital input signals sampled at different rates to analog signals includes a digital to analog converter for each digital input signal. Each digital to analog converter receives a digital input signal and a clock signal corresponding to the sampling rate of the received digital input signal. The apparatus can also receive a set of sample rate signals indicating the sampling rate for each digital input signal. The sample rate signals are used to route each digital input signal, along with a corresponding clock signal, to a corresponding digital to analog converter (DAC). A clock error signal controls routing of the digital input signals to the DACs as well as operation of the DACs. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.

Abstract: A method and apparatus for generating reference voltages for a flat panel display system comprising using a digital to analog converter (DAC) 12 to supply multiple reference voltages to the flat panel display system, and wherein the DAC 12 is adapted to accept digital input voltage reference from one of a plurality of registers 14 and is adapted to provide an analog output to one of a plurality of sample and hold circuits 18. A controller 16 selects which one of the plurality of registers 14 is coupled to the DAC 12 input, and selects which one of the plurality of sample and hold circuits 18 is coupled to the DAC 12 output.

Abstract: A multiplexed signal processor is described as having an input circuit for receiving multiple input signals. A modulator processes a selected input signal to produce a representative digital output. The modulator includes an integrator that integrates the difference between the selected input signal and a feedback signal representative of the digital output. A signal control circuit selects in turn by time division multiplexing each input signal for a processing period as the selected input signal, and stores the digital output and the integrator state at the end of each processing period. After an initial processing period for each input signal, each processing period begins based on the digital output and the integrator state from the end of the previous processing period for that input signal.

Abstract: A method and apparatus are used to process a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information. Command bits are set over a serial port input pin, and include at least one pointer bit indicative of a selected logical channel. In response to the command bits, the serial port controller sends signals indicative of the physical channel and the converter property specified in the selected logical channel to the ADC components.

Abstract: A parallel analog-to-digital converter device has parallel converter cells signal (u) appearing at an input line. The cells are clocked by a common clock signal delayed by delay elements for the respective cell. Timing errors of the sampling times are determined in a calculation unit receiving the output signals of the cells. The output signal of the total converter is compensated by a compensation device for the determined timing errors to provide corrected sampled values on the output line of the converter. In the calculation unit sums of squared differences of the sampled values for successive cells are calculated which by simple operations provide estimates of the timing errors. In the calculation unit also a variance of noise superposed on the sampled values can be estimated and then used to correct the calculated sums for the variance. The input signal is basically unknown and the determination of the timing errors works without using any calibration signal.

Abstract: A PC card and corresponding WLAN system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a PC card (302) and corresponding WLAN system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: An analog-to-digital conversion circuit converts parallel analog voltage signals into corresponding parallel analog current signals. The analog-to-digital conversion circuit multiplexes the parallel analog current signals into a time-interleaved analog current signal. The analog-to-digital conversion circuit converts the time-interleaved analog current signal into a corresponding time-interleaved analog voltage signal and provides gain for the time-interleaved analog voltage signal. The analog-to-digital conversion circuit converts the time-interleaved analog voltage signal into a corresponding digital signal having time-interleaved digital values corresponding to the parallel analog voltage signals.

Abstract: An integration type A/D converter has two sets of integration type A/D converter sections which can be periodically switched over at a predetermined period, with one converter section integrating an input signal to give an integral output voltage and another converter section performing A/D conversion of the integral output voltage. Further, use is made of a residual time interval in the period of A/D conversion, for the integration of the ground voltage and a reference voltage and for A/D conversions of the integrated voltages. The inventive A/D converter permits accurate measurement of continuous integral values of a given input signal.

Abstract: A dual analog-to-digital (A/D) converter circuit having two separate channels coupled to receive a single analog input signal, each of the two channels includes a means for converting an analog input signal to a digital signal at respective sample times that are adjustable to be substantially simultaneous; a means for adjusting the gain of the two channels to differ by a predetermined factor; a means for detecting a channel overflow condition in one of the two channels having a higher gain; and a means for merging the two channels into a continuous output stream.

Abstract: A digital-to-analog (D/A) converter with a required accuracy can be implemented in a smaller chip area and at a lower cost. The D/A converter comprises a decoder which receives a digital input signal comprised of a first number of bits, and divides the first number of bits into a second number of bit groups. Bit group converters equal in number to the second number, are provided for the second number of bit groups, and each selects and uses a form of weight for each of the bit groups associated therewith to convert the bit group into an analog form in response to the second number of bit groups, thereby generating the second number of bit group analog outputs. An adder adds the second number of the bit group analog outputs to form an analog signal output representative of the digital signal input.

Abstract: A method for A/D conversion of analog signals using an A/D converter, and to an appropriate A/D converter circuit. In order to process converter request signals from different converter request sources requesting analog signals for conversion, the invention proposes assigning definable, selectable priorities to the different converter request sources. If there is a request for A/D conversion from a converter request source, the system establishes which of the converter request sources requesting A/D conversion has the highest priority. An analog signal from this selected converter request source is then supplied to the A/D converter.

Abstract: An input circuit of a one-chip microcomputer is connected to an external switching circuit. When an analog input signal of a significant level generated in the external switching circuit is received at an analog input terminal of the input circuit, an A/D conversion start request signal is generated in an A/D conversion start request generating circuit and is sent to an A/D converter. The operation of the A/D converter is started in response to the A/D conversion start request signal, the analog input signal received at the analog input terminal is converted into digital data, and an A/D conversion finish signal is sent from the A/D converter to a CPU of the one-chip microcomputer. The operation of the CPU is started in response to the A/D conversion finish signal, and the digital data is readout to the CPU.

Abstract: A digital system is provided with an Analog to Digital converter (ADC) that has a configuration that allows a programmable number of Auto conversions to occur on two separate and independent, but cascadeable, sequencers (or state machines). For each conversion state, the sequencer/s can be programmed to arbitrarily select any one of a set of muxed analog input channels. In addition, each conversion state has a unique result register in which the converted value is placed at completion of conversion. This ADC control system gives the capability to set up various forms of input signal sampling strategies. For example, one such strategy samples and converts the same channel multiple times allowing an over-sampling algorithm to be easily performed. By over sampling, increased resolution over traditional single sampled conversion systems can be obtained by suitable processing of the over-sampled results.

Abstract: Analog-to-digital converter for converting an analog input signal which is present at a signal input (2a, 2b) and has a specific frequency bandwidth, into an offset-free digital output signal, having a subtracting amplifier (5), which subtracts an analog actuating signal from the analog input signal in order to generate an analog difference signal and amplifies the analog difference signal generated, an analog-to-digital converter circuit (18) having a high clock rate for converting the amplified analog difference signal into the digital output signal, a digital clamping circuit (24) for digital low-pass filtering of the digital output signal, and having a digital-to-analog converter circuit (49) for converting the digital output signal filtered by the clamping circuit (24) into the analog actuating signal.

Abstract: A D/A conversion circuit is described which comprises a n switching, n capacitors and a coupling circuit. Upper n bit of the digital signal control n switches respectively and control charging and discharging of electric charge into the n capacitors, and the n capacitors are connected to the output line in an upper bit writing period. Lower n bit of the digital signal control the n switches and control charging and discharging of electric charge into the n capacitors, and the capacitors are connected to the output line through the coupling capacitor in a lower bit writing period.

Abstract: A PC card and corresponding WLAN system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a PC card (302) and corresponding WLAN system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.

Abstract: In one aspect, the present invention is directed to a converter for converting a signal from a first format to a second format. The converter includes a decomposition section, a converter array operatively coupled to the decomposition section, and a recombination section operatively coupled to the converter array. The decomposition section includes an input to receive the input signal, a splitter to divide the input signal into a plurality of signals, a plurality of signal outputs, each of which provides as an output one of the plurality of signals, and a clock circuit having a plurality of clock outputs for providing sample clocks to the converter array. The converter array includes a plurality of converters each having a signal input to receive one of the plurality of signals, each having a clock input to receive one of the sample clocks and each having an output that provides a converted signal.

Abstract: An apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

Abstract: An image signal processing circuit (102) includes a phase-expansion circuit (103), a digital polarity-inversion circuit (104), first to sixth D/A converters (111 to 116), and first to sixth operational amplifiers (151 to 156). The resistance value of the first to sixth amplitude adjusting resistors (121 to 126) which cause the output amplitude of an analog signal output from the first to sixth D/A converters (111 to 116) to be fixed is adjusted by laser trimming. First to sixth gain setting resistors (161 to 166) are connected to the first to sixth operational amplifiers (151 to 156). The first gain setting resistor (161) includes a first resistor (131) and a second resistor (141), and the gain of the operational amplifier (151) is set by the resistance ratio (R2/R1) thereof. In order that this resistance ratio (R2/R1) is fixed for each set, the first resistor (131) and the second resistor (141) are formed on the same substrate by undergoing the same manufacturing process.