Differential Encoder And/or Decoder (e.g., Delta Modulation, Differential Pulse Code Modulation) Patents (Class 341/143)
  • Patent number: 11984902
    Abstract: A digital decimation filtering circuit of an analog to digital conversion circuit includes an n-tap anti-aliasing filter operable to receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate and filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate. The digital decimation filtering circuit further includes a decimator operable to receive the n-bit filtered signal at the first data output rate, decimate the n-bit filtered signal by a decimation factor to produce a set of output signals, and sum the set of outputs to produce a decimated signal at a second data output rate. The first data output rate is greater than the second data output rate.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: May 14, 2024
    Assignee: SIGMASENSE, LLC.
    Inventors: Grant Howard McGibney, Patrick Troy Gray, Gerald Dale Morrison, Daniel Keith Van Ostrand
  • Patent number: 11962317
    Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: April 16, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Behnam Sedighi, Shi Bu, Elias Dagher, Dinesh Jagannath Alladi
  • Patent number: 11953928
    Abstract: In an embodiment an electric circuit arrangement includes a current generator circuit having a first output terminal and configured to generate an output current, a controller configured to generate control signals to control the current generator circuit, a random code generator configured to generate random codes and a counter configured to generate a count, wherein the current generator circuit comprises a plurality of output current paths and a plurality of controllable switching circuits, wherein each of the output current paths includes a respective electrical component to define a current in the respective output current path, wherein a respective one of the controllable switching circuits is coupled to a respective one of the output current paths to connect the respective electrical component to the first output terminal, and wherein the random code generator is configured to provide a respective code derived from a respective one of the random codes.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 9, 2024
    Assignee: Sciosense B.V.
    Inventors: Alberto Maccioni, Massimiliano Franzolin, Monica Schipani, Fabrizio Mannozzi
  • Patent number: 11942940
    Abstract: Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: March 26, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Aaron Shreeve, Chun Cheung, Michael Jason Houston, Mehul Shah
  • Patent number: 11937052
    Abstract: A method for updating a user model and fitting agent for a hearing device system is disclosed, the hearing device system comprising a hearing device worn by a hearing device user, wherein the fitting agent comprises one or more processors configured to initialize a user model comprising a plurality of user preference functions and associated user response distributions, wherein each user preference function is associated with an environment; obtain environment data indicative of a present environment; obtain a test setting comprising a primary test setting and a secondary test setting for the hearing device; present the test setting to the hearing device user; obtain a user input of a preferred test setting indicative of a preference for either the primary test setting or the secondary test setting; and update the user model based on hearing device parameters of the preferred test setting and the environment data.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 19, 2024
    Assignee: GN HEARING A/S
    Inventors: Aalbert De Vries, Tanya Ignatenko, Kirill Kondrashov
  • Patent number: 11923866
    Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: March 5, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsuan-Ting Ho, Shih-Hsiung Huang, Liang-Wei Huang
  • Patent number: 11916707
    Abstract: Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 27, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Abhishek Bandyopadhyay, Atsushi Matamura
  • Patent number: 11906877
    Abstract: A system and method to convert a wideband optical signal to a multi-bit digital electrical signal using a superconducting integrated circuit. In a preferred embodiment, the optical signal modulates the phase (i.e., adjusts the timing) of a sequence of single-flux-quantum voltage pulses. The optoelectronic modulator may comprise an optically tunable Josephson junction, superconducting inductor, or bolometric detector, with switching speeds approaching 100 ps or less. The optical signal may comprise a plurality of optical signals such as a wavelength-division multiplexed signal. The optical-to-digital converter may be applied to high-speed digital communication switches, broadband digital input/output for superconducting or quantum computing, and control/readout of detector arrays.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 20, 2024
    Assignee: SeeQC, Inc.
    Inventors: Oleg A. Mukhanov, Igor V. Vernik
  • Patent number: 11909410
    Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Sharad Gupta
  • Patent number: 11910116
    Abstract: A photoelectric conversion device includes a pixel array and a reading unit including a plurality of reading circuits each configured to read a signal from the pixel array. Each reading circuit includes a sample-and-hold unit including a first sample-and-hold circuit configured to hold a reset level output from the pixel array and a second sample-and-hold circuit configured to hold a photo signal level output from the pixel array. The plurality of reading circuits include first reading circuits forming a first group and second reading circuits forming a second group. At least some of the plurality of first reading circuits are controlled by a first control signal given via a first control line, and at least some of the plurality of second reading circuits are controlled by a second control signal given via a second control line.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 20, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Daisuke Yoshida
  • Patent number: 11908516
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Patent number: 11894864
    Abstract: In one embodiment, an analog-to-digital converter includes: a sum circuit to receive an analog input signal and a feedback reference signal and generate a sum signal; a feedback circuit coupled to the sum circuit to provide the feedback reference signal to the sum circuit; a filter coupled to the sum circuit to receive the sum signal and generate a filtered signal; and a punctured quantizer coupled to the filter to receive the filtered signal and quantize the filtered signal to a digital output and to output the digital output and to provide the digital output to the feedback circuit.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 6, 2024
    Assignee: Silicon Laboratories Inc.
    Inventor: John M. Khoury
  • Patent number: 11881888
    Abstract: An electronics (100, 200) including an electrical isolation is provided. The electronics (100, 200) include a bidirectional isolation circuit (110, 210) separating a first portion (100a, 200a) from a second portion (100, 200b) and a bus transceiver switch (120b, 220b) disposed in the second portion (100b, 200b). The bus transceiver switch (120b, 220b) is communicatively coupled to the bidirectional isolation circuit (110, 210). The bus transceiver switch (120b, 220b) receives from the bidirectional isolation circuit (110, 210) a communication control signal provided by the first portion (100a, 200a).
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: January 23, 2024
    Assignee: Micro Motion, Inc.
    Inventor: Brian T. Smith
  • Patent number: 11876524
    Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0?), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventor: Muhammed Bolatkale
  • Patent number: 11870453
    Abstract: Systems and methods are provided for analog-to-digital conversion (ADC). A first quantization stage may be configured to receive an analog input signal and sample the analog input signal to generate a first digital signal, the first quantization stage may be further configured to filter the first digital signal with a first noise-shaping transfer function to generate a first noise-shaped digital output and to generate a quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output. A voltage controlled oscillator (VCO)-based second quantization stage may be configured to receive the quantization error signal and sample the quantization error signal to generate a second digital signal, the VCO-based second quantization stage may be further configured to filter the second digital signal with a second noise-shaping transfer function to generate a second noise-shaped digital output.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 11863205
    Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 2, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Abhishek Bandyopadhyay, Kaibo Miao, Langyuan Wang
  • Patent number: 11861814
    Abstract: Disclosed herein are an apparatus and method for sensing an image based on an event. The apparatus includes memory in which at least one program is recorded and a processor for executing the program. The program may perform acquiring at least one of brightness information and color information from an input image signal, performing conversion including at least one of filtering of at least one of the acquired brightness information and color information, color conversion, and brightness conversion, calculating a quantized difference between a first converted image converted from the currently input image signal and a second converted image converted from a previously input image signal, and generating event information for the input image signal as a bitstream based on the quantized difference.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 2, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong-Il Seo, Hyon-Gon Choo
  • Patent number: 11855660
    Abstract: In an embodiment, an ADC converter includes a first injection branch and a second injection branch, a first feedback branch and a second feedback branch, an integration node connected to the first and second injection branches and the first and second feedback branches, an integrator connected to the integration node and a comparator connected downstream of the integrator and configured to generate a comparator output signal to control the first and second feedback branches, wherein the first and second injection branches are configured to provide a charge injection dependent on a respective input quantity to the integration node, wherein the input quantity of the first injection branch is selected from a differential voltage signal, a capacitance dependent signal and a current dependent signal, wherein the input quantity of the second injection branch is selected from another one of the differential voltage signal, the capacitance dependent signal and the current dependent signal, and wherein the first and s
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 26, 2023
    Assignee: Sciosense B.V.
    Inventors: Alberto Maccioni, Monica Schipani, Massimiliano Franzolin, Fabrizio Mannozzi
  • Patent number: 11821731
    Abstract: Facilitating minimization of non-linearity effects of a delay of a capacitance-to-voltage (C2V) converter on an output of a gyroscope is presented herein. A sense output signal of a sense mass of the gyroscope and a drive output signal of a drive mass of the gyroscope are electronically coupled to respective analog-to-digital converter (ADC) inputs of bandpass sigma-delta ADCs of the gyroscope. The bandpass sigma-delta ADCs include respective C2V converters that are electronically coupled, via respective feedback loops, to the respective ADC inputs to facilitate reductions of respective propagation delays of the bandpass sigma-delta ADCs. Respective ADC outputs of the bandpass sigma-delta ADCs are electronically coupled to demodulator inputs of a demodulator of the gyroscope that transforms the sense output into an output of the MEMS gyroscope representing an external stimulus that has been applied to the sense mass.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: November 21, 2023
    Assignee: INVENSENSE, INC.
    Inventors: Carlo Pinna, Sriraman Dakshinamurthy
  • Patent number: 11823740
    Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: November 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey Burr, Masatoshi Ishii, Pritish Narayanan, Paul Michael Solomon
  • Patent number: 11817875
    Abstract: A method for removing low frequency offset components from a digital data stream includes receiving, at an input of an analog-to-digital converter (ADC), an analog input signal from one or more analog front end components. The analog input signal has an associated low frequency offset due, at least in part, to the analog front end components. The method also includes generating, at an output of the ADC, a digital data stream representative of the analog input signal. The digital data stream having an associated low frequency offset due, at least in part, to the analog front end components and/or the ADC. One or more low pass infinite impulse response (IIR) filters are applied to the digital data stream to detect the low frequency offset components in the digital data stream, and generate a filtered output signal with only the low frequency offset components present.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 14, 2023
    Assignee: Schneider Electric USA, Inc.
    Inventor: Erin C. McPhalen
  • Patent number: 11809489
    Abstract: Methods and apparatus to audio watermarking and watermark detection and extracted are described herein. An example method includes receiving a media content signal, sampling the media content signal to generate samples, storing the samples in a buffer, determining a first sequence of samples in the buffer, determining a second sequence of samples in the buffer, wherein the second sequence of samples is of substantially equal length as the first sequence of samples, calculating an average of the first sequence of samples and the second sequence of samples to generate an average sequence of samples, extracting an identifier from the average sequence of samples, and storing the identifier in a tangible memory.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: November 7, 2023
    Assignee: The Nielsen Company (US), LLC
    Inventors: Venugopal Srinivasan, Alexander Topchy
  • Patent number: 11804917
    Abstract: Provided in the present disclosure are an electronic device and a method for wireless communication, and a computer-readable storage medium, the electronic device for wireless communication comprising a processing circuit, the processing circuit configured such that: if it is determined that the electronic device is in a frequency spectrum transaction verification region, verifying an effectiveness of a frequency spectrum transaction, the verification region being determined on the basis of interference generated when a frequency spectrum acquirer in the frequency spectrum transaction uses the transaction frequency spectrum; determining an electronic device signal-to-noise ratio according to interference of the electronic device when the frequency spectrum acquirer uses the transaction frequency spectrum, and if the signal-to-noise ratio is greater than a preset signal-to-noise ratio threshold configured for the electronic device, verifying that the frequency spectrum transaction is in effect.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: October 31, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Youping Zhao, Cong Lu, Chen Sun
  • Patent number: 11799494
    Abstract: A delta-sigma modulator which receives an input signal. The input signal is combined with a feedback signal and the combined signal is filtered by the delta-sigma modulator. The filtered signal is quantized, wherein the feedback signal is generated on the basis of the quantized signal. The quantized signal is output as an output signal. The input signal and/or the filtered signal and/or the feedback signal are filtered in such a way that at least one frequency in an out-of-band frequency range of the input signal is amplified in order to suppress out-of-band quantization noise at the at least one frequency.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: October 24, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Rudolf Ritter, Andreas Schmidt, Thorsten Balslink
  • Patent number: 11792588
    Abstract: A fitting agent, e.g. for update of a user model for a hearing device user, and related method is disclosed, wherein the fitting agent is configured to initialize a user model comprising a user preference function and/or a user response distribution; obtain a primary test setting for the hearing device; obtain a secondary test setting for the hearing device; present the primary test setting and the secondary test setting to a user; detect a user input of a preferred test setting indicative of a preference for either the primary test setting or the secondary test setting; and update the user model based on hearing device parameters of the preferred test setting, wherein to update the user model optionally comprises to determine a posterior of parameters of the user preference function, e.g. based on a previous parameter posterior, the preferred test setting, and a non-preferred test setting.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: October 17, 2023
    Assignee: GN HEARING A/S
    Inventors: Tanya Ignatenko, Kirill Kondrashov
  • Patent number: 11784615
    Abstract: A class-D amplifier with multiple “nested” levels of feedback. The class-D amplifier surrounds an inner feedback loop, which takes the output of a switching amplifier and corrects for errors generated across the switching amplifier, with additional feedback loops that also take the output of the switching amplifier.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: October 10, 2023
    Assignee: QSC, LLC
    Inventor: Anders Lind
  • Patent number: 11777516
    Abstract: A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path having an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: October 3, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: John L. Melanson, Axel Thomsen, Mucahit Kozak, Paul Wilson, Eric J. King
  • Patent number: 11757466
    Abstract: Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 12, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Preston S. Birdsong, Adam R. Spirer
  • Patent number: 11758308
    Abstract: A method for improving frequency response of a high-speed data acquisition device includes sampling signals received at an input of the high-speed data acquisition device at a first sampling rate and generating a digital data stream representative of the sampled input signals. The digital data stream is interpolated to generate an interpolated digital signal with a higher sample rate than the first sampling rate, and one or more finite impulse response (FIR) filters are applied to the interpolated digital signal to generate a filtered digital signal. The filtered digital signal corrects for: parasitic and/or expected response of elements from the network of resistors and capacitors in the anti-aliasing filter in the high-speed data acquisition device, and select anti-aliasing filter response characteristics. The filtered digital signal is decimated to reduce the sampling rate of the filtered digital signal and generate a decimated digital signal.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 12, 2023
    Assignee: Schneider Electric USA, Inc.
    Inventor: Erin C. McPhalen
  • Patent number: 11742871
    Abstract: Disclosed is a low power modulator with a VCO quantizer. The low power modulator with the VCO quantizer may include an integrator converting an input current to a voltage, a quantizer converting the converted voltage to digital information, a filter unit filtering the converted digital information, a DAC converting the filtered digital information into a feedback current, and a controller calculating the digital information output based on a difference value between the input current and the feedback current for each sampling time.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: August 29, 2023
    Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Seong Jin Kim, Jee Ho Park
  • Patent number: 11718190
    Abstract: A system comprises an inverter including a first galvanic isolator separating a low voltage area from a high voltage area, a second galvanic isolator separating the low voltage area from the high voltage area, a first bias network connected to the first galvanic isolator, a second bias network connected to the second galvanic isolator, a first filter connected to the first bias network, a second filter connected to the second bias network, a first amplifier connected to the first filter, a second amplifier connected to the second filter, and an open detector connected to the first amplifier and the second amplifier.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: August 8, 2023
    Assignee: Delphi Technologies IP Limited
    Inventors: Seyed R. Zarabadi, Srikanth Vijaykumar
  • Patent number: 11716074
    Abstract: A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 1, 2023
    Assignee: NXP B.V.
    Inventors: Shagun Bajoria, Lucien Johannes Breems
  • Patent number: 11716092
    Abstract: A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between a unipolar or bipolar analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.
    Type: Grant
    Filed: September 5, 2021
    Date of Patent: August 1, 2023
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Lars R. Furenlid, Maria Ruiz-Gonzalez
  • Patent number: 11693383
    Abstract: Systems and methods are provided herein for determining motion in a volume using a lighting based sensor. A status of a light is determined with which a motion sensor is associated. Motion measurements are received from the motion sensor. Based on the motion measurements, a motion score is determined. A room status is adjusted based on the motion score.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 4, 2023
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: David Smith, Neil Joseph
  • Patent number: 11695327
    Abstract: Embodiments of a power converter are disclosed. In an embodiment, the power converter comprises a power factor correction (PFC) stage circuit, an emulation circuit and a controller. The PFC stage circuit is configured to produce an output signal on an output terminal. The PFC stage circuit includes an inductor coupled between a rectifier and the output terminal and a switch coupled to the inductor. The emulation circuit is connected to the PFC stage circuit to generate an emulated current that corresponds to current through the inductor of the PFC stage circuit. The emulated current is generated based on a voltage signal at a node between the inductor and the output terminal and a sensed current at a sense resistor connected to the rectifier. The controller is connected to the emulation circuit to receive the emulated current and generate a control signal for the switch of the PFC stage circuit based on the emulated current.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 4, 2023
    Assignee: NXP B.V.
    Inventors: Hans Halberstadt, Alfred Grakist
  • Patent number: 11689214
    Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11686826
    Abstract: A semiconductor body includes a driver for driving a light source, at least two detectors each including an avalanche diode, a time-to-digital converter arrangement coupled to outputs of the at least two detectors, a memory that is coupled to the time-to-digital converter arrangement and is configured to store at least one histogram, and an evaluation unit coupled to the driver and to the memory.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 27, 2023
    Assignee: AMS AG
    Inventors: Kerry Glover, Manfred Lueger, Robert Kappel, Christian Mautner, Mario Manninger, Georg Roehrer
  • Patent number: 11677411
    Abstract: An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 13, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Nakatsuka, Hiroki Yoshino, Jun'ichi Naka, Koji Obata, Masaaki Nagai
  • Patent number: 11669069
    Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: June 6, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Romig, Mayank Garg
  • Patent number: 11664815
    Abstract: A digital filter is used in an A/D converter and includes a first filter and second filter. The first filter outputs first digital data by performing filter processing on output of an A/D conversion unit included in the A/D converter. The second filter outputs second digital data by performing filter processing on the output of the A/D conversion unit. The second digital data has either a lower resolution or a smaller effective number of bits than the first digital data does. The second filter outputs the second digital data before the first filter outputs the first digital data.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 30, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaaki Nagai, Hiroki Yoshino, Junji Nakatsuka, Jun'ichi Naka, Koji Obata
  • Patent number: 11658678
    Abstract: Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 23, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Preston S. Birdsong, Adam R. Spirer
  • Patent number: 11640797
    Abstract: A display driver integrated circuit (IC) is provided. The display driver IC includes a shift register configured to output a digital signal, and a digital-analog converter configured to receive the digital signal and generate a data voltage corresponding to the digital signal, wherein the digital-analog converter includes a delta-sigma modulator configured to output a modulated signal by receiving the digital signal and a first voltage, and performing delta-sigma modulation on the digital signal using the first voltage, and a level shifter configured to receive the modulated signal and a second voltage higher than the first voltage, and amplify the modulated signal using the second voltage.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 2, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Dong-Il Park
  • Patent number: 11637562
    Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 25, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Roberto Modaffari, Paolo Pesenti, Germano Nicollini
  • Patent number: 11593573
    Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: February 28, 2023
    Assignee: Ceremorphic, Inc.
    Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
  • Patent number: 11586883
    Abstract: Methods and apparatus are disclosed for providing emulation of quantized precision operations in a neural network. In some examples, the quantized precision operations are performed in a block floating-point format where values of a tensor share a common exponent. Techniques for selecting higher precision or lower precision can be used based on a variety of input metrics. When converting to a quantized tensor, a residual tensor is produced. In one embodiment, an error value associated with converting from a normal-precision floating point number to the quantized tensor is used to determine whether to use the residual tensor in a dot product calculation. Using the residual tensor increases the precision of an output from a node. Selection of whether to use the residual tensor can depend on various input metrics including the error value, the layer number, the exponent value, the layer type, etc.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 21, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric S. Chung, Daniel Lo, Jialiang Zhang, Ritchie Zhao
  • Patent number: 11581901
    Abstract: Systems, apparatuses, and methods for performing digital pre-distortion compensation of digital-to-analog converter non-linearity are described. A correction circuit receives a digital input word and couples a portion of the most significant bits (MSB's) of the digital input word to a correction lookup table (LUT). A correction value is retrieved from a correction LUT entry that matches the MSB's of the digital input word. Next, the correction value is added to the original digital input word in the digital domain. Then, the sum generated by adding the correction value to the original digital input word is optionally clipped if the sum exceeds the DAC core's input range. Next, the DAC core converts the sum into an analog value that is representative of the digital input word. The above approach helps to reduce non-linearities introduced by the DAC core in an energy-efficient manner by performing a correction in the digital domain.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: February 14, 2023
    Assignee: Apple Inc.
    Inventors: Dusan Stepanovic, Mansour Keramat
  • Patent number: 11581902
    Abstract: A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 14, 2023
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 11567551
    Abstract: A power supply comprises a control unit for adjusting a power output by the power control unit in response to a control signal. The power supply further includes a processing unit configured to generate the control signal using a control model and based at least on one or more sensor signals supplied to the processing unit. The processing unit is configured to communicate via an interface with an external processing entity to receive a data set for generating the control model and/or to receive the control model, and/or to transmit the model to the external processing entity.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: January 31, 2023
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Philipp Weigell, Sascha Kunisch
  • Patent number: 11563443
    Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 24, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Patent number: 11551071
    Abstract: A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: January 10, 2023
    Assignee: TDK CORPORATION
    Inventor: Yukio Terasaki