Abstract: A method for testing an analog-to-digital converter unit, which is equipped to convert an analog input signal into a digital output signal with the aid of delta-sigma modulation. The method includes: generating an analog input signal; applying a predefined interference signal to the analog input signal and storing the resulting digital output signal as test result; determining that a fault is present if a transfer function of the analog-to-digital converter unit, which is ascertained from the test result and the input signal, has a deviation from a predefined target transfer function that is greater than a predefined reference value, a fault signal being output if a fault is determined.

Abstract: The present disclosure generally relates to techniques and apparatus for implementing an envelope-tracking power supply for a radio frequency (RF) power amplifier. One aspect includes an amplification system. The amplification system may include a first amplifier configured to generate an amplifier output voltage, a second amplifier having an output coupled to a supply node for the first amplifier, a voltage regulator having an output coupled to a supply node for the second amplifier, and control circuitry configured to control the voltage regulator to generate a supply voltage at the supply node for the second amplifier based on an indication associated with the amplifier output voltage. In some aspects, the control circuitry may be configured to control the voltage regulator through at least providing an updated control setting for the voltage regulator with a periodicity associated with a power control period.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: Disclosed is an input impedance boosting apparatus. More particularly, an input impedance boosting apparatus including an analog-to-digital converter; an input capacitor connected to an input terminal of the analog-to-digital converter and a ground line and including a first shielding metal formed thereunder; a feedback capacitor connected onto a positive feedback loop of the analog-to-digital converter and including a second shielding metal formed thereunder; and an impedance booster connected to both ends of the feedback capacitor and configured to boost an input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal is provided.

Abstract: Apparatuses and methods of capacitance-to-digital code conversion are described. One capacitance-to-digital converter (CDC) includes front-end circuitry, including a comparator. The CDC further includes a first capacitive digital-to-analog converter (CDAC) coupled to a first input of the comparator and, in a first phase, to a sensor cell. The CDC further includes a second CDAC coupled to a second input of the comparator and, in a second phase, to the sensor cell. The front-end circuitry provides a digital output. The digital output is proportional to a sensor capacitance of the sensor cell.

Abstract: Head-wearable apparatus to generate binaural audio content includes a first stem coupled to a first microphone housing that encases first front microphone and first rear microphone that generates acoustic signals, respectively. First microphone housing includes a first front port that faces downward and a first rear port that faces backwards. Apparatus includes second stem coupled to second microphone housing that encases second front microphone and second rear microphone that generate acoustic signals, respectively. Second microphone housing includes second front port that faces downward and second rear port that faces backwards. Apparatus includes binaural audio processor that includes beamformer and storage device. Beamformer generate first beamformer signal based on acoustic signals from first front microphone and first rear microphone, and second beamformer based on acoustic signals from second front microphone and second rear microphone.

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Abstract: A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Abstract: A multipath D/A converter is provided and has input terminals for a first and a second digital signal, and a signal combination unit D/A converting the digital signals supplied to the input terminals, and combining the generated analog signals. The signal combination unit includes a clock signal with a period having a first half period and a second half period. The signal combination unit combines the analog first and second signals by aggregating them with respective weighting coefficients. The signal combination unit has an output terminal for issuing an analog signal based on the aggregation. The signal combination unit applies a first set of weighting coefficients during the first half period of each period and a second set of weighting coefficients during said second half period of each period. The first set of weighting coefficients differs from the second set of weighting coefficients in at least one coefficient.

Abstract: An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.

Abstract: Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.

Abstract: Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit beamforming capability information including a switching gap that indicates an amount of time associated with the UE switching between an analog beamforming mode and a digital beamforming mode. The UE may receive a resource allocation based at least in part on the beamforming capability information. Numerous other aspects are described.

Abstract: Systems and techniques that facilitate trimmable inductors for qubit frequency tuning are provided. In various embodiments, a device can comprise a Josephson junction. In various aspects, the Josephson junction can be shunted by a capacitor, and a trimmable inductor can couple the Josephson junction to a pad of the capacitor. In various cases, the trimmable inductor can comprise a first conductive path that includes a severable and/or weldable superconducting bridge and a second conductive path that is in parallel with the first conductive path. In various aspects, severing and/or welding the severable and/or weldable superconducting bridge can controllably change an inductance of the trimmable inductor, which can commensurately change a resonant frequency of a qubit formed by the Josephson junction and the capacitor.

Abstract: A method for contact detection for an ultrasonic sensor system installed in a concealed or unconcealed manner is disclosed. The method involves detecting reference surroundings information, comprising a time profile of a signal with: noise signal information relating to a wall material and/or airborne sound signal information, using an ultrasonic sensor of the ultrasonic sensor system; storing the reference surroundings information; detecting real-time surroundings information, comprising a time profile of a signal with: noise signal information relating to the wall material and/or airborne sound signal information and/or object sound signal information relating to an object in contact with the wall material, using the ultrasonic sensor; and forming a difference signal between the surroundings information of reference surroundings information and real-time surroundings information, using a computational unit. The difference signal can be interpreted in a further step.

Abstract: Techniques to deliver a precision low noise reference voltage to a precision analog-to-digital converter without the need of a reference buffer or digital correction. In an example, a technique can use an integrated resistor divider and external capacitor to derive a low noise precision reference voltage either from the power supply of the ADC, or from an integrated reference source.

Abstract: The present invention relates to a method for computational noise compensation for an ultrasonic sensor system (1) that is mounted in a concealed manner, in particular for a vehicle with a wall material (2), including the following steps: detecting reference surroundings information (100) comprising noise signal information (3) relating to a wall material (2) and/or airborne sound signal information (4), using an ultrasonic sensor (5) of the ultrasonic sensor system (1); storing the reference surroundings information (200); detecting real-time surroundings information (300) comprising noise signal information (3) relating to the wall material (2) and/or airborne sound signal information (4), using the ultrasonic sensor (5); and forming a difference signal between the pieces of surroundings information (400) of reference surroundings information and real-time surroundings information, using a computational unit (6).

Abstract: A sensor device includes: first sensors; second sensors which form capacitances with the first sensors; a sensor transmitter connected to the first sensors, where the sensor transmitter supplies driving signals to the first sensors; and a sensor receiver connected to the second sensors, where the sensor receiver receives sensing signals from the second sensors, and the sensor receiver includes a band pass filter which filters the sensing signals. The band pass filter includes: a first integrator including a first amplifier; a first high pass filter converter connected to a first input terminal, a second input terminal and a first output terminal of the first amplifier, where the first high pass filter converter time-divisionally provides N high pass filter conversion paths; and a first gain auxiliary component connected to the first input terminal and the first output terminal of the first amplifier while the first integrator performs an integral function.

Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.

Abstract: A signal sensing and classification system, including: a detection module for obtaining a spectrum of signals; a separation module for extracting a signal from the spectrum of signals; and a multi-task learning (MTL) module for performing a plurality of tasks in parallel on the extracted signal using an MTL neural network model; the plurality of tasks including at least two of: determining a signal class of the extracted signal; determining a modulation class of the extracted signal; and determining at least one signal descriptor of the extracted signal. Additional tasks may include, for example, radio frequency (RF) fingerprinting on the extracted signal to identify an RF device that produced the extracted signal. Other classification and regression tasks may also be performed by the MTL neural network model.

Abstract: A digital decimation filtering circuit of an analog to digital conversion circuit includes an n-tap anti-aliasing filter operable to receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate and filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate. The digital decimation filtering circuit further includes a decimator operable to receive the n-bit filtered signal at the first data output rate, decimate the n-bit filtered signal by a decimation factor to produce a set of output signals, and sum the set of outputs to produce a decimated signal at a second data output rate. The first data output rate is greater than the second data output rate.

Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

Abstract: In an embodiment an electric circuit arrangement includes a current generator circuit having a first output terminal and configured to generate an output current, a controller configured to generate control signals to control the current generator circuit, a random code generator configured to generate random codes and a counter configured to generate a count, wherein the current generator circuit comprises a plurality of output current paths and a plurality of controllable switching circuits, wherein each of the output current paths includes a respective electrical component to define a current in the respective output current path, wherein a respective one of the controllable switching circuits is coupled to a respective one of the output current paths to connect the respective electrical component to the first output terminal, and wherein the random code generator is configured to provide a respective code derived from a respective one of the random codes.

Abstract: Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.

Abstract: A method for updating a user model and fitting agent for a hearing device system is disclosed, the hearing device system comprising a hearing device worn by a hearing device user, wherein the fitting agent comprises one or more processors configured to initialize a user model comprising a plurality of user preference functions and associated user response distributions, wherein each user preference function is associated with an environment; obtain environment data indicative of a present environment; obtain a test setting comprising a primary test setting and a secondary test setting for the hearing device; present the test setting to the hearing device user; obtain a user input of a preferred test setting indicative of a preference for either the primary test setting or the secondary test setting; and update the user model based on hearing device parameters of the preferred test setting and the environment data.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

Abstract: A system and method to convert a wideband optical signal to a multi-bit digital electrical signal using a superconducting integrated circuit. In a preferred embodiment, the optical signal modulates the phase (i.e., adjusts the timing) of a sequence of single-flux-quantum voltage pulses. The optoelectronic modulator may comprise an optically tunable Josephson junction, superconducting inductor, or bolometric detector, with switching speeds approaching 100 ps or less. The optical signal may comprise a plurality of optical signals such as a wavelength-division multiplexed signal. The optical-to-digital converter may be applied to high-speed digital communication switches, broadband digital input/output for superconducting or quantum computing, and control/readout of detector arrays.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A photoelectric conversion device includes a pixel array and a reading unit including a plurality of reading circuits each configured to read a signal from the pixel array. Each reading circuit includes a sample-and-hold unit including a first sample-and-hold circuit configured to hold a reset level output from the pixel array and a second sample-and-hold circuit configured to hold a photo signal level output from the pixel array. The plurality of reading circuits include first reading circuits forming a first group and second reading circuits forming a second group. At least some of the plurality of first reading circuits are controlled by a first control signal given via a first control line, and at least some of the plurality of second reading circuits are controlled by a second control signal given via a second control line.

Abstract: In one embodiment, an analog-to-digital converter includes: a sum circuit to receive an analog input signal and a feedback reference signal and generate a sum signal; a feedback circuit coupled to the sum circuit to provide the feedback reference signal to the sum circuit; a filter coupled to the sum circuit to receive the sum signal and generate a filtered signal; and a punctured quantizer coupled to the filter to receive the filtered signal and quantize the filtered signal to a digital output and to output the digital output and to provide the digital output to the feedback circuit.

Abstract: An electronics (100, 200) including an electrical isolation is provided. The electronics (100, 200) include a bidirectional isolation circuit (110, 210) separating a first portion (100a, 200a) from a second portion (100, 200b) and a bus transceiver switch (120b, 220b) disposed in the second portion (100b, 200b). The bus transceiver switch (120b, 220b) is communicatively coupled to the bidirectional isolation circuit (110, 210). The bus transceiver switch (120b, 220b) receives from the bidirectional isolation circuit (110, 210) a communication control signal provided by the first portion (100a, 200a).

Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0?), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by

Abstract: Systems and methods are provided for analog-to-digital conversion (ADC). A first quantization stage may be configured to receive an analog input signal and sample the analog input signal to generate a first digital signal, the first quantization stage may be further configured to filter the first digital signal with a first noise-shaping transfer function to generate a first noise-shaped digital output and to generate a quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output. A voltage controlled oscillator (VCO)-based second quantization stage may be configured to receive the quantization error signal and sample the quantization error signal to generate a second digital signal, the VCO-based second quantization stage may be further configured to filter the second digital signal with a second noise-shaping transfer function to generate a second noise-shaped digital output.

Abstract: Disclosed herein are an apparatus and method for sensing an image based on an event. The apparatus includes memory in which at least one program is recorded and a processor for executing the program. The program may perform acquiring at least one of brightness information and color information from an input image signal, performing conversion including at least one of filtering of at least one of the acquired brightness information and color information, color conversion, and brightness conversion, calculating a quantized difference between a first converted image converted from the currently input image signal and a second converted image converted from a previously input image signal, and generating event information for the input image signal as a bitstream based on the quantized difference.

Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

Abstract: In an embodiment, an ADC converter includes a first injection branch and a second injection branch, a first feedback branch and a second feedback branch, an integration node connected to the first and second injection branches and the first and second feedback branches, an integrator connected to the integration node and a comparator connected downstream of the integrator and configured to generate a comparator output signal to control the first and second feedback branches, wherein the first and second injection branches are configured to provide a charge injection dependent on a respective input quantity to the integration node, wherein the input quantity of the first injection branch is selected from a differential voltage signal, a capacitance dependent signal and a current dependent signal, wherein the input quantity of the second injection branch is selected from another one of the differential voltage signal, the capacitance dependent signal and the current dependent signal, and wherein the first and s

Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Abstract: Facilitating minimization of non-linearity effects of a delay of a capacitance-to-voltage (C2V) converter on an output of a gyroscope is presented herein. A sense output signal of a sense mass of the gyroscope and a drive output signal of a drive mass of the gyroscope are electronically coupled to respective analog-to-digital converter (ADC) inputs of bandpass sigma-delta ADCs of the gyroscope. The bandpass sigma-delta ADCs include respective C2V converters that are electronically coupled, via respective feedback loops, to the respective ADC inputs to facilitate reductions of respective propagation delays of the bandpass sigma-delta ADCs. Respective ADC outputs of the bandpass sigma-delta ADCs are electronically coupled to demodulator inputs of a demodulator of the gyroscope that transforms the sense output into an output of the MEMS gyroscope representing an external stimulus that has been applied to the sense mass.

Abstract: A method for removing low frequency offset components from a digital data stream includes receiving, at an input of an analog-to-digital converter (ADC), an analog input signal from one or more analog front end components. The analog input signal has an associated low frequency offset due, at least in part, to the analog front end components. The method also includes generating, at an output of the ADC, a digital data stream representative of the analog input signal. The digital data stream having an associated low frequency offset due, at least in part, to the analog front end components and/or the ADC. One or more low pass infinite impulse response (IIR) filters are applied to the digital data stream to detect the low frequency offset components in the digital data stream, and generate a filtered output signal with only the low frequency offset components present.

Abstract: Methods and apparatus to audio watermarking and watermark detection and extracted are described herein. An example method includes receiving a media content signal, sampling the media content signal to generate samples, storing the samples in a buffer, determining a first sequence of samples in the buffer, determining a second sequence of samples in the buffer, wherein the second sequence of samples is of substantially equal length as the first sequence of samples, calculating an average of the first sequence of samples and the second sequence of samples to generate an average sequence of samples, extracting an identifier from the average sequence of samples, and storing the identifier in a tangible memory.

Abstract: Provided in the present disclosure are an electronic device and a method for wireless communication, and a computer-readable storage medium, the electronic device for wireless communication comprising a processing circuit, the processing circuit configured such that: if it is determined that the electronic device is in a frequency spectrum transaction verification region, verifying an effectiveness of a frequency spectrum transaction, the verification region being determined on the basis of interference generated when a frequency spectrum acquirer in the frequency spectrum transaction uses the transaction frequency spectrum; determining an electronic device signal-to-noise ratio according to interference of the electronic device when the frequency spectrum acquirer uses the transaction frequency spectrum, and if the signal-to-noise ratio is greater than a preset signal-to-noise ratio threshold configured for the electronic device, verifying that the frequency spectrum transaction is in effect.

Abstract: A delta-sigma modulator which receives an input signal. The input signal is combined with a feedback signal and the combined signal is filtered by the delta-sigma modulator. The filtered signal is quantized, wherein the feedback signal is generated on the basis of the quantized signal. The quantized signal is output as an output signal. The input signal and/or the filtered signal and/or the feedback signal are filtered in such a way that at least one frequency in an out-of-band frequency range of the input signal is amplified in order to suppress out-of-band quantization noise at the at least one frequency.

Abstract: A fitting agent, e.g. for update of a user model for a hearing device user, and related method is disclosed, wherein the fitting agent is configured to initialize a user model comprising a user preference function and/or a user response distribution; obtain a primary test setting for the hearing device; obtain a secondary test setting for the hearing device; present the primary test setting and the secondary test setting to a user; detect a user input of a preferred test setting indicative of a preference for either the primary test setting or the secondary test setting; and update the user model based on hearing device parameters of the preferred test setting, wherein to update the user model optionally comprises to determine a posterior of parameters of the user preference function, e.g. based on a previous parameter posterior, the preferred test setting, and a non-preferred test setting.

Abstract: A class-D amplifier with multiple “nested” levels of feedback. The class-D amplifier surrounds an inner feedback loop, which takes the output of a switching amplifier and corrects for errors generated across the switching amplifier, with additional feedback loops that also take the output of the switching amplifier.

Abstract: A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path having an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

Abstract: A method for improving frequency response of a high-speed data acquisition device includes sampling signals received at an input of the high-speed data acquisition device at a first sampling rate and generating a digital data stream representative of the sampled input signals. The digital data stream is interpolated to generate an interpolated digital signal with a higher sample rate than the first sampling rate, and one or more finite impulse response (FIR) filters are applied to the interpolated digital signal to generate a filtered digital signal. The filtered digital signal corrects for: parasitic and/or expected response of elements from the network of resistors and capacitors in the anti-aliasing filter in the high-speed data acquisition device, and select anti-aliasing filter response characteristics. The filtered digital signal is decimated to reduce the sampling rate of the filtered digital signal and generate a decimated digital signal.

Abstract: Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.