Differential Encoder And/or Decoder (e.g., Delta Modulation, Differential Pulse Code Modulation) Patents (Class 341/143)
  • Patent number: 10355708
    Abstract: An idle tone dispersion device outputs a frequency delta-sigma modulation signal obtained by using either one of a reference signal and a measured signal to perform frequency delta-sigma modulation of the other and dispersing an idle tone. The idle tone dispersion device includes n (n is any natural number equal to or larger than 2) frequency delta-sigma modulation sections and an adder configured to add up output signals of the n frequency delta-sigma modulation sections and output the frequency delta-sigma modulation signal. Each of the n frequency delta-sigma modulation sections uses either one of the reference signal and the measured signal to perform the frequency delta-sigma modulation of the other. At least one of the reference signal and the measured signal includes jitter including a frequency component higher than a frequency of an idle tone of an output signal of the frequency delta-sigma modulation section.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 16, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Masayoshi Todorokihara
  • Patent number: 10348326
    Abstract: In accordance with an embodiment, a digital microphone interface circuit includes a delta-sigma analog-to-digital converter (ADC) having an input configured to be coupled to a microphone, a digital lowpass filter coupled to an output of the delta-sigma ADC, and a digital sigma-delta modulator coupled to an output of the digital lowpass filter. The delta-sigma ADC, the digital lowpass filter, and the digital sigma-delta modulator are configured to operate at different sampling frequencies.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Elmar Bach, Dietmar Straeussnigg, Luca Valli
  • Patent number: 10348325
    Abstract: A measuring device includes a delta-sigma modulator configured to take an analog signal as a basis for generating a bit stream, and an evaluation unit that receives the bit stream from the delta-sigma modulator and evaluates the received bit stream. The measuring device has a single data transmission line, wherein the delta-sigma modulator is configured to transmit the bit stream to the evaluation unit via the single data transmission line using a transmit clock, and wherein the evaluation unit is configured to reconstruct the transmit clock and/or a phase of bits within the bit stream from the received bit stream and to extract the bits from the received bit stream based on the reconstructed transmit clock and/or based on the reconstructed phase.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: July 9, 2019
    Assignee: Lenze Automation GmbH
    Inventor: Dirk Duesterberg
  • Patent number: 10347233
    Abstract: An adaptive active noise cancellation apparatus performs a filtering operation in a first digital domain and performs adaptation of the filtering operation in a second digital domain.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Hyun Jin Park, Kwokleung Chan, Ren Li
  • Patent number: 10340942
    Abstract: An analog signals generating device comprises a current pump controlled by a control code generated by a module for calculating the digital code with shaping of noise. The calculation module receives as input a digital signal representative of the analog signal to be generated and comprises at least one quantizer and a quantization error compensating stage. The current pump comprises two groups of at least one electric current generator and two groups of at least one switching means, the switching facilities being controlled by the control signal and causing the electric currents to flow between the electric current generators and the inputs of a differential amplifier exhibiting a predominantly capacitive input impedance and connected in series between the two groups of switching means.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 2, 2019
    Assignees: THALES, UNIVERSITE DE BORDEAUX, INSTITUT POLYTECHNIQUE DE BORDEAUX, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Patrick Garrec, Richard Montigny, François Rivet, Yann Deval, Yoan Veyrac
  • Patent number: 10341148
    Abstract: The invention provides a sigma-delta modulator (SDM) and associated system improving spectrum efficiency of wired interconnection. The SDM may comprise a main circuit for transferring an aggregated signal by a signal transfer function, and a noise shaping circuit for shaping noise away from a low-pass band by a modified noise transfer function. A frequency response of the modified noise transfer function may have a notch at a passband, and the passband may not overlap with the low-pass band.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Huan Tsai
  • Patent number: 10333545
    Abstract: Proposed is a sigma-delta modulator circuit. The circuit comprises a loopfilter having at least one integrator or resonator section; and a feed-forward path adapted to provide a feed-forward signal to the output of the at least one integrator or resonator section via a filter.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 25, 2019
    Assignee: NXP B.V.
    Inventor: Lucien Johannes Breems
  • Patent number: 10317482
    Abstract: A resistive sensor includes a current input sigma-delta converter that uses a switched offset voltage source to provide scalable gain and more linear operation. The sigma-delta converter includes an integrator, a quantizer, and a decimator. In one embodiment, the resistive sensor and offset voltage source are coupled to provide an input current at a first node. The integrator has a first input terminal coupled to the first node, and an output terminal. The quantizer has a first input terminal coupled to the output terminal of the integrator, a second input terminal for receiving a clock signal, and an output terminal coupled to provide a feedback signal to control the offset voltage source. The decimator has an input terminal coupled to the output terminal of the quantizer, and an output terminal for providing an output signal. The switched offset voltage source provides scalable gain and good linearity.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventors: Marijn Nicolaas Van Dongen, Edwin Schapendonk, Selcuk Ersoy
  • Patent number: 10317250
    Abstract: Embodiments of an apparatus for direct coupling of a capacitive sensor to a delta-sigma converter are described. One apparatus includes a sensor, a charge coupling circuit configured to transfer at least a portion of charge generated by the sensor to an integrating circuit, a first charge feedback circuit configured to feed back charge to the sensor, a second charge feedback circuit configured to feed back charge to the integrating circuit, a comparing circuit configured to detect accumulated charge at the integrating circuit for a current cycle to determine a polarity of charge feedback for a subsequent cycle, and a logic circuit configured to provide a digital output corresponding to the sensed quantity and also configured to provide the polarity of charge feedback determined by the comparing circuit to the first charge feedback circuit and also to the second charge feedback circuit.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: June 11, 2019
    Assignee: ION Geophysical Corporation
    Inventors: William Terry McDavid, Lawrence Philip Behn
  • Patent number: 10312926
    Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventor: Roberto Sergio Matteo Maurino
  • Patent number: 10312892
    Abstract: A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10313162
    Abstract: The embodiments described herein provide communication devices and methods that can facilitate communication between galvanically isolated systems. Specifically, the embodiments facilitate communication to a galvanically isolated system that is shut down without requiring that this shutdown system consume its own power while it is shutdown. To facilitate this, the communication devices and methods provide a wake-up device on the side of the shutdown system and facilitate the transfer of power across the galvanic isolation to the wake-up device when communication to the shutdown system is needed. With the wake-up device powered using power that was transferred across the galvanic isolation, the wake-up device can perform the actions needed to wake up the shutdown system, and can thus facilitate communication between the galvanically isolated systems. Thus, communication between galvanically isolated systems is facilitated without requiring that the shutdown system consume its own power during shutdown periods.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 4, 2019
    Assignee: NXP B.V.
    Inventors: Stefan Paul Van Den Hoek, Lucas Pieter Lodewijk Van Dijk, Cecilius Gerardus Kwakernaat
  • Patent number: 10305506
    Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Ketan Dewan, Reinhard Kussian, Juergen Schaefer
  • Patent number: 10303746
    Abstract: A sentence communicating a desired vanity message is parsed into the component parts. Code blocks corresponding to one or more component parts of the sentence are unambiguously coded. At least one of the code blocks is non-phonetically and unambiguously coded. And at least one of the code blocks representing a component part of a sentence has, as a part of the code block, a code distinguishing feature for the code block representing the component part of the sentence. The code blocks follow each other to form a coded message. The first and one or more other code blocks have no fewer than the predetermined minimum number of characters and no more than the predetermined maximum number of characters.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 28, 2019
    Assignee: CRLK, Inc.
    Inventor: M. Peri Periasamy
  • Patent number: 10303125
    Abstract: A time-to-digital converter includes first and second oscillation circuits, first and second sampling circuits, and a processing circuit. The first and second oscillation circuits start an oscillation operation in accordance with first and second signals and output first and second clock signals, respectively. The first and second sampling circuits perform sampling of the first and second clock signals by a first reference clock signal and output first and second output signals, respectively. The processing circuit obtains first frequency information and first phase information of the first clock signal and second frequency information and second phase information of the second clock signal based on the first and second output signals of the first and second sampling circuits, and obtains a digital value corresponding to a time difference of a transition timing between the first and second signals.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 28, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Hideo Haneda
  • Patent number: 10305507
    Abstract: A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jerry Lee Doorenbos, Keith Eric Sanborn, Mina Raymond Naguib Nashed, Srikanth Vellore Avadhanam Ramamurthy, Dwight David Griffin
  • Patent number: 10298256
    Abstract: An analog-to-digital conversion system includes two quantizers having a least significant bit arranged in a parallel pair. An input circuit coupled to the quantizers provides an analog input signal to the quantizers. A dither generator coupled to the quantizers provides an analog differential dither signal for perturbing quantization of the analog input signal. A combiner coupled to the quantizers adds respective outputs of the quantizers to obtain a linearized digital representation of the analog input signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Raytheon Company
    Inventors: Ian S. Robinson, James Toplicar, John G. Heston
  • Patent number: 10298245
    Abstract: An analog-to-digital conversion (ADC) system includes a transconductance amplifier, loop filter, quantizer, logic circuit, and digital-to-analog converter (DAC). The transconductance amplifier is configured to generate a current signal in response to an audio signal. The loop filter is connected to the transconductance amplifier and configured to generate a filtered signal based on the current signal. The quantizer is configured to generate a digital representation of the filtered signal. The logic circuit is configured to generate control signals based on the digital representation. The DAC is coupled to the loop filter's and the transconductance amplifier's output. The DAC includes three-level unit elements, where each unit element is configured to provide one of two signal levels or no signal to the loop filter in response to control signals from the logic circuit. Such an ADC system may allow for a high dynamic range while maintaining low power consumption and low noise.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 21, 2019
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Claudio De Berti, Lorenzo Crespi
  • Patent number: 10291239
    Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 14, 2019
    Assignee: XILINX, INC.
    Inventors: Zhaoyin D. Wu, Winson Lin, Parag Upadhyaya, Geoffrey Zhang, Kun-Yung Chang
  • Patent number: 10284223
    Abstract: The invention describes a method of performing analog-to-digital conversion on an input signal (Pin) within a range (R1) using a sigma-delta modulator (1) comprising a feedback digital-to-analog conversion arrangement (12, 120), which method comprises the steps of: obtaining an amplitude estimate (E1, E2, E3, E4) of the input signal (Pin); defining a subsequent subrange (R2, R3, R4) on the basis of the amplitude estimate (E1, E2, E3); and adjusting operation parameters of the feedback digital-to-analog conversion arrangement (12, 120) on the basis of the subsequent subrange (R2, R3, R4); whereby the method steps are repeated a predefined number of iterations (N). The invention further describes a sigma-delta modulator (1), an analog-to-digital converter (50), and a monitoring device (5) for monitoring an analog input signal (Pin).
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 7, 2019
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Sotir Filipov Ouzounov, Ketan Pol
  • Patent number: 10284213
    Abstract: Some or all of a comparator circuit of an analog-to-digital converter (ADC) circuit can be efficiently repurposed or reused for residue amplification for efficient noise-shaping, e.g., in a noise-shaping feedback configuration. A preamplifier portion of a comparator circuit in an oversampling ADC can be re-purposed to provide an amplifier to amplify or otherwise modify a residue left after the bit trials of a conversion cycle. The amplified or modified residue can then be used elsewhere, for example, for noise-shaping by applying a noise transfer function (NTF), a result of which can then be fed back (e.g., summed with the next sampled input at an input of the comparator circuit for use in the N bit trials of the next ADC cycle).
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 7, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Rong Jin
  • Patent number: 10284400
    Abstract: This ?? modulator is a ?? modulator using multiple integrators. The integrator: includes a plurality of stages of adder sequences, each of the adder sequences including a plurality of adders connected in series; performs feedback of a result of a second adder sequence as an input to a first adder sequence, the first adder sequence being a first stage of the plurality of stages, and the second adder sequence being a last stage of the plurality of stages; and processes inputs supplied to the plurality of adders of the first adder sequence and supplies it to the second adder sequence.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 7, 2019
    Assignee: NEC CORPORATION
    Inventors: Masaaki Tanio, Tomoyuki Yamase, Shinichi Hori
  • Patent number: 10284222
    Abstract: An analog-to-digital converter (ADC) device includes a delta-sigma modulator having at least one integrator and a quantizer configured to receive an output of the at least one integrator. The delta-sigma modulator also includes digital-to-analog converter (DAC) capacitor bank, a sampling capacitor bank, and a pre-charge capacitor bank, each selectively coupled to an input node of the at least one integrator. The delta-sigma modulator also includes a pre-charge signal generator coupled to the pre-charge capacitor bank. The pre-charge signal generator is configured to generate a pre-charge signal to charge the pre-charge capacitor bank based at least in part on an output code of the quantizer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amit Kumar Gupta, Peng Cao
  • Patent number: 10285227
    Abstract: Described herein is an apparatus including, a decoder that is configured to decode a digital control code. The digital control code corresponds to an intensity level control code of a plurality of LEDs. The apparatus includes a modulator that modulates a combination of the decoded control code and a dither signal, wherein the combined signal has a first modulation format. The apparatus also includes a converter that generates a dimming control signal by converting the first modulation format associated with the combined signal to a programmable second modulation format.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 7, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Hui Pan, Jingguang Wang, Martin Weetman
  • Patent number: 10273894
    Abstract: A variety of methods and arrangements for improving the fuel efficiency of internal combustion engines based on skip fire operation of the engine are described. In one aspect the skip fire decisions are made on a working cycle by working cycle basis. During selected skipped working cycles, the corresponding cylinders are deactivated such that air is not pumped through the cylinder during the selected skipped working cycles. In some implementations, the cylinders are deactivated by holding associated intake and exhaust valves closed such that an air charge is not present in the working chamber during the selected skipped working cycles.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 30, 2019
    Assignee: Tula Technology, Inc.
    Inventor: Adya S. Tripathi
  • Patent number: 10277238
    Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 30, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Krishnaswamy Nagaraj
  • Patent number: 10277241
    Abstract: A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 30, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Omid Rajaee, Elias Dagher, Yan Wang, Dinesh Jagannath Alladi
  • Patent number: 10263634
    Abstract: AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 16, 2019
    Assignee: KAGOSHIMA UNIVERSITY
    Inventor: Kenichi Ohhata
  • Patent number: 10250272
    Abstract: A digital-to-analog converter (DAC) may have an encoder that generates a multi-bit output based on a multi-bit input, a plurality of first converter elements, with each first converter element generating an output according to a single bit of the multi-bit output of the encoder; and a combiner that generates a combined output based on combining outputs from the plurality of first converter elements. The number of bits in the multi-bit input being two or more and the number of bits in the multi-bit output being greater than the number of bits in the multi-bit input. The DAC may also have one or more second converter elements, with second converter element generating an output according to a single bit, and the combiner may generates the combined output based on combining outputs from the plurality of first converter elements with outputs from the one or more second converter elements.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 2, 2019
    Assignee: MAXLINEAR, INC.
    Inventor: Jianyu Zhu
  • Patent number: 10242745
    Abstract: A semiconductor memory device includes a memory cell array, a temperature sensor that generates a first voltage which is based on a temperature of the semiconductor memory device, compares the first voltage with a second voltage that is based on a result of previous temperature measurement, and generates a voltage generation signal based on a result of comparing the first voltage with the second voltage, and a voltage generating circuit that generates a voltage applied to the memory cell array based on the voltage generation signal.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Hosoya
  • Patent number: 10235308
    Abstract: A write-enable circuit outputting a write-enable signal for digital data, in an analog-to-digital converter comprising a bus-controller connected to an external unit, an arithmetic processing unit performing data processing, and an arithmetic unit holding the data and having a normal access mode in which the data are temporarily written into the arithmetic processing unit and then written into the bus-controller and a high-speed access mode in which the data are written directly into the bus-controller. The circuit comprises an address-coincidence-determining circuit provided in the arithmetic unit outputting a write-enable signal from the arithmetic unit when a predetermined address for a memory of the bus-controller coincides with an address specified by the arithmetic processing unit; and a logic circuit inputting the write-enable signal to the bus-controller when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 19, 2019
    Assignee: Mistubishi Electric Corporation
    Inventors: Masaru Hoshikawa, Masataka Watahiki, Yuta Takenaka
  • Patent number: 10235000
    Abstract: A sensing system includes: a transmitter circuitry configured to transmit drive signals to N sensors, N being a positive integer; N receiver circuitries configured to receive in parallel N sense signals generated in response to the drive signals by N sensors, N being a positive integer; N modulation circuitries configured to modulate outputs of the N receiver circuitries; a mixer circuitry configured to mix outputs of the N modulation circuitries; an A/D converter circuitry configured to receive an output of the mixer circuitry; and a demodulation circuitry. The demodulation circuitry is configured to demodulate an output of the A/D converter circuitry to generate N digital sense values corresponding to the N sense signals.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 19, 2019
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Nobukazu Tanaka, Takayuki Noto, Tetsuo Tanemura
  • Patent number: 10224952
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 5, 2019
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Patent number: 10209138
    Abstract: A distributed sensing device for determining a physical quantity which includes a measuring unit configured for measuring signals over time and space by distributed sensing, a determining unit configured for determining, based on the measured signals, data being correlated to the physical quantity, and a filtering unit configured for filtering the data to reduce noise and substantially preserve real features based on at least one filter parameter which is determined depending on the data which relate to the physical quantity at a plurality of different times.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: February 19, 2019
    Assignee: AiQ Dienstleistungen UG (haftungsbeschränkt)
    Inventors: Gregor Cedilnik, Aldemar Dünkel, Alf Clement
  • Patent number: 10193533
    Abstract: Continuous-time digital systems implemented with separate timing paths and data paths are disclosed. The disclosed continuous-time digital systems, can implement an event-grouping and detection method that can be used feedback systems with propagation delays. By implementing event-detection into a feedback loop of a continuous-time digital system, the system can automatically stop when there is no event in the system. When new events are detected the system can commence operation.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 29, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Yu Chen, Yannis Tsividis
  • Patent number: 10185166
    Abstract: A digital to analog converter includes N lines of transistors. A number of each rear line of transistors is equal to a half of a number of each adjacent front line of transistors. Each transistor includes a conducting terminal, an input terminal, and an output terminal. In any two adjacent lines of transistors, input terminals of the first transistors and input terminals of the second transistors of the rear line are connected to output terminals of the first transistors of a front line respectively. Output terminals of the second transistors of the front line are connected to output terminals of the first transistors of the front line. Output terminals of the second transistors of the rear line of transistors are connected to output terminals of the first transistor of the rear line of transistors. Conducting terminals of each line of transistors are connected to each other.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 22, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jiang Zhu
  • Patent number: 10181862
    Abstract: A delta-sigma modulator (DSM) includes: a first summation circuit coupled to an input signal for subtracting an error feedback signal from the input signal; a tunable signal transfer function coupled to the first summation circuit for setting a desired pole in a frequency response of the DSM; a second summation circuit coupled to the tunable signal transfer function for adding a noise transfer function to an output of the tunable signal transfer function; and a quantizer coupled to the second summation circuit for quantizing an output of the second summation circuit to generate an output of the DSM. The output of the DSM is used as feedback to the first summation circuit as the error feedback signal, and the tunable signal transfer function is dynamically tuned to allow selecting and tuning a center frequency and a bandwidth of the DSM.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 15, 2019
    Assignee: RAYTHEON COMPANY
    Inventors: Harry B. Marr, Daniel Thompson, Mark B. Yeary
  • Patent number: 10169704
    Abstract: This disclosure is directed to artificially intelligent (AI) communication generation by traversing routes of a graph in a complex computing network. The intelligent communication generation is used for determining whether an input signal has certain desired signal attributes.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 1, 2019
    Assignee: Research New Group, Inc.
    Inventors: Michael D. Bigby, Leonard A. Bucchino, III, Charles A. Hunt, Khusro Khalid, Rabik Maharjan, Gregory B. Molik, Michael C. Munsie, Timothy W. Proffitt, Bradley D. White
  • Patent number: 10162467
    Abstract: An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance sensing circuit also includes a comparator configured to generate an output based on comparing a first voltage of the first modulation capacitor with a second voltage of the second modulation capacitor, and initiate a transition between the first phase and the second phase in response to the comparing.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 25, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventor: Andriy Maharyta
  • Patent number: 10157034
    Abstract: Clock rate adjustment methods and systems, including receiving, by a playback device from a source device, a plurality of frames, including a first frame and a second frame, each frame being associated with audio information and a time indicating when to play the audio information wherein the time is based on the clock of the source device; determining, by the playback device an expected time value for a third frame; comparing, by the playback device, the expected time value to the time indicating when to play the audio information associated with the third frame; and when the difference between the expected time value and the time indicating when to play the audio information is above a threshold level, adjusting, by the playback device, a rate of a digital to analog converter clock associated with the playback device.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: December 18, 2018
    Assignee: Sonos, Inc.
    Inventor: Nicholas A. J. Millington
  • Patent number: 10154211
    Abstract: A pixel circuit comprises a first capacitor, a photo diode and a switch. A voltage source generates a reference voltage to reset the pixel circuit. The pixel circuit is reset for a first reset time period by electrically coupling a cathode of the photo diode and a first capacitor terminal to the voltage source. The cathode is decoupled from the voltage source and the photo diode is exposed to light for an accumulation time period. After the accumulation time period, a first reference voltage is sampled. The cathode is then coupled, via the switch, to the first capacitor terminal for a selected transfer time period, during which a second signal voltage is sampled. After the selected transfer time period, a first signal voltage is sampled with the cathode decoupled. The pixel circuit is then reset for a second reset time period, after which a second reference voltage value is sampled.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: December 11, 2018
    Assignee: TELEDYNE DALSA B.V.
    Inventor: Willem Hendrik Maes
  • Patent number: 10153778
    Abstract: A sigma-delta converter including a sigma-delta modulator including at least one analog filter capable, for each cycle of a conversion phase, of receiving an internal analog signal originating from the analog input signal and of supplying an analog output signal, wherein: the contribution of the internal analog signal to the output value of the filter is smaller at a given cycle of the conversion phase than at a previous cycle, the contributions to the different cycles being governed by a first predetermined law which is a function of the rank of the cycle; and the duration of a given cycle of the conversion phase is shorter than the duration of a previous cycle, the durations of the different cycles being governed by a second predetermined law which is a function of the rank of the cycle in the conversion phase.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 11, 2018
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Arnaud Verdant, William Guicquero
  • Patent number: 10148283
    Abstract: A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 4, 2018
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Bai Sun Kong, Moo Yeol Choi
  • Patent number: 10148278
    Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: December 4, 2018
    Assignee: Intel IP Corporation
    Inventors: Marco Bresciani, John G. Kauffman, Udo Schuetz, Patrick Torta, Francesco Conzatti
  • Patent number: 10142052
    Abstract: Methods and apparatus embodiments to communicate data via a digital isolator by receiving an input data stream having first and second states, generating a first pulse train for the first state and a second pulse train for the second state. The first and second pulse types are transmitted across a voltage barrier of a digital signal isolator and received by a receive channel. The first and second pulse trains are processed to recover the input data stream in an output data stream. Data/System integrity functionality can identify fault conditions from an alteration of transmitted pulses.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: November 27, 2018
    Assignee: Allegro MicroSystems, LLC
    Inventors: Alejandro Gabriel Milesi, Guillermo Stuarts, Juan Guido Salaya
  • Patent number: 10139480
    Abstract: A transducer for an ultrasound imaging system includes an array of transducer elements and an analog-to-digital converter configured to convert analog signals produced by the transducer elements into corresponding digital samples that are encoded with a first number of bits. One or more memories are used to store digital samples associated with frames of ultrasound data. A processor or logic circuit in the transducer is configured to compress the digital ultrasound data by calculating differences between the samples and encoding the differences with a second number of bits that is less than the first number of bits. In addition, the logic circuit is configured to transmit a packet that includes the differences encoded with the second number of bits and an overflow portion that encodes the differences that are too large to be encoded with the second number of bits.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 27, 2018
    Assignee: FUJIFILM SonoSite, Inc.
    Inventor: Kai Wen Liu
  • Patent number: 10141948
    Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 27, 2018
    Assignee: MediaTek Inc.
    Inventors: Chan-Hsiang Weng, Tien-Yu Lo
  • Patent number: 10135459
    Abstract: A low power high precision mixed signal analog to digital converter is provided for processing biometric signals in the presence of a large interferer signal for cableless patient monitoring; a capacitive difference circuit produces an analog difference signal by differencing an analog feedback loop signal and an input signal; an analog-to-digital converter sigma delta converter produces a digital version of the difference signal, a digital feedback loop includes a digital integrator and a capacitive digital-to-analog converter configured to produce the analog loop feedback signal based upon the digital version of the difference.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 20, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Yogesh Jayaraman Sharma, Arthur J. Kalb
  • Patent number: 10136488
    Abstract: Techniques are provided for low, or deep, dimming of a light-emitting diode (LED) load. In an example, a method of adjusting an initial voltage of a driver circuit for an LED load can include providing current to an LED load from a power stage of the driver during an on-time of a pulse-width modulation (PWM) cycle, receiving error current information of the driver circuit at a low-dimming control circuit of the driver, and adjusting a voltage of an output capacitor coupled to the driver during an off-time of the PWM cycle, the charge adjustment based on the error current information.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Linear Technology Holding, LLC
    Inventors: Dongwon Kwon, Joshua William Caldwell
  • Patent number: 10128859
    Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 13, 2018
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Sanjay Rajasekhar, Roberto Sergio Matteo Maurino