Differential Encoder And/or Decoder (e.g., Delta Modulation, Differential Pulse Code Modulation) Patents (Class 341/143)
  • Patent number: 10735005
    Abstract: A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 4, 2020
    Assignee: The Regents of the University of California
    Inventors: Ian Galton, Enrique Alvarez-Fontecilla
  • Patent number: 10734971
    Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Carl W. Werner
  • Patent number: 10727860
    Abstract: A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 28, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Wai-Shun Shum, Lei Zhu, Johann G. Gaboriau, Xiaofan Fei, Xin Zhao
  • Patent number: 10727876
    Abstract: A multi-channel, multi-band system for wireless communication includes a radio frequency (RF) front end, a mixed-signal front end for converting an incoming analog RF signal into an incoming digital RF signal and converting a composite outgoing digital RF signal into an outgoing analog RF signal, a summation circuit for combining multiple outgoing digital RF signals to the composite outgoing digital RF signal, and multi-band transceivers. Each of the multi-band transceivers may process the incoming digital RF signal to provide an incoming baseband signal and process an outgoing baseband signal to provide an outgoing digital RF signal. The mixed-signal front end may apply a loading control to each transceiver for adjusting an amount of loading on the transmit path from the transceiver to the mixed-signal front-end. The transceivers may individually conduct a feedback calibration on the receive path to optimize the incoming baseband signal for each band.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: July 28, 2020
    Assignee: Jariet Technologies, Inc.
    Inventors: Craig A. Hornbuckle, Leo Ghazikhanian
  • Patent number: 10727859
    Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Meghna Agrawal
  • Patent number: 10720904
    Abstract: A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: July 21, 2020
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Vinoth Kumar, Bhanu Pande, Carroll C. Speir, Satishchandra G. Rao, Sajkapoor P. K.
  • Patent number: 10718801
    Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Amar Vellanki, Zhong You, Johann G. Gaboriau
  • Patent number: 10707893
    Abstract: A second-order ?? modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 7, 2020
    Assignee: NEC CORPORATION
    Inventor: Masaaki Tanio
  • Patent number: 10707894
    Abstract: A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tetsuo Matsui, Mitsuya Fukazawa, Tomohiko Yano
  • Patent number: 10707890
    Abstract: A circuit is for sampling an analog input signal that receives and samples an analog input signal. Sampling circuitry is clocked at a sampling frequency and samples the analog input signal at a rate corresponding to the sampling frequency. The sampling circuitry includes at least one pulse density modulator that includes a comparator configured to be clocked at the sampling frequency, to provide bandpass sampling of the analog input signal at the sampling frequency, and to produce a corresponding pulsed output that is pulse density modulated based on the analog input signal.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: July 7, 2020
    Assignee: CAMBRIDGE CONSULTANTS LIMITED
    Inventors: Desmond Phillips, Bryan James Donoghue
  • Patent number: 10693482
    Abstract: A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Aaron J. Caffee
  • Patent number: 10693490
    Abstract: A Sigma-Delta (?-?) analog-to-digital converter (ADC) and operation method thereof are provided. The ?-? ADC includes a ?-? modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the ?-? modulator is configured to receive an analog signal. The ?-? modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the ?-? modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the ?-? modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 23, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Chiao-Min Chen, Min-Yuan Wu, Shih-Yi Shih, Po-Liang Chen
  • Patent number: 10690719
    Abstract: A system for testing an application-specific integrated circuit, includes a characterization integrated circuit comprising at least two configurable test structures and a test assembly comprising: a device for controlling the characterization integrated circuit, configured to vary at least one physical parameter of at least one configurable test structure, an interface for receiving at least one description of an application-specific integrated circuit and extracting at least one path, a configuration device for activating and interconnecting at least one subset of the logic cells of at least one degraded test structure and of at least one non-degraded test structure, so that they each produce a topology identical to a portion of an extracted path, a measurement control device for performing at least one first measurement of a physical variable on the degraded test structure and at least one second measurement, identical to the first measurement, on the non-degraded test structure.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 23, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Heron, Boukary Ouattara
  • Patent number: 10686326
    Abstract: A wireless power receiver for wirelessly receiving power from a wireless power transmitter comprises: a power reception circuit receiving electromagnetic waves emitted from the wireless power receiver so as to output power having an alternating current waveform; a rectifier for rectifying the power, having an AC waveform, outputted from the power reception circuit into power having a direct current waveform; a DC/DC converter for converting, into a voltage of a preset level, a voltage of the power having a direct current waveform, the power being rectified by the rectifier; a charger for charging a battery by using the power having a DC waveform, converted from the DC/DC converter; an alternating current ground connected to the power reception circuit and/or the rectifier so as to receive at least a portion of the power having an alternating current waveform; and a direct current ground connected to the DC/DC converter and/or the charger so as to receive at least a portion of the power having a direct current
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Chong-Min Lee, Yu-Su Kim, Hyung-Koo Chung, Hyo-Seok Han
  • Patent number: 10680637
    Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 9, 2020
    Assignee: Apple Inc.
    Inventors: John G. Kauffman, Krzysztof Dufrene
  • Patent number: 10680617
    Abstract: Techniques regarding a DSFQ logic family are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a dynamic single flux quantum logic circuit that has a self-resetting internal state and can be powered by direct current. Further, the self-resetting internal state can be characterized by two time constants.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Sergey Rylov
  • Patent number: 10680638
    Abstract: Described herein is a method and apparatus for reducing ISI in a single-bit ?? modulator without reducing the dynamic range of the modulator. In one embodiment, the signal fed back to the input of the modulator is not the single-bit outputs of a quantizer as in the prior art, but rather patterns of such outputs. The patterns are selected so that each pattern has the same number of transition edges and there is thus no mismatch of transition times. In one embodiment, the patterns are created by digital logic. In another embodiment, an analog signal is added to the error signal in the feedback loop which causes the quantizer to generate the patterns. When the amplitude of the input signal exceeds a certain level, the modulator reverts to the typical operation of a prior art modulator, thus preserving the full dynamic range of the modulator.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 9, 2020
    Assignee: SiliconIntervention Inc.
    Inventor: A. Martin Mallinson
  • Patent number: 10673606
    Abstract: A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 2, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10666276
    Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Krishnaswamy Nagaraj
  • Patent number: 10666285
    Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 26, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shahin Mehdizad Taleie, Behnam Sedighi, Dongwon Seo, Parisa Mahmoudidaryan, Bhushan Shanti Asuri, Sang-June Park, Shrenik Patel
  • Patent number: 10666286
    Abstract: A partitioned delta-sigma modulator for high-speed applications includes a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series. In some aspects, each of the plurality of modulation stages is configured to combine a first error signal from a prior modulation stage of the plurality of modulation stages with a first digital signal to produce an adder signal. In some aspects, the first error signal includes a delay from the prior modulation stage. Each of the plurality of modulation stages is also configured to convert the adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width. Each of the modulation stages is also configured to provide a second error signal based on the quantized signal to a subsequent modulation stage of the plurality of modulation stages.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 26, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Federico Santiago Cattivelli, Gozde Sahinoglu
  • Patent number: 10665222
    Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Suyoung Bang, Muhammad Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Wootaek Lim, Tobias Bocklet, David Pearce
  • Patent number: 10659074
    Abstract: To effectively suppress an idle tone in a delta-sigma modulator that generates a feedback signal by a digital-to-analog converter. A filter integrates a difference between an input analog signal and a feedback signal, and outputs the integrated difference as an integrated signal. A preceding-stage quantizer quantizes an integrated signal into a digital signal, and outputs the resulting digital signal as a preceding-stage output signal. An adder adds a predetermined dithering signal to a preceding-stage output signal, and outputs the resulting signal as a subsequent-stage input signal. A subsequent-stage quantizer configured to quantize the subsequent-stage input signal into a digital signal of a shorter number of bits than a preceding-stage output signal, and outputs the resulting digital signal as a subsequent-stage output signal.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 19, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Eiichi Nakamoto
  • Patent number: 10650682
    Abstract: The invention relates to a communication system for a vehicle, which device includes a sensor device, wherein the sensor device is arranged to capture sensor data when the sensor device moves. A receiving device receives reference data from an external management system and a processing device determines a difference between the captured sensor data and the corresponding reference data, wherein the determined difference between the captured sensor and the corresponding reference data is transmitted to the external management system.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: May 12, 2020
    Assignee: Continental Automotive GmbH
    Inventor: Ralph Grewe
  • Patent number: 10644807
    Abstract: The present disclosure includes a photodetector element (11) that converts an optical signal into an electric current signal; a transimpedance amplifier (12a) that converts the electric current signal into a voltage signal; a differential amplifier (12d) that converts the voltage signal into a differential signal, by performing differential amplification of a difference between the voltage signal and a threshold voltage; an LOS detection circuit that detects a no-signal section of the optical signal; and an MCU that repeatedly executes offset cancellation processing, the offset cancellation processing including threshold voltage change processing in which the threshold voltage is changed such that an offset voltage of the differential signal is reduced, the MCU 13 skipping the threshold voltage change processing in the no-signal section.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: May 5, 2020
    Assignee: FUJIKURA LTD.
    Inventors: Takayuki Tanaka, Minako Hayashi
  • Patent number: 10644695
    Abstract: A source driver is proposed. The source driver includes N output buffers, (N?1) switches, a first auxiliary switch, a second auxiliary switch, and a third auxiliary switch. The (N?1) switches are respectively coupled between N output terminals of the N output buffers. The first auxiliary switch is coupled between a first output terminal among the N output terminals of the N output buffers and a first endpoint. The second auxiliary switch is coupled between the first output terminal and a second endpoint. The third auxiliary switch is coupled between the first output terminal and a third endpoint. Each of the first endpoint, the second endpoint, and the third endpoint receives a first fixed voltage, a second fixed voltage, a third fixed voltage, or is in a floating state.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 5, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Han-Kun Wu, Pang-Chen Hung
  • Patent number: 10644718
    Abstract: An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 5, 2020
    Assignee: University of Macau
    Inventors: Biao Wang, Sai-Weng Sin, Franco Maloberti, Rui Paulo da Silva Martins
  • Patent number: 10630311
    Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Lung Chen, Jie-Fan Lai, Yu-Chang Chen, Shih-Hsiung Huang
  • Patent number: 10623014
    Abstract: Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 14, 2020
    Assignee: Syntropy Systems, LLC
    Inventor: Christopher Pagnanelli
  • Patent number: 10623008
    Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Parag Upadhyaya, Adebabay M. Bekele, Didem Z. Turker Melek, Zhaoyin D. Wu
  • Patent number: 10615815
    Abstract: An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: April 7, 2020
    Assignee: MAXLINEAR, INC.
    Inventors: Rishi Mathur, Chandrajit Debnath, Abhishek Ghosh, Anand Mohan Pappu
  • Patent number: 10615821
    Abstract: A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n?1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: April 7, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Vincent Quipuempoix, Eve Carletti
  • Patent number: 10601439
    Abstract: Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 24, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Pernull, Massimo Rigo, Herwig Wappis
  • Patent number: 10587278
    Abstract: An analog or digital to encoder signal converter is provided that includes a current sense circuit, if an analog input, configured to receive an analog signal from a sensor and convert the signal into a digital signal via an analog-to-digital converter. The digital signal is processed to generate an appropriate reading value and an encoder string is made that represents the desired value for data transmission, wherein the string is formatted for a selected, specific encoder reader protocol. In this way, existing data collection systems that require a specific encoder protocol for data transmissions can be expanded to collect data from any sensing device with an analog or digital output, thereby adding value to existing encoder data collection systems by enabling them to collect data from devices other than just the customer billing meters for which the encoder protocol networks were designed.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: March 10, 2020
    Assignee: F.S. Brainard & Company
    Inventor: Bradford Brainard
  • Patent number: 10585644
    Abstract: An integrated quantum random noise source includes a substrate, an optical oscillator that may be integral to the substrate coupled by an optical waveguide to an optical directional coupler. The optical directional coupler has two outputs that are coupled by optical waveguides to a pair of photodetectors that are part of a balanced photodetector. The balanced photodetector in response outputs an analogue signal proportional to the difference in photocurrents of the two photodetectors. The analogue output signal from the balanced photodetector is a random Gaussian-distributed signal representative of quadrature measurements on the quantum vacuum state of light. The random noise source can be coupled other apparatus to provide a source of random bits.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 10, 2020
    Assignee: QuintessenceLabs Pty Ltd.
    Inventors: Ken Li Chong, Andrew Lance
  • Patent number: 10581451
    Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jagannathan Venkataraman, Prabu Sankar Thirugnanam, Raja Reddy Patukuri, Sandeep Kesrimal Oswal
  • Patent number: 10581453
    Abstract: A current sensing system and delta sigma modulator architecture are discloses for sensing and digitizing a current input signal from a high impedance signal source with improve power efficiency. The delta sigma modulator integrates a signal condition stage within the delta sigma modulator feedback loop by utilizing a capacitive summation stage. For given gain, resolution, and bandwidth requirements, the delta sigma modulator architecture achieves reduced power consumption by advantageously reducing the number of nodes in the system that require a high dynamic range. Additionally, the delta sigma modulator has very high input impedance such that the input of the delta-sigma modulator can be connected directly to a high impedance signal source, without the need for a front-end pre-amplifier stage, or the like.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 3, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Saikrishna Ganta, Man-Chia Chen, Chinwuba Ezekwe
  • Patent number: 10574247
    Abstract: The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 25, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Junbiao Ding, Tony Yincai Liu, Dennis A. Dempsey, John Jude O'Donnell
  • Patent number: 10574258
    Abstract: A method includes applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin to a digital stream using a Sigma-Delta modulator; converting the digital stream to a first digital output signal proportional to the analog signal in a first input range between a first analog signal value and a second analog signal value, where the first input range corresponds to a pre-determined range of the analog signal smaller than a full-scale input range of the analog signal; converting the digital stream to a second output signal; comparing the second output signal to a first threshold corresponding to a third analog signal value at the input pin that is outside of the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 25, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Siegfried Albel, Matthias Bogus, Christian Heiling, Jaafar Mejri, Markus Zannoth
  • Patent number: 10573329
    Abstract: Methods and systems for high frequency injection and detection for improved false acceptance reduction are disclosed. An information handling system may be configured to receive audio data and to add an identification signal to the audio data, wherein the identification signal is determined based on the audio data. The combined audio data and the identification signal may be output to a receiving device. An information handling system may also be configured to receive data that includes audio data and an identification signal that is associated with one or more frequencies in the audio data, identify the one or more frequencies in the audio data that are associated with the identification signal, and attenuate the one or more frequencies in the audio data to obtain modified audio data. The modified audio data may be output for audio processing.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 25, 2020
    Assignee: Dell Products L.P.
    Inventors: Steven Thomas Embleton, Eric Michael Tunks
  • Patent number: 10566991
    Abstract: A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peng Cao, Amit Kumar Gupta
  • Patent number: 10566994
    Abstract: A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 18, 2020
    Assignee: Cable Television Laboratories, Inc.
    Inventors: Belal Hamzeh, Zhensheng Jia, Luis Alberto Campos, Curtis Dean Knittle, Jing Wang
  • Patent number: 10565506
    Abstract: This disclosure is directed to communication generation by traversing routes of a graph in a complex computing network. The communication generation is used for determining whether an input signal has certain desired signal attributes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 18, 2020
    Assignee: Research Now Group, LLC
    Inventors: Michael D. Bigby, Leonard A. Bucchino, III, Charles A. Hunt, Khusro Khalid, Rabik Maharjan, Gregory B. Molik, Michael C. Munsie, Timothy W. Proffitt, Bradley D. White
  • Patent number: 10566986
    Abstract: The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: February 18, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ya-Nan Wen, Yingsi Liang
  • Patent number: 10560114
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 11, 2020
    Assignee: Avnera Corporation
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Patent number: 10554215
    Abstract: An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency, where the analog signal includes a set of pure tone components. The analog to digital conversion circuit further includes a digital decimation filtering circuit operable to convert the first digital signal into a second digital signal having a second data rate frequency. The analog to digital conversion circuit further includes a digital bandpass filter (BPF) circuit operable to convert the second digital signal into an outbound digital signal having a third data rate frequency, where the digital bandpass filter circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 4, 2020
    Assignee: SIGMASENSE, LLC.
    Inventors: Grant Howard McGibney, Patrick Troy Gray, Gerald Dale Morrison, Daniel Keith Van Ostrand
  • Patent number: 10554218
    Abstract: A sigma-delta modulator and method for converting an input voltage such as an analog signal into a digital signal is presented. The modulator may be used as an analog-to-digital converter (ADC). The modulator has a plurality of bias transistors with at least one p-type transistor and at least one n-type transistor. The modulator receives a bias voltage, wherein each bias transistor receives the same bias voltage. This sigma-delta modulator results in reduced power consumption.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventor: Petrus Hendrikus Seesink
  • Patent number: 10547323
    Abstract: A bitstream converter for converting a 1-bit pulse density modulated (PDM) bitstream signal into an analog audio signal, the bitstream converter comprising: a processor configured to process the 1-bit PDM bitstream signal using a return to zero clock having a frequency higher than a sampling frequency of the 1-bit PDM bitstream signal to output a corresponding 1-bit return to zero signal, wherein the processor is configured to process the 1-bit PDM signal to ensure a portion of each bit of the 1-bit PDM bitstream signal is zero for a duration which is based on the frequency of the return to zero clock; and signal processing means configured to extract the analog audio signal from the 1-bit return to zero signal by filtering the 1-bit return to zero signal.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: January 28, 2020
    Assignee: D&M Holdings, Inc.
    Inventors: Rainer Finck, Shozo Kawahara
  • Patent number: 10541707
    Abstract: The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 21, 2020
    Assignee: UNIVERSITY COLLEGE CORK, NUI, CORK
    Inventors: Hongjia Mo, Michael Peter Kennedy
  • Patent number: 10530385
    Abstract: A Sigma-Delta (??) modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f0 to a digital output signal at a sampling frequency fs. The ?? modulator comprises a quantizer (420) for generating the digital output signal and a loop filter for shaping the quantization noise. The loop filter comprises at least one subfilter (430, 410) centered around a frequency f0 and constant noise shaping coefficients (451, 452, 453). The ?? modulator further comprises a tunable delay element (455), a frequency adjuster (480) for adjusting the sampling frequency fs such that the normalized center frequency f0/fs is constant, and a delay adjuster (490) for adjusting the loop delay td implemented by the quantizer and the tunable delay element (455), such that the normalized loop delay td/Ts falls in a predetermined range [tmin, tmax], where Ts=1/fs.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 7, 2020
    Assignees: SORBONNE UNIVERSITE, Centre National de la Recherche Scientifique
    Inventors: Hassan Aboushady, Tamer Badran, Alhassan Sayed