Abstract: Described herein is a method and apparatus for reducing ISI in a single-bit ?? modulator without reducing the dynamic range of the modulator. In one embodiment, the signal fed back to the input of the modulator is not the single-bit outputs of a quantizer as in the prior art, but rather patterns of such outputs. The patterns are selected so that each pattern has the same number of transition edges and there is thus no mismatch of transition times. In one embodiment, the patterns are created by digital logic. In another embodiment, an analog signal is added to the error signal in the feedback loop which causes the quantizer to generate the patterns. When the amplitude of the input signal exceeds a certain level, the modulator reverts to the typical operation of a prior art modulator, thus preserving the full dynamic range of the modulator.

Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Abstract: Techniques regarding a DSFQ logic family are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a dynamic single flux quantum logic circuit that has a self-resetting internal state and can be powered by direct current. Further, the self-resetting internal state can be characterized by two time constants.

Abstract: A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.

Abstract: A partitioned delta-sigma modulator for high-speed applications includes a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series. In some aspects, each of the plurality of modulation stages is configured to combine a first error signal from a prior modulation stage of the plurality of modulation stages with a first digital signal to produce an adder signal. In some aspects, the first error signal includes a delay from the prior modulation stage. Each of the plurality of modulation stages is also configured to convert the adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width. Each of the modulation stages is also configured to provide a second error signal based on the quantized signal to a subsequent modulation stage of the plurality of modulation stages.

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.

Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.

Abstract: To effectively suppress an idle tone in a delta-sigma modulator that generates a feedback signal by a digital-to-analog converter. A filter integrates a difference between an input analog signal and a feedback signal, and outputs the integrated difference as an integrated signal. A preceding-stage quantizer quantizes an integrated signal into a digital signal, and outputs the resulting digital signal as a preceding-stage output signal. An adder adds a predetermined dithering signal to a preceding-stage output signal, and outputs the resulting signal as a subsequent-stage input signal. A subsequent-stage quantizer configured to quantize the subsequent-stage input signal into a digital signal of a shorter number of bits than a preceding-stage output signal, and outputs the resulting digital signal as a subsequent-stage output signal.

Abstract: The invention relates to a communication system for a vehicle, which device includes a sensor device, wherein the sensor device is arranged to capture sensor data when the sensor device moves. A receiving device receives reference data from an external management system and a processing device determines a difference between the captured sensor data and the corresponding reference data, wherein the determined difference between the captured sensor and the corresponding reference data is transmitted to the external management system.

Abstract: A source driver is proposed. The source driver includes N output buffers, (N?1) switches, a first auxiliary switch, a second auxiliary switch, and a third auxiliary switch. The (N?1) switches are respectively coupled between N output terminals of the N output buffers. The first auxiliary switch is coupled between a first output terminal among the N output terminals of the N output buffers and a first endpoint. The second auxiliary switch is coupled between the first output terminal and a second endpoint. The third auxiliary switch is coupled between the first output terminal and a third endpoint. Each of the first endpoint, the second endpoint, and the third endpoint receives a first fixed voltage, a second fixed voltage, a third fixed voltage, or is in a floating state.

Abstract: An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.

Abstract: The present disclosure includes a photodetector element (11) that converts an optical signal into an electric current signal; a transimpedance amplifier (12a) that converts the electric current signal into a voltage signal; a differential amplifier (12d) that converts the voltage signal into a differential signal, by performing differential amplification of a difference between the voltage signal and a threshold voltage; an LOS detection circuit that detects a no-signal section of the optical signal; and an MCU that repeatedly executes offset cancellation processing, the offset cancellation processing including threshold voltage change processing in which the threshold voltage is changed such that an offset voltage of the differential signal is reduced, the MCU 13 skipping the threshold voltage change processing in the no-signal section.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.

Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

Abstract: Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.

Abstract: A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n?1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.

Abstract: An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

Abstract: Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.

Abstract: An analog or digital to encoder signal converter is provided that includes a current sense circuit, if an analog input, configured to receive an analog signal from a sensor and convert the signal into a digital signal via an analog-to-digital converter. The digital signal is processed to generate an appropriate reading value and an encoder string is made that represents the desired value for data transmission, wherein the string is formatted for a selected, specific encoder reader protocol. In this way, existing data collection systems that require a specific encoder protocol for data transmissions can be expanded to collect data from any sensing device with an analog or digital output, thereby adding value to existing encoder data collection systems by enabling them to collect data from devices other than just the customer billing meters for which the encoder protocol networks were designed.

Abstract: An integrated quantum random noise source includes a substrate, an optical oscillator that may be integral to the substrate coupled by an optical waveguide to an optical directional coupler. The optical directional coupler has two outputs that are coupled by optical waveguides to a pair of photodetectors that are part of a balanced photodetector. The balanced photodetector in response outputs an analogue signal proportional to the difference in photocurrents of the two photodetectors. The analogue output signal from the balanced photodetector is a random Gaussian-distributed signal representative of quadrature measurements on the quantum vacuum state of light. The random noise source can be coupled other apparatus to provide a source of random bits.

Abstract: A current sensing system and delta sigma modulator architecture are discloses for sensing and digitizing a current input signal from a high impedance signal source with improve power efficiency. The delta sigma modulator integrates a signal condition stage within the delta sigma modulator feedback loop by utilizing a capacitive summation stage. For given gain, resolution, and bandwidth requirements, the delta sigma modulator architecture achieves reduced power consumption by advantageously reducing the number of nodes in the system that require a high dynamic range. Additionally, the delta sigma modulator has very high input impedance such that the input of the delta-sigma modulator can be connected directly to a high impedance signal source, without the need for a front-end pre-amplifier stage, or the like.

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract: The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.

Abstract: A method includes applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin to a digital stream using a Sigma-Delta modulator; converting the digital stream to a first digital output signal proportional to the analog signal in a first input range between a first analog signal value and a second analog signal value, where the first input range corresponds to a pre-determined range of the analog signal smaller than a full-scale input range of the analog signal; converting the digital stream to a second output signal; comparing the second output signal to a first threshold corresponding to a third analog signal value at the input pin that is outside of the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

Abstract: Methods and systems for high frequency injection and detection for improved false acceptance reduction are disclosed. An information handling system may be configured to receive audio data and to add an identification signal to the audio data, wherein the identification signal is determined based on the audio data. The combined audio data and the identification signal may be output to a receiving device. An information handling system may also be configured to receive data that includes audio data and an identification signal that is associated with one or more frequencies in the audio data, identify the one or more frequencies in the audio data that are associated with the identification signal, and attenuate the one or more frequencies in the audio data to obtain modified audio data. The modified audio data may be output for audio processing.

Abstract: The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.

Abstract: A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels.

Abstract: A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.

Abstract: This disclosure is directed to communication generation by traversing routes of a graph in a complex computing network. The communication generation is used for determining whether an input signal has certain desired signal attributes.

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Abstract: An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency, where the analog signal includes a set of pure tone components. The analog to digital conversion circuit further includes a digital decimation filtering circuit operable to convert the first digital signal into a second digital signal having a second data rate frequency. The analog to digital conversion circuit further includes a digital bandpass filter (BPF) circuit operable to convert the second digital signal into an outbound digital signal having a third data rate frequency, where the digital bandpass filter circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone.

Abstract: A sigma-delta modulator and method for converting an input voltage such as an analog signal into a digital signal is presented. The modulator may be used as an analog-to-digital converter (ADC). The modulator has a plurality of bias transistors with at least one p-type transistor and at least one n-type transistor. The modulator receives a bias voltage, wherein each bias transistor receives the same bias voltage. This sigma-delta modulator results in reduced power consumption.

Abstract: A bitstream converter for converting a 1-bit pulse density modulated (PDM) bitstream signal into an analog audio signal, the bitstream converter comprising: a processor configured to process the 1-bit PDM bitstream signal using a return to zero clock having a frequency higher than a sampling frequency of the 1-bit PDM bitstream signal to output a corresponding 1-bit return to zero signal, wherein the processor is configured to process the 1-bit PDM signal to ensure a portion of each bit of the 1-bit PDM bitstream signal is zero for a duration which is based on the frequency of the return to zero clock; and signal processing means configured to extract the analog audio signal from the 1-bit return to zero signal by filtering the 1-bit return to zero signal.

Abstract: The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

Abstract: A duty compensation device of one embodiment has a structure capable of more accurately setting a duty of a clock within an appropriate range. The duty compensation device comprises a duty adjusting unit, a duty measuring unit, a controlling unit. The duty measuring unit generates a sampling clock of a frequency fn that is asynchronous to the clock over an n-th period Tn (n=1 to N and N is an integer of 3 or more), and obtains measurement information for specifying the duty of the clock by using the sampling clock. The controlling unit determines a control code to be given to the duty adjusting unit based on control code candidates obtained for each of the N periods T1 to TN and the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.

Abstract: A Sigma-Delta (??) modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f0 to a digital output signal at a sampling frequency fs. The ?? modulator comprises a quantizer (420) for generating the digital output signal and a loop filter for shaping the quantization noise. The loop filter comprises at least one subfilter (430, 410) centered around a frequency f0 and constant noise shaping coefficients (451, 452, 453). The ?? modulator further comprises a tunable delay element (455), a frequency adjuster (480) for adjusting the sampling frequency fs such that the normalized center frequency f0/fs is constant, and a delay adjuster (490) for adjusting the loop delay td implemented by the quantizer and the tunable delay element (455), such that the normalized loop delay td/Ts falls in a predetermined range [tmin, tmax], where Ts=1/fs.

Abstract: Various embodiments of the present technology may comprise a method, apparatus or system for dynamic addressing decimation filtering. In various embodiments, the apparatus comprises an analog modulator and a multi-bit dynamically addressing decimation filter. By pairing an analog modulator with the proper configuration with a multi-bit dynamically addressing decimation filter with the proper matching number of physical sub decimation filters, decimation filtering can be completed with a smaller number of physical sub decimation filters “N” than the quantizer level “M.

Abstract: A magnetic sensor, a motor and an application apparatus are provided. The magnetic sensor includes a magnetic sensing element, a chopping switch, a first discharging branch, and a second discharge branch. The magnetic sensing element includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first discharging branch is coupled between the first terminal and the third terminal. The second discharging branch is coupled between the second terminal and the fourth terminal. Before the first terminal and the third terminal serve as power input terminals, the second terminal and the fourth terminal serve as output terminals of magnetic field detection signal, the second discharging branch is turned on; before the first terminal and the third terminal serve as the magnetic field detection signal output terminals, the second terminal and the fourth terminal serve as power input terminals, the first discharging branch is turned on.

Abstract: A signal processing arrangement has a signal input for connecting a capacitive sensor. An amplifier circuit is coupled between the signal input and a feedback point. A loop filter is coupled downstream to the feedback point. A quantizer is connected downstream to the loop filter and provides a multi-bit output word. The multi-bit output word consists of one or more higher significance bits and one or more lower significance bits. A first feedback path is coupled between a quantizer and the feedback point for providing a first feedback signal to the feedback point being representative of the one or more lower significance bits. A second feedback path is coupled to the quantizer for providing a second feedback signal to the signal input being representative of the one or more higher significance bits.

Abstract: An electronic circuit for a microphone and a microphone are disclosed. In an embodiment, the electronic circuit includes a sigma-delta modulator having a configurable resolution and a mode selector, wherein the sigma-delta modulator is selectively operable in at least two operation modes and the mode selector is configured to determine a desired operation mode dependent on an externally provided control signal and to select the resolution of the sigma-delta modulator according to the determined operation mode.

Abstract: Embodiments of the invention provide a signal transmission method of a wireless communication system, the method comprising: selecting a phase compensation value for a k-th layer of user data of the wireless communication system, performing, according to the phase compensation value, phase rotation on a reference signal in the k-th layer user data, so that a signal power of the reference signal, after performing interference mitigation thereon at a transmission end, does not exceed a predetermined power threshold, wherein, k is selected from 1 to M, and M is less than or equal to K, and K is the total number of layers of user data of the wireless communication system; and transmitting, through a wireless channel, the reference signal after the phase rotation.

Abstract: An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.

Abstract: A hearing assistive device having an input transducer (18) for picking up sound from the environment, a digital signal processor (27) for alleviating a hearing loss of a specific user by compensating an audio signal according to the users hearing deficit, and an output transducer (29) for reproducing the compensated audio signal. The hearing assistive device further includes an integrated circuit component (40) having at least one analog-to-digital converter adapted for receiving an audio input signal from a microphone and providing a data output for signal processing. The at least one analog-to-digital converter includes an AC filter (50) preventing audible signal losses towards the microphone, and the AC filter (50) is provided with all components integrated in the integrated circuit component (40).

Abstract: A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816).

Abstract: The present technology relates to a signal processing apparatus, a control method, an image pickup element, and an electronic appliance that achieve the suppression of an increase in electric power consumption. The signal processing apparatus may be configured to control an amount of electric current at a differential stage in a comparison unit that compares signal levels of a plurality of signals and reduce the amount of electric current for a period other than this comparison period. For example, the amount of electric current may be reduced by turning off part of a group of switches each capable of disconnecting a path of an electric current from an electric current source In addition, for example, the amount of electric current may be reduced by causing a gate potential at the electric current source unit to decrease. The present technology can be applied to, for example, an image pickup element and an electronic appliance.

Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.

Abstract: A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.

Abstract: A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

Abstract: A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.