Abstract: An audio processing system can include an Analog to Digital Converter structured to receive an analog input signal and convert the analog input signal to a digital input signal, a first processor coupled with the Analog to Digital Converter, the first processor including at least one programmable bi-quadratic filter chain structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a first clock rate, and a second processor coupled with the first processor and the Analog to Digital Converter and structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a second clock rate that is different from the first clock rate.

Abstract: A sigma-delta analog-to-digital converter (ADC) includes a feed-forward circuit, a finite-impulse-response (FIR) digital-to-analog converter (DAC), and a decimation filter. The feed-forward circuit is configured to receive an analog input signal and a feedback signal and generate a set of digital signals. Each feedback element of the FIR DAC includes a flip-flop and a reset circuit. The reset circuit is configured to receive a corresponding reset signal of a set of reset signals and output a reference output signal when the corresponding reset signal is deactivated. The reset signal of each feedback element is deactivated sequentially after each cycle of a clock signal that is received by the flip-flop associated with a corresponding reset circuit of each feedback element. The feedback signal is generated based on the reference output signal. The decimation filter is configured to generate a digital output signal based on the set of digital signals.

Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.

Abstract: Repetitive waveforms are processed to produce an averaged replica of the waveforms by first determining a stream of digital samples, with random time shifts of waveform starts relative to the samples. A mutual arrangement of a trigger signal and a following sample over a succession of sampling periods, enables k sections coinciding with segments [k·T/K, (k+1)·T/K]. K is determined and a distance D between the trigger signal and the following sample is calculated. Second, values of the samples are transformed so that waveforms represented by the samples, are shifted in time by D in relation to the sample positions. The mutual positions of the delayed waveforms and the sampling clock along multiple axes, exactly repeats so that values of the produced samples along the axes coincide. The discreet time delays before averaging avoid frequency component distortions in resulting replicas of the waveforms.

Abstract: A signal processing structure and method are presented. A first digital filter operates on received sigma-delta modulated (SDM) input signals. A second pre-processing digital filter receives a SDM input signal, directly low pass filter the SDM input signal and provides an output SDM signal. The output sigma-delta modulated signal is provided as an input for said first digital filter. In standard digital systems operating with digital microphones, filtering of the microphones' output signal requires to first convert the signal into pulse code modulation (PCM), then filter and finally convert back to pulse density modulation (PDM). This approach increases the latency of the system because decimation and interpolation must be performed in order to pass from PDM to PCM. By using filters that operate directly on the oversampled PDM output of the digital microphones it is possible to reduce the latency of the system and minimize the hardware area.

Abstract: A channel driver circuit includes a differential module and a driver module. In some examples, the channel driver circuit also includes a sigma-delta module. The differential module receives, via a single node of a load, a channel driving signal that is provided to the load at the single node (e.g., that is based on an electrical characteristic of the load) and generates an analog error signal that is based on the channel driving signal and a reference signal. The driver module is coupled to the differential module and generates the channel driving signal based on the analog error signal or a digital error signal corresponding to the analog error signal and transmits the channel driving signal via the single node to the load. The channel driver circuit simultaneously transmits the channel driving signal to the load at the single node and senses the channel driving signal at the single node.

Abstract: Described herein is an improved apparatus for increasing the performance of a ?? modulator, which may function as an ADC. In one embodiment, the ?? modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ?? modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

Abstract: Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed.

Abstract: An apparatus for calibrating an analog-to-digital converter is provided. The apparatus includes a reference input generation circuit configured to subsequently generate two reference inputs for calibrating the analog-to-digital converter. The two reference inputs both represent ramp waveforms, wherein the ramp waveforms represented by the two reference inputs are different from each other. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the analog-to-digital converter to either the reference input generation circuit or to a signal node capable of providing an analog input for digitization.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

Abstract: A voltage-controlled ring oscillator (VCRO) and a VCRO-based sigma delta modulator having capability of enabling and disabling the VCRO cells. A VCRO includes a plurality of inverters coupled in a ring and a transition detector. The transition detector detects a transition of a first inverter and sends a control signal to enable a second inverter if the transition of the first inverter is detected. The transition detector may include a comparator configured to compare an input and an output of an inverter(s) to detect the transition of the first inverter and a latch configured to hold the control signal until it is reset.

Abstract: A sigma-delta analog-to-digital converter (ADC) is disclosed. The sigma delta ADC has an analog input and a digital output. A sigma-delta modulator input is coupled to the analog input and a sigma-delta modulator output. A first filter having a first filter input is coupled to the sigma-delta modulator output and a first filter output. A second filter having a second filter input is coupled to the sigma-delta modulator output and a second filter output. The sigma-delta ADC operates in a first and second mode. In a first mode, the first filter output is coupled to the digital output. In a second mode, the second filter output is coupled to the digital output.

Abstract: Described herein are apparatus and methods for low speed characterization of a high-speed signal. A circuit includes a sub-sampling circuit configured to sub-sample a high-speed signal received from a device, a reconstruction loop circuit configured to reconstruct a low-speed signal from the sub-sampled high-speed signal, a low pass filter configured to filter the reconstructed low-speed signal, a discrete time low pass filter configured to mitigate skew rate requirements of the filtered low-speed signal for a digitization circuit, a continuous time low pass filter configured to smooth the skew rate mitigated low-speed signal and the digitization circuit is configured to generate a digital representation of the smoothed low-speed signal for characterization by a characterization device, and shape a noise associated with the smoothed low-speed signal outside a frequency range of interest of the smoothed low-speed signal.

Abstract: A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.

Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

Abstract: A circuit device includes a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first and second clock signals, and a PLL circuit adapted to perform phase synchronization between the first and second clock signals.

Abstract: A continuously or step variable passive noise filter for removing noise from a signal received from a DUT added by a test and measurement instrument channel. The noise filter may include, for example, a splitter splits a signal into at least a first split signal and a second split signal. A first path receives the first split signal and includes a variable attenuator and/or a variable delay line which may be set based on the channel response of the DUT which is connected. The variable attenuator and/or the variable delay line may be continuously or stepped variable, as will be discussed in more detail below. A second path is also included to receive the second split signal and a combiner combines a signal from the first path and a signal from the second path into a combined signal.

Abstract: A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.

Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.

Abstract: This disclosure provides an active envelope detector to generate an output voltage based on an input radio-frequency (RF) signal. The active envelope detector includes a plurality of transistors configured to operate in a sub-threshold mode and generate an output voltage based on the input RF signal. A delta-modulation analog-to-digital converter (ADC) and a sigma-delta modulation ADC are provided. Both ADCs include an implementation of the active envelope detector to receive input RF signals.

Abstract: The present disclosure relates to a solid-state imaging apparatus, a method for driving the solid-state imaging apparatus, and electronic equipment for improving the determination speed of comparators and allowing the comparators to operate faster. A differential input circuit operates on a first power supply voltage and outputs a signal when a voltage of a pixel signal is higher than a voltage of a reference signal. A voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to a second power supply voltage. A positive feedback circuit accelerates a transition rate at which a comparison result signal of a comparison in voltage between the pixel signal and the reference signal is inverted. Multiple time code transfer sections each include a shift register that transfer a time code. The present disclosure can be applied, for example, to an imaging apparatus including A/D converters disposed in pixels.

Abstract: Various implementations described herein are directed to device having multiple stages. The device may include a first stage that converts an analog voltage signal in a power supply domain into a digitally coded signal. The device may include a second stage that generates a derivative of the digitally coded signal, detects an event of the analog voltage signal based on the derivative of the digitally coded signal, and derives a control signal based on the event. The device may include a third stage that injects current into or sinks current from the power supply domain that is associated with the analog voltage signal based on the control signal.

Abstract: A system may include an input configured to receive a digital audio input signal having at least four and fewer than 65,000 quantization levels and sampled at at least 500 kilohertz, a low-pass filter configured to receive the digital audio input signal and perform filtering on the digital audio input signal to generate a filtered digital audio input signal having a bandwidth of between approximately 100 hertz and 10 kilohertz, a digital-to-analog converter configured to receive the filtered digital audio input signal and convert the filtered digital audio input signal into an equivalent analog audio input signal, and a driver configured to receive the equivalent analog audio input signal and drive an analog audio output signal to a transducer, wherein a group delay from the input to an output of the driver is less than 50 microseconds.

Abstract: In accordance with implementations of the subject matter described herein, a hybrid digital-analog coding scheme is proposed. In general, in accordance with implementations of the subject matter described herein, digital or analog encoding is selected at a level of chunks of a frame rather than at a level of the whole frame. Further, the encoding of a chunk is based on an expected distortion to be caused by analog transmission of the chunk over a communication channel, the distortion being estimated based on a constraint on available transmission resources over the transmission channel.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for an analog-to-digital converter. Methods and apparatus for an analog-to-digital converter (ADC) may be configured as a delta-sigma type ADC and include an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier. The switched-capacitor circuits receive various control signals such that one SC circuit performs sampling while the other SC circuit simultaneously performs integration.

Abstract: Embodiments provide a MEMS microphone comprising a MEMS microphone unit and a modulator connected downstream the MEMS microphone unit. The modulator is configured to apply a defined phase shift to a signal to be modulated.

Abstract: Embodiments relate to sensing a current provided by a power supply circuit. The current sensing circuit includes a sense transistor for sensing the current provided by a main transistor, a driver for controlling a bias provided to the sense transistor and the main transistor, and a sense resistor for converting the sensed current to a voltage value. Moreover, the current sensing circuit includes a controller that modifies at least one of: (a) a resistance of the main transistor by adjusting the bias voltage provided by the driver, (b) a gain ratio between a load current and a sensing current by adjusting a number of individual devices that are active in the sense transistor, and (c) a resistance of the sense resistor.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Abstract: A continuous time Delta-Sigma (CT-??) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-?? modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-?? modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

Abstract: A method for detecting frequency mismatch in microelectromechanical systems (MEMS) gyroscopes is described. Detection of the frequency mismatch between a drive signal and a sense signal may be performed by generating an output signal whose spectrum reflects the physical characteristics of the gyroscope, and using the output signal to determine the frequency fC of the sense signal. The output signal may be generated by cross-correlating a random or pseudo-random noise signal with a response signal, where the response signal can be obtained by allowing the noise signal to pass through a system designed to have a noise transfer function that mimics the frequency response of the gyroscope. Since the noise signal is random or pseudo-random, cross-correlating the noise signal with the response signal reveals spectral characteristics of the gyroscope. To improve computational efficiency, the cross-correlation can be performed on demodulated versions of the noise signal and the response signal.

Abstract: Noise suppression is achieved by averaging a sequence of repetitive waveforms with correction of frequency distortions, establishing a real time processing of signals. First, the waveforms are processed seriatim, and saved in partitioned memory. Then, the memory contents are merged to form an output digital signal. Initially, an input repetitive signal is sampled with a sampling period T, and divided into K sections along the sampling period so that a kth section, where 0?k<K, coincides with segment [k·T/K, (k?1)·T/K]. Time displacement detection determines relative positions of trigger pulses and edges of the sampling clock, and the number k of a sampling period section where the trigger pulse appears, keeping k unchanged thereafter. A resultant stream of N·K samples is transmitted through a lowpass filter, followed by decimation by K, to complete the averaging.

Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

Abstract: An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; and a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM.

Abstract: An amplification device including: a switch including an output that is suitable for being connected to a first or a second input; a first branch that is connected to the first input, which applies a first gain to generate a first amplified signal; a second branch that is connected to the second input, which applies a second gain to generate a second amplified signal; a controller for controlling the switching of the switch to apply the first or the second amplified signal to the output, depending on whether or not the value of a predetermined quantity of the first amplified signal falls within a predetermined range. The first gain and the second gain being non-zero real numbers of opposite sign.

Abstract: A delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a near-zero asymmetric quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: A system for Nyquist zone disambiguation of a received broadband RF signal is disclosed. The system includes continuous-wave (CW) and pulsed photonic sources whose outputs may be combined into a single input. Both CW and pulsed components of the combined photonic input are modulated by sampling the received RF input signal. The system includes hybrid couplers for IQ demodulation of the modulated combined photonic signal. The system demultiplexes the demodulated inphase and quadrature differential photonic signals into their CW and pulsed component signals. The pulsed component signals may be digitized by narrowband multibit analog-digital converters (ADC) while the CW component signals are digitized by high speed low latency mono-bit ADCs to determine frequency components (e.g., bandwidth information) and other spectrum information of the RF input signal.

Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.

Abstract: A digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible. The arrangement converts the analog signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.

Abstract: An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits.

Abstract: A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levels—a functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

Abstract: A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles.

Abstract: A ?? modulator includes: an integrator having an operational amplifier and an integral capacitor; a quantizer outputting a quantization result; a D/A converter connected to a first input terminal of the operational amplifier through a first control switch, and subtracting an electric charge based on the quantization result from an electric charge stored in the integral capacitor to perform feedback of the quantization result to the integrator; a control circuit outputting a digital output value; and a sampling capacitor being connected to the first input terminal through a second control switch. The second control switch switches on and off an electrical connection between the sampling capacitor and the intermediate point between the integral capacitor and first input terminal, and plural feedbacks of the quantization results are performed per one sampling cycle.

Abstract: An electric control device includes a first delta sigma modulator having a clock input connection, a second delta sigma modulator having a clock input connection, and an evaluation unit. The evaluation unit includes a first clock output connection which is connected to the clock input connection of the first delta sigma modulator by a first electrical cable, and a second clock output connection which is connected to the clock input connection of the second delta sigma modulator by a second electrical cable. The evaluation unit is designed to generate a clock signal (CLK1) at the first clock output connection (7) in phase opposition to a clock signal (CLK2) at the second clock output connection (9).

Abstract: Described herein is a ?? modulator with improved metastability in which the control loop remains stable. In one embodiment, the ?? modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero.

Abstract: Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Abstract: A capacitor-drop power supply includes a rectifier and a switched capacitor converter coupled to the rectifier. The rectifier is configured to receive an alternating current (AC) signal at an AC voltage and convert the AC signal into a rectified direct current (DC) signal at a rectified voltage. The switched capacitor converter is configured to receive the rectified DC signal and generate a converter output signal at a converter voltage that is proportional to the rectified voltage and that is less than the AC voltage.