Abstract: The present disclosure relates to a solid-state imaging apparatus, a method for driving the solid-state imaging apparatus, and electronic equipment for improving the determination speed of comparators and allowing the comparators to operate faster. A differential input circuit operates on a first power supply voltage and outputs a signal when a voltage of a pixel signal is higher than a voltage of a reference signal. A voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to a second power supply voltage. A positive feedback circuit accelerates a transition rate at which a comparison result signal of a comparison in voltage between the pixel signal and the reference signal is inverted. Multiple time code transfer sections each include a shift register that transfer a time code. The present disclosure can be applied, for example, to an imaging apparatus including A/D converters disposed in pixels.

Abstract: Various implementations described herein are directed to device having multiple stages. The device may include a first stage that converts an analog voltage signal in a power supply domain into a digitally coded signal. The device may include a second stage that generates a derivative of the digitally coded signal, detects an event of the analog voltage signal based on the derivative of the digitally coded signal, and derives a control signal based on the event. The device may include a third stage that injects current into or sinks current from the power supply domain that is associated with the analog voltage signal based on the control signal.

Abstract: A system may include an input configured to receive a digital audio input signal having at least four and fewer than 65,000 quantization levels and sampled at at least 500 kilohertz, a low-pass filter configured to receive the digital audio input signal and perform filtering on the digital audio input signal to generate a filtered digital audio input signal having a bandwidth of between approximately 100 hertz and 10 kilohertz, a digital-to-analog converter configured to receive the filtered digital audio input signal and convert the filtered digital audio input signal into an equivalent analog audio input signal, and a driver configured to receive the equivalent analog audio input signal and drive an analog audio output signal to a transducer, wherein a group delay from the input to an output of the driver is less than 50 microseconds.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for an analog-to-digital converter. Methods and apparatus for an analog-to-digital converter (ADC) may be configured as a delta-sigma type ADC and include an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier. The switched-capacitor circuits receive various control signals such that one SC circuit performs sampling while the other SC circuit simultaneously performs integration.

Abstract: Embodiments provide a MEMS microphone comprising a MEMS microphone unit and a modulator connected downstream the MEMS microphone unit. The modulator is configured to apply a defined phase shift to a signal to be modulated.

Abstract: In accordance with implementations of the subject matter described herein, a hybrid digital-analog coding scheme is proposed. In general, in accordance with implementations of the subject matter described herein, digital or analog encoding is selected at a level of chunks of a frame rather than at a level of the whole frame. Further, the encoding of a chunk is based on an expected distortion to be caused by analog transmission of the chunk over a communication channel, the distortion being estimated based on a constraint on available transmission resources over the transmission channel.

Abstract: Embodiments relate to sensing a current provided by a power supply circuit. The current sensing circuit includes a sense transistor for sensing the current provided by a main transistor, a driver for controlling a bias provided to the sense transistor and the main transistor, and a sense resistor for converting the sensed current to a voltage value. Moreover, the current sensing circuit includes a controller that modifies at least one of: (a) a resistance of the main transistor by adjusting the bias voltage provided by the driver, (b) a gain ratio between a load current and a sensing current by adjusting a number of individual devices that are active in the sense transistor, and (c) a resistance of the sense resistor.

Abstract: A continuous time Delta-Sigma (CT-??) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-?? modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-?? modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Abstract: A method for detecting frequency mismatch in microelectromechanical systems (MEMS) gyroscopes is described. Detection of the frequency mismatch between a drive signal and a sense signal may be performed by generating an output signal whose spectrum reflects the physical characteristics of the gyroscope, and using the output signal to determine the frequency fC of the sense signal. The output signal may be generated by cross-correlating a random or pseudo-random noise signal with a response signal, where the response signal can be obtained by allowing the noise signal to pass through a system designed to have a noise transfer function that mimics the frequency response of the gyroscope. Since the noise signal is random or pseudo-random, cross-correlating the noise signal with the response signal reveals spectral characteristics of the gyroscope. To improve computational efficiency, the cross-correlation can be performed on demodulated versions of the noise signal and the response signal.

Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; and a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM.

Abstract: An amplification device including: a switch including an output that is suitable for being connected to a first or a second input; a first branch that is connected to the first input, which applies a first gain to generate a first amplified signal; a second branch that is connected to the second input, which applies a second gain to generate a second amplified signal; a controller for controlling the switching of the switch to apply the first or the second amplified signal to the output, depending on whether or not the value of a predetermined quantity of the first amplified signal falls within a predetermined range. The first gain and the second gain being non-zero real numbers of opposite sign.

Abstract: Noise suppression is achieved by averaging a sequence of repetitive waveforms with correction of frequency distortions, establishing a real time processing of signals. First, the waveforms are processed seriatim, and saved in partitioned memory. Then, the memory contents are merged to form an output digital signal. Initially, an input repetitive signal is sampled with a sampling period T, and divided into K sections along the sampling period so that a kth section, where 0?k<K, coincides with segment [k·T/K, (k?1)·T/K]. Time displacement detection determines relative positions of trigger pulses and edges of the sampling clock, and the number k of a sampling period section where the trigger pulse appears, keeping k unchanged thereafter. A resultant stream of N·K samples is transmitted through a lowpass filter, followed by decimation by K, to complete the averaging.

Abstract: An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

Abstract: A delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a near-zero asymmetric quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: A system for Nyquist zone disambiguation of a received broadband RF signal is disclosed. The system includes continuous-wave (CW) and pulsed photonic sources whose outputs may be combined into a single input. Both CW and pulsed components of the combined photonic input are modulated by sampling the received RF input signal. The system includes hybrid couplers for IQ demodulation of the modulated combined photonic signal. The system demultiplexes the demodulated inphase and quadrature differential photonic signals into their CW and pulsed component signals. The pulsed component signals may be digitized by narrowband multibit analog-digital converters (ADC) while the CW component signals are digitized by high speed low latency mono-bit ADCs to determine frequency components (e.g., bandwidth information) and other spectrum information of the RF input signal.

Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.

Abstract: A digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible. The arrangement converts the analog signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.

Abstract: An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits.

Abstract: A ?? modulator includes: an integrator having an operational amplifier and an integral capacitor; a quantizer outputting a quantization result; a D/A converter connected to a first input terminal of the operational amplifier through a first control switch, and subtracting an electric charge based on the quantization result from an electric charge stored in the integral capacitor to perform feedback of the quantization result to the integrator; a control circuit outputting a digital output value; and a sampling capacitor being connected to the first input terminal through a second control switch. The second control switch switches on and off an electrical connection between the sampling capacitor and the intermediate point between the integral capacitor and first input terminal, and plural feedbacks of the quantization results are performed per one sampling cycle.

Abstract: A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levels—a functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

Abstract: A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles.

Abstract: A capacitor-drop power supply includes a rectifier and a switched capacitor converter coupled to the rectifier. The rectifier is configured to receive an alternating current (AC) signal at an AC voltage and convert the AC signal into a rectified direct current (DC) signal at a rectified voltage. The switched capacitor converter is configured to receive the rectified DC signal and generate a converter output signal at a converter voltage that is proportional to the rectified voltage and that is less than the AC voltage.

Abstract: Described herein is a ?? modulator with improved metastability in which the control loop remains stable. In one embodiment, the ?? modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero.

Abstract: Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Abstract: An electric control device includes a first delta sigma modulator having a clock input connection, a second delta sigma modulator having a clock input connection, and an evaluation unit. The evaluation unit includes a first clock output connection which is connected to the clock input connection of the first delta sigma modulator by a first electrical cable, and a second clock output connection which is connected to the clock input connection of the second delta sigma modulator by a second electrical cable. The evaluation unit is designed to generate a clock signal (CLK1) at the first clock output connection (7) in phase opposition to a clock signal (CLK2) at the second clock output connection (9).

Abstract: In accordance with various embodiments of the disclosed subject matter, a system, apparatus and method is configured to provide a poly-phased, time-interleaved radio frequency (RF) digital-to-analog converter (DAC) suitable for use in radar, radio, mobile and other RF systems.

Abstract: An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.

Abstract: Systems and methods are provided for operating a physiological monitoring system for determining a physiological parameter of a subject. The physiological system may comprise a pulse oximetry sensor for generating a photoplethysmography (PPG) signal and a gain controller for setting a light detection level. The system may also comprise a filter for filtering the PPG signal. The filter may comprise at least one of filter history and filter coefficients. The system may comprise a processor for determining the power level of light sources of the pulse oximetry sensor and the light detection gain level, and calculating a scaling factor based on the determined power level and the light detection gain level. The processor may also be used for scaling one or more of the filter history and filter coefficients based on the scaling factor, and determining at least one physiological parameter based on the filtered PPG signal.

Abstract: A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.

Abstract: A system may include an input configured to receive a digital audio input signal having at least four and fewer than 65,000 quantization levels and sampled at at least 500 kilohertz, a low-pass filter configured to receive the digital audio input signal and perform filtering on the digital audio input signal to generate a filtered digital audio input signal having a bandwidth of between approximately 100 hertz and 10 kilohertz, a digital-to-analog converter configured to receive the filtered digital audio input signal and convert the filtered digital audio input signal into an equivalent analog audio input signal, and a driver configured to receive the equivalent analog audio input signal and drive an analog audio output signal to a transducer, wherein a group delay from the input to an output of the driver is less than 50 microseconds.

Abstract: An apparatus includes a digital frequency synthesizer (DFS). The DFS includes a time-to-digital converter (TDC) to provide an output signal that represents a phase difference between a reference signal and a feedback signal. The DFS further includes a scaling circuit, which has an adaptively changed gain, to provide a scaled residue signal used to cancel an effect of the residue signal in the DFS.

Abstract: Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.

Abstract: A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

Abstract: A multi-channel, multi-band system for wireless communication includes a radio frequency (RF) front end, a mixed-signal front end for converting an incoming analog RF signal into an incoming digital RF signal and converting a composite outgoing digital RF signal into an outgoing analog RF signal, a summation circuit for combining multiple outgoing digital RF signals to the composite outgoing digital RF signal, and multi-band transceivers. Each of the multi-band transceivers may process the incoming digital RF signal to provide an incoming baseband signal and process an outgoing baseband signal to provide an outgoing digital RF signal. The mixed-signal front end may apply a loading control to each transceiver for adjusting an amount of loading on the transmit path from the transceiver to the mixed-signal front-end. The transceivers may individually conduct a feedback calibration on the receive path to optimize the incoming baseband signal for each band.

Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Abstract: A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.

Abstract: A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.

Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.

Abstract: A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.

Abstract: A circuit is for sampling an analog input signal that receives and samples an analog input signal. Sampling circuitry is clocked at a sampling frequency and samples the analog input signal at a rate corresponding to the sampling frequency. The sampling circuitry includes at least one pulse density modulator that includes a comparator configured to be clocked at the sampling frequency, to provide bandpass sampling of the analog input signal at the sampling frequency, and to produce a corresponding pulsed output that is pulse density modulated based on the analog input signal.

Abstract: A second-order ?? modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.

Abstract: A Sigma-Delta (?-?) analog-to-digital converter (ADC) and operation method thereof are provided. The ?-? ADC includes a ?-? modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the ?-? modulator is configured to receive an analog signal. The ?-? modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the ?-? modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the ?-? modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.

Abstract: A system for testing an application-specific integrated circuit, includes a characterization integrated circuit comprising at least two configurable test structures and a test assembly comprising: a device for controlling the characterization integrated circuit, configured to vary at least one physical parameter of at least one configurable test structure, an interface for receiving at least one description of an application-specific integrated circuit and extracting at least one path, a configuration device for activating and interconnecting at least one subset of the logic cells of at least one degraded test structure and of at least one non-degraded test structure, so that they each produce a topology identical to a portion of an extracted path, a measurement control device for performing at least one first measurement of a physical variable on the degraded test structure and at least one second measurement, identical to the first measurement, on the non-degraded test structure.

Abstract: A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.

Abstract: A wireless power receiver for wirelessly receiving power from a wireless power transmitter comprises: a power reception circuit receiving electromagnetic waves emitted from the wireless power receiver so as to output power having an alternating current waveform; a rectifier for rectifying the power, having an AC waveform, outputted from the power reception circuit into power having a direct current waveform; a DC/DC converter for converting, into a voltage of a preset level, a voltage of the power having a direct current waveform, the power being rectified by the rectifier; a charger for charging a battery by using the power having a DC waveform, converted from the DC/DC converter; an alternating current ground connected to the power reception circuit and/or the rectifier so as to receive at least a portion of the power having an alternating current waveform; and a direct current ground connected to the DC/DC converter and/or the charger so as to receive at least a portion of the power having a direct current