Abstract: A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

Abstract: A system, method, and non-transitory computer readable medium that detects trajectories of unmanned aerial vehicles (UAV) approaching a protected site is described. Airborne defense agents (ADAs) located at a fixed radius from the protected and equidistant from one another detect acoustic signals emitted by an approaching UAV. Circuitry included in each ADA use the detected acoustic signals to determine a direction and a distance of each UAV. A base station having a control center (BS-CC) located in the protected site communicates with the ADAs to aggregate direction and distance data from the ADAs. Using the aggregated direction and distance data, the BS-CC predicts routes towards the protected site of the approaching UAV and alerts the protected site of the predicted route of the approaching UAV.

Abstract: A microphone assembly includes an acoustic filter with a first highpass cut-off frequency. The microphone assembly additionally includes a forward signal path and a feedback signal path. The forward signal path is configured to amplify or buffer an electrical signal generated by a transducer in response to sound and to convert the electrical signal to a digital signal. The feedback signal path is configured to generate a digital control signal based on the digital signal and to generate and output a sequence of variable current pulses based on the digital control signal. The variable current pulses suppress frequencies of the electrical signal below a second highpass cut-off frequency, higher than the first highpass cut-off frequency.

Abstract: A signal density modulation (SDM) encoder includes a first subtractor, a sigma circuit and a multi-bit quantizer. The first subtractor is used for receiving an input signal. The sigma circuit is coupled to the first subtractor. The multi-bit quantizer, coupled to the first subtractor and the sigma circuit, is configured to generate an output signal. The sigma circuit or the multi-bit quantizer produces a first feedback signal to the first subtractor. The first subtractor performs a subtraction operation according to the first feedback signal and the input signal, and generates a delta signal. The sigma circuit performs an operation on the delta signal, such that the SDM encoder has a noise transfer function having a high pass filtering effect. The noise transfer function is a ratio of a quantization error brought by the multi-bit quantizer with respect to the input signal. The output signal has more than two levels.

Abstract: In a semiconductor integrated circuit, a first generation circuit generates a common mode voltage of a differential signal. A second generation circuit generates temperature information according to the common mode voltage. The temperature information is information corresponding to a characteristic of an amplifier circuit related to an ambient temperature. A correction circuit corrects a first reference voltage and a second reference voltage according to the temperature information. A comparator includes a first input node to which a first signal line is electrically connected; a second input node to which a second signal line is electrically connected; a third input node to which the corrected first reference voltage is input; and a fourth input node to which the corrected second reference voltage is input.

Abstract: An analog-to-digital converter is connected to a crossbar array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and processing circuitry. The voltage generator includes at least one resistive memory element including a same resistive material as the resistive element included in the crossbar array, and is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element and to divide the first voltage to generate at least one divided voltage. The processing circuitry is configured to compare a signal voltage generated from the crossbar array with the at least one divided voltage to generate at least one comparison signal and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Abstract: An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

Abstract: A negative feedback system architecture and a loop filter thereof are provided. The negative feedback system architecture includes a loop filter, a pulse width modulation circuit, and a driver. The loop filter includes a three-stage series integrator for receiving a signal and outputting the filtered signal. The loop filter has three in-bandwidth poles and at least two in-bandwidth zeros. The pulse width modulation circuit is electrically connected to the loop filter for receiving the filtered signal and modulating it into a pulse width modulation signal to output. The driver is electrically connected to the pulse width modulation circuit and the loop filter for receiving the pulse width modulation signal to generate an output signal to drive a load device, and the output signal is fed back to the loop filter.

Abstract: Methods and apparatus to audio watermarking and watermark detection and extracted are described herein. An example method includes receiving a media content signal, sampling the media content signal to generate samples, storing the samples in a buffer, determining a first sequence of samples in the buffer, determining a second sequence of samples in the buffer, wherein the second sequence of samples is of substantially equal length as the first sequence of samples, calculating an average of the first sequence of samples and the second sequence of samples to generate an average sequence of samples, extracting an identifier from the average sequence of samples, and storing the identifier in a tangible memory.

Abstract: Provided is a digital filter that is configured to generate a first integration signal by integrating data groups, which are generated by sampling sample data within a first time period that overlaps with another time period, configured to generate a second integration signal by integrating data groups, which are generated by sampling the sample data within a second time period that is included in the first time period, the first time period and the second time period overlapping with one another, and configured to output a difference between the first and second integration signals as digital data. The first integration signal is generated during a third time period that is included in the first time period.

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

Abstract: A wide bandwidth ADC circuit that combines a resistive-input continuous-time sigma-delta ADC circuit with a second ADC circuit having a switched capacitor input. The combination of these two ADC circuits can achieve an easy-to-drive, alias free, wide bandwidth ADC that has excellent DC precision.

Abstract: A digital-to-analog converter (DAC) includes a plurality of reference modules, an output capacitor configured to output the analog voltage, and a sharing switch coupled between the output capacitor and the reference modules. The reference modules are mutually connected in parallel. Each reference module includes a reference capacitor and a reference switch connected in series. A plurality of reference capacitances of the reference capacitors are substantially identical. The reference switches are controlled by a plurality of control signals. The control signals are corresponding to a control code. The DAC produces an analog voltage according to the control code. An analog difference, between a first analog voltage corresponding to a first control code and a second analog voltage corresponding to a second control code, monotonically increases or monotonically decreases as a first value corresponding to the first control code increases. The first control code is consecutive to the second control code.

Abstract: A method for removing low frequency offset components from a digital data stream includes receiving, at an input of an analog-to-digital converter (ADC), an analog input signal from one or more analog front end components. The analog input signal has an associated low frequency offset due, at least in part, to the analog front end components. The method also includes generating, at an output of the ADC, a digital data stream representative of the analog input signal. The digital data stream having an associated low frequency offset due, at least in part, to the analog front end components and the ADC. One or more low pass finite impulse response (FIR) filters are applied to the digital data stream to detect the low frequency offset components in the digital data stream, and generate a filtered output signal with only the low frequency offset components present.

Abstract: Instability of an internal state in a current-input-type delta-sigma modulator is reduced in a case where input changes sharply. A signal current is input to a first integration node. A difference current between a fixed current and the signal current is input to a second integration node. A voltage-to-current converter that converts a difference voltage between the voltage of the first integration node and a first reference voltage into a current and outputs it is connected between the first integration node and the second integration node. The voltage of the second integration node is compared with a second reference voltage, and a 1-bit digital signal is output. Current is draws from the first integration node or the second integration node according to the 1-bit digital signal. A short-circuit switch is provided between the first integration node and the second integration node for short-circuiting them.

Abstract: An apparatus and a method for transmission system are disclosed. According to an embodiment, a voltage standing wave ratio (VSWR) detection apparatus, comprising: a signal processing circuit with 1-bit analog-to-digital converter (ADC) functionality configured to receive a forward coupled signal in a transmission line of an antenna system, receive a reverse coupled signal in the transmission line of the antenna system, detect the forward coupled signal and the reverse coupled signal, convert the forward detected signal and the reverse detected signal to an analog voltage signal mapped to a return loss value, convert by the 1-bit ADC the analog voltage signal into a digital pulse train and output the digital pulse train to a digital interface of a processing device or unit.

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract: A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.

Abstract: A system and method in an audio signal electrical circuit including a feedback loop with a digital filter coupled to a current digital to analog converter (IDAC) includes providing an output signal from the IDAC to analog elements of the audio signal electrical circuit, the output signal from the IDAC based upon a reference signal input to the IDAC when an output of the digital filter is not input to the IDAC. The system and method also include comparing an output signal of the audio signal electrical circuit to a reference, and calibrating the audio signal electrical circuit to correspond the output signal of the audio signal electrical circuit to the reference. Calibration of the audio signal electrical circuit enables more precise control of a cut-off frequency of a microphone signal when the output of the digital filter is input to the IDAC.

Abstract: A method for monitoring a power electronic assembly is improved to be more effective and versatile. It includes converting and/or modifying an electrical input into at least one electrical output by a conversion and/or modifying process which proceeds in connection with the power electronic assembly. During the conversion and/or modification a bit stream is generated by a delta-sigma modulator and represents the electrical value, that is to say the electrical input or the at least one electrical output. One bit stream each can also be generated by a plurality of delta-sigma modulators and represents the respective electrical value, that is to say the electrical input and the at least one electrical output. The power electronic assembly is monitored based on the one bit stream(s) thus generated and available as a result. The bit stream(s) is/are not demodulated, and therefore very meaningful information of the corresponding useful signal is provided.

Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

Abstract: Systems, apparatuses, and methods for implementing an anti-aliasing technique for a time-to-digital converter are described. A pulse generator generates a pulse with a width that is representative of a voltage level of a supply voltage. A buffer chain receives the pulse from the pulse generator. A first sum is calculated by adding together a number of one bits in a first portion of the buffer chain. Also, a second sum is calculated by adding together a number of one bits in a second portion of the buffer chain. Then, a third sum is calculated by adding the first sum to the second sum if the first sum is saturated. Otherwise, the third sum is equal to the first sum if the first sum is not saturated. The third sum is used as a representation of the voltage level of the supply voltage.

Abstract: A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.

Abstract: A second-order ?? modulator includes: a two-stage integrator; a first arithmetic operation circuit; and a second arithmetic operation circuit. The two-stage integrator includes a plurality of adder arrays, each of which includes a plurality of adders. The plurality of adder arrays includes first to fourth adder arrays. An output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array. An output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array. A sum bit string obtained in the first adder array is input to the third adder array. A sum bit string obtained in the second adder array is input to the fourth adder array.

Abstract: Techniques described herein are related to spread amplifier having a differential amplifier spread (DAS) configured to receive a pair of input signals and to provide a plurality of graded outputs each having different output levels. The spread amplifier further includes a final driver stage having a plurality of final drivers, wherein each of the final drivers is configured to receive a respective one of the plurality of graded outputs. The spread amplifier may be used for the regulation of various voltages such as VDQS and VARY.

Abstract: The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits is also lower than a number of significant bits allowing the second digital signal, or a signal derived therefrom to match an expected bit depth of a processing unit said second digital signal, or a signal derived therefrom is to be sent to.

Abstract: A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels.

Abstract: A circuit for correlated double sampling is disclosed. In one aspect, the circuit comprises a reset switch connected with an input node, and with a first node of a first capacitor; a sampling switch connected with the input node, and with a first node of a second capacitor; a second node of the first/second capacitor is adapted to be connected with a first/second reference node, of which at least one using a reference switch; a first switch connected between the second node of the first capacitor and the first node of the second capacitor; a second switch connected between the first node of the first capacitor and the second node of the second capacitor.

Abstract: A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device has a first input terminal and a second input terminal for receiving a received signal and an adjustable reference voltage respectively, and for generating an output signal at an output port. The first digital-slope quantizer is coupled to the output port and the second input terminal for generating a first set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer is coupled to the output port and the second input terminal for generating a second set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a second phase after the first phase according to a second quantization unit.

Abstract: An array of antennae includes a monobit transmitter to insert dither into a transmit signal to form a dithered transmit signal. Monobit receivers process received signals that are combined with the dithered transmit signal to form composite received signals. Digital down converters process the composite received signals to form down converted received signals. A beam former circuit processes the down converted received signals to form recovered signals.

Abstract: A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.

Abstract: A system includes an analog-to-digital converter (ADC) and a digital modulator coupled to the ADC, wherein the digital modulator comprises an output for providing a digital signal, wherein the digital modulator comprises a main signal path and a feedback path, and wherein the feedback path comprises a first digital gain stage having a first adjustable gain range.

Abstract: The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.

Abstract: A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

Abstract: An analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter configured to store a plurality of partial sums as respective entries in a plurality of lookup tables, retrieve at least one of the plurality of partial sums based on an output of the sigma-delta modulator, and calculate a filter output by adding retrieved ones of the plurality of partial sums together.

Abstract: Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches and/or errors. The mismatches and/or errors can degrade the quality of the analog output. To extract the mismatches and/or errors, a transparent dither can be used. The mismatches and/or errors can be extracted by observing the analog output, and performing a cross-correlation of the observed output with a switching bit stream of the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the respective mismatches and/or errors.

Abstract: A system, method, and non-transitory computer readable medium that detects trajectories of unmanned aerial vehicles (UAV) approaching a protected site is described. Airborne defense agents (ADAs) located at a fixed radius from the protected and equidistant from one another detect acoustic signals emitted by an approaching UAV. Circuitry included in each ADA use the detected acoustic signals to determine a direction and a distance of each UAV. A base station having a control center (BS-CC) located in the protected site communicates with the ADAs to aggregate direction and distance data from the ADAs. Using the aggregated direction and distance data, the BS-CC predicts routes towards the protected site of the approaching UAV and alerts the protected site of the predicted route of the approaching UAV.

Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Abstract: A signal compensation device is disclosed. The signal compensation device includes an operation circuit and a modulation circuit. The operation circuit is configured to generate a control signal according to a first data signal and a second data signal, in which the second data signal is generated according to the first data signal by a signal conversion circuit. The modulation circuit is configured to provide a loop gain according to the control signal to compensate an attenuation of the signal conversion circuit.

Abstract: A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between an analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.

Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.

Abstract: An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

Abstract: A system, method, and non-transitory computer readable medium that detects trajectories of unmanned aerial vehicles (UAV) approaching a protected site is described. Airborne defense agents (ADAs) located at a fixed radius from the protected and equidistant from one another detect acoustic signals emitted by an approaching UAV. Circuitry included in each ADA use the detected acoustic signals to determine a direction and a distance of each UAV. A base station having a control center (BS-CC) located in the protected site communicates with the ADAs to aggregate direction and distance data from the ADAs. Using the aggregated direction and distance data, the BS-CC predicts routes towards the protected site of the approaching UAV and alerts the protected site of the predicted route of the approaching UAV.

Abstract: A delta-sigma (?-?) modulator and method for reducing nonlinear error and gain error. The ?-?modulator includes: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle.

Abstract: An A/D conversion device, which operates in one mode including at least one of a ?? mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

Abstract: An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output subsystem (2) having at least one external connection (4). The external connection is configured to provide an input to or output from the device depending upon an associated setting in the general purpose input or output subsystem. At least one further module on the device is configured to be able to request at least a first or a second task which may control a state of the external connection, the general purpose input or output subsystem being configured, upon receipt of conflicting requests for the first and second tasks, to apply a predetermined priority to allow only one of the tasks to be applied to the external connection.

Abstract: Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

Abstract: A system for generating a control signal for a capacitive sensor includes a waveform generator configured to generate a digital waveform, a first sigma-delta modulator (SDM) configured to generate a first output corresponding to the control signal based on the digital waveform and first adjustment data and a second SDM configured to generate a second output corresponding to an offset signal based on the digital waveform and second adjustment data. The first SDM is configured to selectively adjust a phase and an amplitude of the control signal and the second SDM is configured to selectively adjust a phase and an amplitude of the offset signal.