Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Abstract: In accordance with systems and methods of the present disclosure, an input network for a delta-sigma modulator having at least one integrator stage and a feedback digital-to-analog stage, may be configured to, during a first period of a first phase of a clock signal, drive an analog feedback signal proportional to a digital feedback signal of the feedback digital-to-analog stage onto an input plate of a sampling capacitor integral to the input network. The input network may further be configured to, during a second period of the first phase of the clock signal, sample an analog input signal onto the input plates of the sampling capacitor.

Abstract: A delta-sigma modulator for a switching amplifier, which achieves a high signal-to-noise ratio (SNR) in the multi-MHz range and keeps the noise-transfer function over the useful frequency range as low and as flat as possible. A series connection of a parallel-serial converter and a downstream swap element for the serial output signal ya2 of the parallel serial converter is connected to the multi-bit output of the delta-sigma-modulator. The swap element swaps, based on the last bit value 0 or 1 of a preceding word in the resulting output signal ya3, the sequence of the binary zeroes and ones of the current word, where present, and then an input signal is fed to the delta-sigma-modulator. The signal is capable of having a frequency range above 25 kHz, and is prepared with a low oversampling ratio and a high SNR. And, 1-0 or 0-1 transitions are largely eliminated at the word boundaries.

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract: Circuitry for performing digital modulation is described. The circuitry includes a digital modulator. The digital modulator receives a first signal with a first duty cycle. The digital modulator also receives a second signal with a second duty cycle. The digital modulator further produces a monotonic multiplied modulated signal based on the first signal and the second signal.

Abstract: A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.

Abstract: The present invention provides a quantizer with a sigma-delta modulator, an analog-to-digital converter including the same and a quantization method using the same capable of obtaining a high signal-to-noise ratio with a relatively small number of comparators. The quantizer, the analog-to-digital converter and the quantization method of the present invention reduces quantization errors and increases noise shaping order.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g.

Abstract: An analog-to-digital converter (ADC) is described. This ADC converts an analog signal into a digital value using a two-pass digitization process. In a first operation, coarse digitization is performed by an averaging converter based on a set of references. Then, in a second operation, fine digitization is performed by either another averaging converter or the same averaging converter based on a subset of the set of references that is progressively closer to an instantaneous value of the analog signal. For example, the coarse digitization may be performed by a low-resolution ADC stage and the fine digitization may be performed by a sigma-delta ADC, such as a single-bit sigma-delta ADC. Moreover, the other averaging converter may use dynamic element matching to shuffle reference elements used to generate the subset. In this way, the ADC may provide high resolution with reduced nonlinearity and quantization noise.

Abstract: An encoding device, a decoding device, and related methods are provided that eliminate the loss of synchronization of the adaptive filters of a terminal at the encoding end and a terminal at the decoding end caused by transmission errors. Deterioration of the sound quality is suppressed when a multiple channel signal is encoded with high efficiency using an adaptive filter. In the terminal at the encoding end, a buffer stores updated filter coefficients. When packet loss detection information indicating whether there is any packet loss in the terminal at the decoding end indicates that there is packet loss, a switch outputs the past filter coefficients of the previous (NX+1) frames from the buffer to an adaptive filter. The adaptive filter uses the past filter coefficients of the previous (NX+1) frames to conduct filtering.

Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.

Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

Abstract: Systems and methods can detect a relationship between portions of an analog input signal using a single sensing point, and can provide information about the detected relationship in a digital signal. A system can include an input transconductance stage, a gate circuit driven by a first control signal, a phase-select multiplexer circuit driven by a second control signal, and multiple analog-to-digital converter (ADC) channels. The ADC channels can include respective integrator circuits that receive information from the phase-select multiplexer circuit, and the ADC channels can include comparator circuits coupled to respective outputs of the integrator circuits. The outputs of the comparator circuits can be used as control signals for respective feedback multiplexers, or respective feedback current DACs, that selectively couple reference currents to the respective integrator circuit inputs. The feedback current DACs can be configured to continuously provide information to the respective integrator circuits.

Abstract: A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

Abstract: A delta-sigma analog-to-digital converter includes: a summing stage having a first input for an input signal and a second input for a feedback signal; an integrator coupled to an output of the summing stage; an analog-to-digital conversion stage coupled to an output of the integrator; and a switchable gain stage coupled in a feedback path between an output of the analog-to-digital conversion stage and the second input of the summing stage. The switchable gain stage is arranged to switch, responsive to a gain selection signal, between a first gain and a second gain via a transition period comprising time periods during which the switchable gain stage has the first gain interleaved with time periods during which the switchable gain stage has the second gain.

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

Abstract: A charge distributor comprises a charge generator configured to output a charge, a current conveyor, and a plurality of output stages. The current conveyor is configured to receive the charge from the charge generator as an input and to couple this charge to a plurality of output stages. A first output stage, of the plurality of output stages, comprises a plurality of current mirrors. The plurality of current mirrors is configured to mirror and scale the charge received from the current conveyor into a scaled mirrored charge. The first output stage is configured to provide the scaled mirrored charge as an output.

Abstract: An apparatus and method for improving signal to noise ratio of a physiological signal is provided. At least one sensor senses the analog data signal, the analog data signal having a first component including ECG data and a second component including ancillary data. A converter is coupled to the at least one sensor that automatically converts the analog data signal into a digital data signal and decimates the digital data signal from a first sample rate to a second sample rate.

Abstract: A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308?) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310?) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.

Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.

Abstract: A delta-sigma modulator (1) for converting a delta-sigma modulator input signal into a sequence of delta-sigma modulator output values comprising an actual delta-sigma modulator output value and at least one preceding delta-sigma modulator output value preceding the actual delta-sigma modulator output value is presented. At least one feedback signal modifier for modifying a at least one first feedback signal in dependence of the actual delta-sigma modulator output value and the at least one preceding delta-sigma modulator output value is provided. By means of the at least one first feedback signal modifier the signal quality of a subsequent final stage (7) can be improved.

Abstract: An analog-to-digital converter includes an integrator to determine an integrated signal from a communication signal. A comparator quantizes the integrated signal to produce a quantized signal. An adjustable delay element provides a delayed quantized signal to the comparator.

Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

Abstract: A continuous-time delta sigma modulator, having an integrator and a comparator clocked with a clock frequency that are connected in a feedback loop, having a voltage source that is connected to the comparator for applying a threshold voltage to the comparator, in which an integration time constant of the integrator has a first resistor and a first capacitor, in which the voltage source has a second resistor and a second capacitor for setting the threshold voltage, in which the first resistor and the second resistor are part of a resistor pairing structure, and in which the first capacitor and the second capacitor are part of a capacitor pairing structure.

Abstract: A delta-sigma converter for a sensor signal is configured to emit a digital output signal using the sensor signal. The delta-sigma converter includes a control unit configured to generate a control signal on the basis of a frequency of signal level changes of the digital output signal. The delta-sigma converter further includes a digital compensation unit configured to emit a compensation signal using the digital output signal and the control signal. The delta-sigma converter is further configured to determine the digital output signal also using the compensation signal.

Abstract: A delta-sigma A/D converter includes a loop filter including a resonant filter, a quantizer, and a feedback D/A converter. The resonant filter includes a resonator including a resistor and a capacitor, and a feedback path through which an output of the resonator is positively fed back to an input of the resonator. The resonant filter operates as an oscillator or a filter under the on/off control of a first switch. At least one of the resistor and the capacitor of the resonator is configured to allow a resistance value or a capacitance value thereof to be adjusted based on a third external signal.

Abstract: Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.

Abstract: Operating capacitive sensors in force feedback mode has many benefits, such as improved bandwidth, and lower sensitivity to process and temperature variation. To overcome, the non-linearity of the voltage-to-force relation in capacitive feedback, a two-level feedback signal is often used. Therefore, a single-bit ?-? modulator represents a practical way to implement capacitive sensors interface circuits. However, high-Q parasitic modes that exist in high-Q sensors (operating in vacuum) cause a stability problem for the ?-? loop, and hence, limit the applicability of ?-? technique to such sensors. A solution is provided that allows stabilizing the ?-? loop, in the presence of high-Q parasitic modes. The solution is applicable to low or high order ?-? based interfaces for capacitive sensors.

Abstract: Representative implementations of devices and techniques provide a variable quantizer for a modulator. A compare value of the quantizer changes with each clock cycle of the modulator. The variable compare value results in a spread spectrum output of the modulator.

Abstract: Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal.

Abstract: A digital polar modulator (DPM) for transforming a baseband signal into a modulated digital modulator output signal comprises an input unit and two low-pass delta-sigma modulators, a first one being connected downstream from the first input part and configured to provide at its output a first pulse train in dependence on an amplitude- modulating baseband signal component, and a second one being connected downstream from the second input part and configured to provide at its output a multilevel quantized signal in dependence on a phase modulating baseband signal component; a multiphase generator, which is configured to provide a set of square-wave carrier signals having a common carrier frequency and exhibiting discrete phase shifts with respect to each other; a multiplexer, which is configured to provide a multiplexer output signal that is formed by switching, in dependence on a signal received at a select input as a function of time, between selected ones of the carrier signals; and a combiner unit.

Abstract: Embodiments of the present invention may include an apparatus and method to reduce an output swing in each stage of a multi-stage loop filter while also maintaining a desired signal transfer function for each respective stage. A given stage of the loop filter may include an integrator, a feedback path, a first cancellation path, and a second cancellation path. The first cancellation path may be coupled to the output of the integrator. The second cancellation path may be coupled to a feedback path provided about the input and output of the integrator. A first cancellation signal may be injected into the first cancellation path to reduce the output swing of the integrator. A second cancellation signal may be injected into the second cancellation path to minimize a change in the integrator's signal transfer function caused by the first cancellation signal.

Abstract: DEM circuit (130) includes a switch (131) configured to receive an N-bit digital input signal (SD1) and shift bit positions of the digital input signal (SD1) based on a switch control signal (SC) in a circulating pattern to output the digital input signal (SD1) as an N-bit digital output signal (SD2), where N is an integer greater than or equal to 2, and a switch control signal generation circuit (132) including a plurality of pointers which move in an identical direction based on a predetermined rule, and configured to generate the switch control signal (SC), each time when the digital input signal (SD1) is input to the switch (131), by using the pointers in a predetermined order.

Abstract: A method may include measuring a frequency difference between an actual frequency and an expected frequency associated with a frequency control calibration signal value for each of a plurality of frequency control calibration signal values during a calibration phase. The method may additionally include generating integral non-linearity compensation values based on the frequency differences measured The method may further include generating the applied frequency control signal based on a frequency control calibration signal value received by the digital-to-analog converter during the calibration phase. The method may also include generating a compensated frequency control signal value based on a frequency control signal value received by the integral non-linearity compensation module and an integral non-linearity compensation value associated with the frequency control signal value during an operation phase of the wireless communication element.

Abstract: One or more techniques for buffer offset modulation or buffer offset cancelling are provided herein. In an embodiment, an output for a sigma-delta analog digital converter (ADC) is provided using an output of a first chop-able buffer (FB) and an output of a second chop-able buffer (SB). For example, the output of the FB is associated with a first offset, the output of the SB is associated with a second offset, and the output of the ADC includes an ADC offset associated with the first offset and the second offset. In an embodiment, buffer offset modulation is provided by modulating the ADC offset using an offset rotation. In an example, the offset rotation is based at least in part on a reference clock and the output of the ADC. The buffer offset modulation mitigates the first offset or the second offset, where such offsets are generally undesired.

Abstract: A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop.

Abstract: Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.

Abstract: Measurement circuits having a delta-sigma modulator are disclosed. One example measurement circuit includes a low pass filter coupled to receive an input voltage, a switched-capacitor integrator circuit, and a switched comparator circuit. The measurement circuit may generate a digital output made up of a sequence of logic high and logic low levels that are representative of a scaled value of the input voltage output by the low pass filter circuit. Also, by virtue of its switched-capacitor configuration, the electric charge received by the switched difference amplifier circuit may be returned to the input in a manner such that the input to the delta-sigma modulator takes little to no average current from the voltage it measures. In other words, the delta-sigma modulator may have a high input impedance by virtue of its switched-capacitor circuit configuration.

Abstract: Embodiments of the invention provide a pulseoximetry system with ambient offset cancellation that subtracts an estimated ambient offset to thereby allow a large front end gain while operating the front end on a low supply voltage. This large gain reduces input referred noise of an analog to digital converter in the front end while providing high dynamic range for signals with a large ambient offset.

Abstract: A continuous-time ??-ADC (1) is disclosed, comprising a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ??-ADC (1) at sample instants nT. The ??-ADC (1) further comprises two or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5), and a continuous-time analog network (20) arranged to generate an analog input signal to the quantizer (5) based on the feedback signal(s) from the two or more DACs (10a-b) and an analog input signal to the ??-ADC (1). At least a first DAC (10a) of the two or more DACs (10a-b) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+a1)T and (?+?1)T, wherein 0<?1<?1<1.

Abstract: The stability of a delta-sigma modulator may be improved by limiting a value within the delta-sigma modulator. For example, the value provided to a quantizer may be limited, by a limiter circuit in the delta-sigma modulator, to a value within a single step range of the quantizer. The limiter circuit may be placed in an inner loop of the delta-sigma modulator to decouple the stability of the inner loop from an outer loop. For example, a delta-sigma modulator may be constructed with an inner loop having a sixth order and an outer loop having a second order, in which the stability of the delta-sigma modulator is proportional to that of a second order.

Abstract: The invention comprises sample-and-hold circuit and digital-to-analog converter into a differentially operational unit. In analog-to-digital conversion unit, on the premise of fixed or non-fixed quantization error, analog-to-digital converter dynamically adjusts number of bits solved or size of quantized step according to the magnitude of differential voltage between sampled input signal and previously quantized input signal, thus this invention can reduce the non-necessary power consumption from redundant code and overload of input signal. Differentially operational unit and analog-to-digital unit share the same capacitor array which has binary-weighted arrangement to reduce circuit complexity and area.

Abstract: A sigma-delta analog-to-digital converter includes an input transconductance stage that provides an analog input current proportional to an analog input voltage and a current summing stage that generates an analog error signal corresponding to a difference between the analog input current and a feedback current. The sigma-delta analog-to-digital converter also includes a forward signal path that processes the analog error signal to provide a digital output signal corresponding to the analog input voltage. Additionally, the sigma-delta analog-to-digital converter includes a feedback path that includes a current steering digital-to-analog converter having both sourcing and sinking current sources, wherein currents provided by the sourcing and sinking current sources are steerable and connected to directly provide the feedback current based on the digital output signal. A sigma-delta analog-to-digital converter operating method is also provided.

Abstract: A delta-sigma A/D converter includes a loop filter including a resonant filter, a quantizer, and a feedback D/A converter. The resonant filter includes a resonator including a resistor and a capacitor, and a feedback path through which an output of the resonator is positively fed back to an input of the resonator. The resonant filter operates as an oscillator or a filter under the on/off control of a first switch. At least one of the resistor and the capacitor of the resonator is configured to allow a resistance value or a capacitance value thereof to be adjusted based on a third external signal.

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of analog inputs. A multistage comparator using a feed-forward technique can provide noise shaping of conversion errors. For example, the comparator may feed a conversion error forward from a first stage to a next stage of the multistage comparator.

Abstract: An isolated current-sensing system for use with a resistive current sense element includes an analog front-end configured to receive a voltage from the resistive current sense element, and to provide an analog output. A processing circuit receives the analog output, and provides a measurement signal indicative of the sensed current. An isolation circuit provides an isolation barrier, and is configured to pass the measurement signal. A programmable over-current protection alarm may be included, and configured to generate an alarm signal when the analog output exceeds a programmable threshold. The processing circuit may include a voltage-to-PWM converter.

Abstract: A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.