Abstract: A driver circuit for programmable solid state light bulb assemblies including light emitting diodes is operable to provide a drive current to a light source of the light bulb assembly. The controller comprises a data storage unit storing a test scenario for calibration of the light bulb assembly; wherein the test scenario indicates a sequence of states of the light source; wherein a state of the light source is associated with settings of the driver circuit; a data input unit receiving a command signal via a modulated electricity supply signal; and a data processing unit retrieving the test scenario from the data storage unit; in dependence of the received command signal, generating a control signal for operating the light source in at least one state of the sequence of states of the test scenario; and to output the control signal.

Abstract: An electronic analog-to-digital conversion device includes an analog-to-digital conversion block having a first input for receiving a voltage signal to be converted based on a reference voltage signal provided to a second input, and an input block connected to the first input of the analog-to-digital conversion block. The input block receives an input signal at a first resistive network connected to a second resistive network, which is then connected to a reference potential. The input block also includes an active network connected between an output of the first resistive network and the first input of the analog-to-digital conversion block. The active network has a first input terminal directly connected to the second input of the analog-to-digital conversion block for receiving the same reference voltage signal so that the input voltage signal received at a second input of the active network is processed based on the reference voltage signal.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. Each of the processing branches includes a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit.

Abstract: An analog-to-digital conversion system includes a track-and-hold unit configured to output an input value; a digital-to-analog (D/A) conversion unit configured to generate a feedback value; a coupling unit configured to generate an error signal value based on the input signal and the feedback value; a loop filter configured to generated a filtered error signal value; a comparison unit configured to generate a comparison result based on the input value minus the summation of the feedback value and the filtered error signal value; and a control unit. The control unit is configured to, during a sampling cycle, set an N-bit logical value accordingly to N comparison results; and to cause the coupling unit to generate the error signal value. N is a positive integer.

Abstract: In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes an input current buffer circuit, a signal charge integration node, a dual function comparator, a step charge subtractor, a state latch, a coarse N-bit counter, an optional residue signal buffer and a residue signal M-bit time-to-digital (TDC) converter. The circuitry is free running, meaning that it is never reset. Instead, what is tracked for each frame is how much additional charge has been accumulated since the end of the previous integration period. Between each frame, the state of the counter and the amount of charge residing in the integration node are recorded. This information from the beginning and end of a given frame is differenced and to this is added the amount of charge indicated by the number of times the counter overflowed during the integration period.

Abstract: An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal.

Abstract: A method and apparatus for a feed-forward delta-sigma modulator are provided. The apparatus includes a first adder configured to receive a feedback signal and an input signal and a first integrator configured to receive an output from the first adder. The apparatus also includes a noise-coupled summer/integrator (NCSI). The NCSI includes a second adder configured to receive a differentiation path from the first integrator, an output from the first integrator, and a delayed feedback path from the output of a second integrator. The NCSI also includes the second integrator configured to receive an output from the second adder. The apparatus also includes a quantizer configured to receive the output of the second integrator, feed back the output to the first adder and the NCSI and produce the output from the feed-forward delta-sigma modulator.

Abstract: A transcoder is arranged to transcode a stream having a dynamically changing audio configuration, such as a changing number of audio channels. The transcoder can receive an input stream whereby changes in the content associated with the input stream causes corresponding changes to the configuration of audio data encoded in the input stream. The transcoder is arranged to detect the change in audio configuration and, in response, to dynamically reconfigure its decoder and encoder modules to continue to transcode the audio data after the audio configuration change.

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (??) modulator is provided at the front-end of the MASH ADC, and another full ?? modulator is provided at the back-end of the MASH ADC. The front-end ?? modulator digitizes an analog input signal, and the back-end ?? modulator digitizes an error between the output of the front-end ?? modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Abstract: An information handling system includes a host including a central processing unit, a first management controller (MC) enabled to communicate with the host, and a network interface resource (NIR) in communication with the host and operable to enable the information handling system to communicate via an external network. The NIR includes a unified management module (UMM) operable to receive and route a local management packet, sent from the host, to the first management controller via a first unified management bus (UMB) and further operable to receive and route a remote management packet, sent from a remote resource via the external network, to the first management controller via the first UMB.

Abstract: A method and device of channel equalization and beam controlling for a digital speaker array system includes (1) converting digital format; (2) performing channel equalization; (3) controlling beam-forming; (4) performing multi-bit ?-? modulation; (5) performing thermometer code conversion; (6) performing dynamic mismatch-shaping processing; and (7) extracting the channel information to send to the digital power amplifier and drive the array sound. A device includes a sound source, a digital converter, a channel equalizer, a beam-former, a ?-? modulator, a thermometer coder, a dynamic mismatch shaper, an extraction selector, a multi-channel digital power amplifier and a speaker array. Each unit connects to each other serially.

Abstract: An analog to digital convertor (ADC) comprises an integrator having an input selectively connected to an intermediate frequency (IF) signal input and an output connected to a summer. The summer has an output connected to an input of a quantizer, the quantizer output being operatively connected to a signal strength indicator. The integrator includes a programmable gain feedback component. The summer has a synthesized calibration signal input, the value of the programmable gain feedback component being configured to vary when a synthesized calibration signal at the intermediate frequency is applied to the summer. The signal strength indicator is configured to detect a value of the programmable gain feedback component when the signal strength is minimized and to calibrate the ADC accordingly.

Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: An innovative analog circuit design using digital components is disclosed. Embodiments of the present invention includes, but not limited to analog amplifiers and comparators. An amplifier of an embodiment of the present invention includes an inverter, a plurality of switches, offset capacitor and flying capacitor. The one terminal of the offset capacitor is connected to the input of the inverter. During setup phase of clock signals, the switches are configured to connect input and output of the inverter and to connect the flying capacitor to input terminals of the amplifier, respectively, for storing a differential input voltage. Then, during the enable phase of the clock signals, the switches are configured to connect the first terminal of the second capacitor and the first terminal of the first capacitor, and to connect the second terminal of the second capacitor to the output of the inverter.

Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.

Abstract: The present disclosure is directed towards a sensor interface module that delivers a supply voltage to a plurality of sensors, and which exchanges data signals between the plurality of sensors and a control unit (e.g., an ECU). The sensor interface often employs a single-bit comparator (or a coarse analog to digital converter (ADC), e.g., a 2-bit or 3-bit ADC) to track signals to be exchanged between the sensors and controller over the sensor interface. Compared to power hungry ADC with more bits (e.g., 32 bit ADC), the single-bit comparator/coarse ADC limits hardware complexity and power consumption. In addition, in some embodiments the sensor interface module can include an estimator and assist comparators to speed up the tracking ability of the sensor interface module. In this way, techniques provided herein facilitate reliable, low-power communication between a control unit (e.g., an ECU) and its corresponding sensors.

Abstract: A single-ended receiver compares signal levels representing current symbols to levels representing immediately preceding symbols to resolve the symbols. The receiver applies offsets selected based on resolved prior symbols to interpret successive like-symbols.

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract: A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308?) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310?) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: A circuit includes a first digital filter H(z), a second digital filler 1 1 + H ? ( z ) , a third digital filter, a first and a second digital modulators, and a gain block. The first digital filter generates a first output based on a digital input and a first digital output signal. The first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. The gain block amplifies the first error output by a predetermined ratio, thereby generating a second error output. The second digital modulator generates a second output and a third error output based on the second error output. The second digital filter generates a second digital output signal based on the second output. The third filter generates the feedback error output based on the third error output.

Abstract: Methods, systems and devices are disclosed, such as an electronic device that includes a plurality of data locations and a delta-sigma modulator. In some embodiments, the delta-sigma modulator includes a preamplifier coupled to the data locations and a latch coupled to the preamplifier.

Abstract: Provided herein are processes for preparing an isoindoline-1,3-dione compound, or an enantiomer or a mixture of enantiomers thereof; or a pharmaceutically acceptable salt, solvate, hydrate, or polymorph thereof.

Abstract: Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The continuous-time quantization-noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

Abstract: Continuous time analog/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analog input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

Abstract: A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

Abstract: An apparatus generally relating to a receiver is disclosed. In this apparatus, the receiver includes a phase interpolator, a detector and a slicer. The slicer is coupled to the phase interpolator to provide a sampling signal for a sampling position of the phase interpolator. The detector is coupled to the slicer to receive the sampling signal. The detector is configured to adjust a code of the phase interpolator to adjust the sampling position iteratively in response to the sampling signal to tune the sampling position of the receiver toward an optimum therefor.

Abstract: A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.

Abstract: Measurement circuits having a delta-sigma modulator are disclosed. One example measurement circuit includes a low pass filter coupled to receive an input voltage, a switched-capacitor integrator circuit, and a switched comparator circuit. The measurement circuit may generate a digital output made up of a sequence of logic high and logic low levels that are representative of a scaled value of the input voltage output by the low pass filter circuit. Also, by virtue of its switched-capacitor configuration, the electric charge received by the switched difference amplifier circuit may be returned to the input in a manner such that the input to the delta-sigma modulator takes little to no average current from the voltage it measures. In other words, the delta-sigma modulator may have a high input impedance by virtue of its switched-capacitor circuit configuration.

Abstract: A continuous-time ??-ADC (1) is disclosed, comprising a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ??-ADC (1) at sample instants nT. The ??-ADC (1) further comprises two or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5), and a continuous-time analog network (20) arranged to generate an analog input signal to the quantizer (5) based on the feedback signal(s) from the two or more DACs (10a-b) and an analog input signal to the ??-ADC (1). At least a first DAC (10a) of the two or more DACs (10a-b) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+a1)T and (?+?1)T, wherein 0<?1<?1<1.

Abstract: An audio amplifier including (i) a mode controller configured to generate a control signal, and (ii) a variable-length finite impulse response (FIR) filter. The variable-length FIR filter includes (i) a first fixed-length FIR filter configured to generate a first filtered signal based on a first digital audio signal, and (ii) a second fixed-length FIR filter configured to generate a second filtered signal based on the first digital audio signal. The variable-length FIR filter also includes an output module configured to (i) select one of the first filtered signal or the second filtered signal based on the control signal, and (ii) provide the selected one of the first filtered signal or the second filtered signal as an output signal. The audio amplifier also includes an analog module configured to generate an amplified analog signal based on the output signal.

Abstract: A light-emitting control circuit, a light-emitting control method and a shift register. The light-emitting control circuit comprises an inputting terminal (Input), an input sampling unit (11), an outputting unit (12), a resetting unit (13), an output pulling-down unit (14) and an outputting terminal for a light-emitting control signal (EM[n]). The input sampling unit (11) samples an input signal under a control of a first clock signal (CK1); the outputting unit (12) generates a light-emitting control signal under a control of a second clock signal (CK2) after the input sampling unit (11) samples the input signal; the resetting unit (13) resets the light-emitting control signal through the output pulling-down unit (14) under a control of a third clock signal (13).

Abstract: The present disclosure provides methods and circuits for compensating reference shifting error. A compensation reference voltage is applied to an error compensation circuit, which is coupled to a multiplying circuit. A compensation parasitic capacitance is induced in the error compensation circuit. The compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.

Abstract: Embodiments of the present invention are directed to an analog to digital converter, comprising a comparator for comparing an analog input signal and an analog feedback signal output from a digital to analog converter to generate a digital direct output signal, a summer, coupled to the comparator, for summing the digital output signal with a digital feedback signal to generate a summed signal, a first integrator, coupled to the summer, for integrating the summed signal to generate a direct output signal and a second integrator, coupled to the first integrator and to the summer, for integrating the direct output signal to generate the digital feedback signal as a quadrature output signal.

Abstract: A programmable intellectual property block includes a PWM processor core to perform audio processing on input audio signals with firmware-driven modules to generate PWM output samples without using digital-analog converters or application processors. PWM processor core directly writes PWM output samples to queues of PWM peripherals to generate and transmit PWM digital pulses used by power stage(s) to drive electroacoustic transducers. Audio processing module(s) and PWM processing module(s) are implemented as a part of the firmware stored on the programmable processor core and are co-optimized by accessing the firmware. PWM processor core is dynamically configurable by identifying appropriate modules or information from the firmware based at least in part upon optimization objectives.

Abstract: A continuous time delta sigma modulator includes a quantizer and a reference module. The quantizer includes: a first comparator that generates a first digital output based on a comparison of a first reference potential with an input generated based on a sample of an analog signal; and a second comparator that generates a second digital output based on a comparison of a second reference potential with the input generated based on the sample of the analog signal. The reference module varies the first and second reference potentials based on the first and second digital outputs.

Abstract: Analog-to-digital converter arrangements and corresponding methods are provided, wherein a reduction signal is subtracted from an analog input signal if a signal level of the input signal exceeds a threshold value.

Abstract: A method for converting a capacitance of a precision capacitor for measurement into a digital signal is described. According to a clocking in charging processes an integration capacitor, discharged before the start of conversion, of an integrator circuit is charged by electric current obtained from a charging of the precision capacitor and in discharge processes by brief current surges in the opposite direction which are obtained from a charging of a reference capacitor, with the result that on average no charge builds up, and the number of discharge processes in a particular number of clock pulses is counted. The clocking is paused after a predetermined number of cycles. A residual voltage is converted into a digital value and the counted number of discharge processes and the particular number of clock pulses are combined with the digital value emitted by the analog-to-digital voltage converter to form a digital total result.

Abstract: A continuous wave Light Detection and Ranging (CW LiDAR) system utilizes two or more laser frequencies and time or range shifted pseudorandom noise (PN) codes to discriminate between the laser frequencies. The performance of these codes can be improved by subtracting out the bias before processing. The CW LiDAR system may be mounted to an artificial satellite orbiting the earth, and the relative strength of the return signal for each frequency can be utilized to determine the concentration of selected gases or other substances in the atmosphere.

Abstract: A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each asynchronous sample is generated.

Abstract: A device that performs Quantization Noise-Shaping and operates at high clock rates. The device can be implemented in parallel with large parallelization factors to produce extremely high throughput. The device has two feed-forward filters that can be implemented using standard parallel Digital Signal Processing techniques. The device can be used in various systems such as Digital-to-Analog Converter (DAC) system and Fractional-N frequency synthesis systems.

Abstract: A continuous-time MASH sigma-delta analogue-to-digital converter ADC. The ADC may include first and second modulators and an output stage. The ADC may be provided with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract: Method and apparatus for providing a data stream generator that generates a data stream associated with a monitored analyte level, and a radio frequency logic portion operatively coupled to the data stream generator, the radio frequency logic portion configured to generate a radio frequency data stream based on the data stream generated from the data stream generator, the radio frequency logic portion further including one or more finite state machines and a plurality of discrete digital logic circuits, the one or more finite state machines configured to control the plurality of digital logic circuits to generate the radio frequency data stream for wireless communication are provided. Systems and kits incorporating the same are also provided.

Abstract: A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler's number as the base, and in a further phase has a profile of a falling exponential function with Euler's number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.

Abstract: In one embodiment, a method and system includes: synchronizing the timing of the change of a clock frequency based on the state of an output subsystem for driving an output transducer.

Abstract: A data converter is disclosed. The data converter includes a loop-filter, a quantizer, an analog dynamic element matching (DEM) shuffler, a digital DEM shuffler and a feedback digital-to-analog converter. The loop-filter receives analog signals from an analog input. The quantizer then converts the filtered analog signals from the loop-filter to digital signals at a digital output. The analog DEM shuffler shuffles a set of analog threshold levels of the quantizer to yield a set of partially shuffled digital data at an output of the quantizer. The digital DEM shuffler shuffles the set of partially shuffled digital data from the output of the quantizer to yield a set of shuffled digital data. The feedback digital-to-analog converter converts the set of shuffled digital data to a set of analog data to be fed back to the loop-filter.

Abstract: The frequency characteristic of a controller is acquired. The gain characteristic and phase characteristic of a controlled system are acquired. The open-loop transfer characteristic of the control system and the variation range of the open-loop transfer characteristic are computed from a variation range of the frequency characteristic of the controlled system and the frequency characteristic of the controller, and the variation range of the frequency characteristic of the controlled system is a region where a variation range of the gain characteristic and a variation range of the phase characteristic overlap in a complex coordinate system. The stability of the control system is estimated from the open-loop transfer characteristic and the variation range of the open-loop transfer characteristic.

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ?? modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.