Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of capacitors, a first input for a clock signal, a second input for a phase shifted clock signal, a reference input for a reference signal, and an output. The phase interpolator is configured to provide at its output an interpolated, modulated phase information signal by switching, dependent on a modulation information, a first number of the capacitors between the first input and the output, a second number of the capacitors between the second input and the output, and a third number of the capacitors to the reference input.

Abstract: An input signal is quantized by a quantizer after being passed through plural loop filters. A last-stage loop filter is formed of an operational amplifier for generating an output signal, a sampling capacitor for sampling the input signal, an integrating capacitor for integrating the signal sampled by the capacitor and plural switches for switching over signal paths. A control circuit controls on/off states of the switches to discharge the sampling capacitor and the integrating capacitor and causes the loop filter to repeat a sampling operation and an integrating operation plural times. The control circuit lastly connects the sampling capacitor and the integrating capacitor to a state, which is opposite to the state of the integrating operation time and turns on a converting switch so that the A/D converter A/D-converts the output signal of the loop filter.

Abstract: A delta-sigma modulator is configured to feedback an output signal of a quantizer to an input of an integrator, and also feedback to the input of the integrator a differentiated error signal representing derivative of quantization error caused by the quantizer.

Abstract: Systems and methods can detect a relationship between portions of an analog input signal using a single sensing point, and can provide information about the detected relationship in a digital signal. A system can include an input transconductance stage, a gate circuit driven by a first control signal, a phase-select multiplexer circuit driven by a second control signal, and multiple analog-to-digital converter (ADC) channels. The ADC channels can include respective integrator circuits that receive information from the phase-select multiplexer circuit, and the ADC channels can include comparator circuits coupled to respective outputs of the integrator circuits. The outputs of the comparator circuits can be used as control signals for respective feedback multiplexers, or respective feedback current DACs, that selectively couple reference currents to the respective integrator circuit inputs. The feedback current DACs can be configured to continuously provide information to the respective integrator circuits.

Abstract: Systems and methods for recognizing human gestures are disclosed. In one embodiment, a method for recognizing a gesture made by an operator with a portable device, may comprise: obtaining a first sensor data profile associated with measurements made by the first sensor while the operator made a specific gesture involving the portable device; obtaining a second sensor data profile associated with measurements made by the second sensor while the operator made the specific gesture involving the portable device; and identifying the specific gesture by analyzing the first sensor data profile and the second sensor data profile.

Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may comprise input terminals, a bitstream encoding circuit, a self-synchronizing encoding circuit and a transmitter. The second semiconductor die may comprise a receiver, a self-synchronizing decoder, a bitstream decoding circuit and an optional digital filter. The bitstream encoding and decoding may enable a plurality of signals to be encoded and transmitted through an isolation material.

Abstract: A digital-to-analog converter apparatus includes a digital-to-analog converter, a resistor-capacitor circuit, a quantizer and a controller. The resistor-capacitor circuit includes an operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a first switch and a second switch. The digital-to-analog converter may generate a plurality of currents. The quantizer may generate a plurality of offset values. The controller may control coupling of the plurality of currents to the operational amplifier.

Abstract: In a speech encoder/decoder a pitch delay contour endpoint modifier is employed to shift the endpoints of a pitch delay interpolation curve up or down. Particularly, the endpoints of the pitch delay interpolation curve are shifted based on a variation and/or a standard deviation in pitch delay.

Abstract: A method may include: determining a signal strength of a signal in a receive path of a wireless communication element, the receive path configured to receive a wireless communication signal and convert the wireless communication signal into a digital signal based at least on an oscillator signal; selecting a current mode from at least one of a first current mode and a second current mode for the wireless communication element based at least on the signal strength; communicating a control signal to the receive path indicative of the current mode; modifying one or more operational parameters of the receive path such that the receive path consumes a different amount of current in each of the current modes.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Abstract: An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes shaping quantization noise in response to: a signal-to-noise ratio of the analog input signal; and a power of the converter.

Abstract: An active feedback control integrated circuit applied to an alternating current/direct current converter includes a feedback pin, an operation unit, a control unit, and a controlled-current generation unit. The feedback pin is used for receiving a feedback current of an output feedback unit of the alternating current/direct current converter. The operation unit is used for generating an operation signal according to the feedback current. The control unit is coupled to the operation unit for generating a current control signal. The controlled-current generation unit is coupled to the control unit for generating a controlled current to the feedback pin according to the current control signal.

Abstract: An analog to digital converter comprises an input terminal configured to receive an analog input signal and an output terminal configured to provide an output digital signal.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.

Abstract: Transport of differential signals is provided. In one aspect, a telecommunications system includes a first unit and a second unit. The first unit can calculate a differential signal from an original signal. The differential signal can represent a change in signal levels between constant time intervals in the original signal. The second unit can estimate the original signal from the differential signal received from the first unit over a communication medium.

Abstract: According to an embodiment, an analog-to-digital converter includes a first AD (analog-to-digital) conversion circuit and a second AD conversion circuit. The first AD conversion circuit performs AD conversion of a first input signal to generate an upper-bit digital signal. The second AD conversion circuit performs AD conversion of a sampled signal to generate a lower-bit digital signal. The sampled signal is obtained by sampling a residual signal corresponding to a residue of the AD conversion in the first AD conversion circuit. A period during which the second AD conversion circuit performs AD conversion of the sampled signal overlaps a period during which a second input signal subsequent to the first input signal is settled.

Abstract: A modulator and a method are disclosed. The modulator is for generating a band pass signal and comprises: sigma delta modulation logic operable to receive an input signal and to perform at least a 3-level quantisation of the input signal to generate an at least 3-level quantised signal; and requantisation logic operable to requantise the at least 3-level quantised signal to a 2-level quantised signal to be provided as the band pass signal. This approach improves the coding efficiency achieved compared to that possible using a 2-level sigma delta modulator, whilst also providing improved noise performance due to the inherent linearity of the 2-level quantised signal which is provided to drive the switch mode power amplifier. Accordingly, the performance of the modulator is improved by increasing its coding efficiency whilst maintaining its linearity which improves the noise performance in adjacent channels.

Abstract: A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.

Abstract: A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: Provided is a switched-capacitor integrator, a method of operating the switched-capacitor integrator, and apparatuses including the switched-capacitor integrator. The switched-capacitor integrator including an amplifier including a first input terminal, a second input terminal, and an output terminal, a first capacitor disposed between the first input terminal and the output terminal, and a switched capacitor circuit configured to sample an input signal in response to control signals, and to integrate a difference between a feedback signal and the input signal while sampling the input signal.

Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Abstract: A selector selects an analog audio signal input to one input port from among analog audio signals input to multiple input ports according to an instruction from the user. An analog gain control circuit amplifies the analog audio signal received from the selector, with a corresponding one of the gains set for the respective input ports. An analog gain control circuit is configured to gradually change its gain when the gain is switched. An A/D converter converts an output signal of the analog gain control circuit into a digital audio signal. A first audio signal processing circuit is monolithically integrated on a signal semiconductor substrate.

Abstract: A continuous-time delta sigma modulator, having an integrator and a comparator clocked with a clock frequency that are connected in a feedback loop, having a voltage source that is connected to the comparator for applying a threshold voltage to the comparator, in which an integration time constant of the integrator has a first resistor and a first capacitor, in which the voltage source has a second resistor and a second capacitor for setting the threshold voltage, in which the first resistor and the second resistor are part of a resistor pairing structure, and in which the first capacitor and the second capacitor are part of a capacitor pairing structure.

Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.

Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (??) modulator is provided at the front-end of the MASH ADC, and another full ?? modulator is provided at the back-end of the MASH ADC. The front-end ?? modulator digitizes an analog input signal, and the back-end ?? modulator digitizes an error between the output of the front-end ?? modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract: An analog to digital converter is disclosed herein. The analog to digital converter includes a bit conversion module and a control module. The bit conversion module is configured to generate a quantization output in accordance with an input signal. The control module is configured to control the bit conversion module, so as to make the bit conversion module operate in one of a sigma delta mode and a successive approximation mode.

Abstract: A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

Abstract: A sigma-delta converter may include an input node, a switched capacitor input stage integrating a difference signal between an input signal from the input node and a feedback signal representing an output signal, and a switched capacitor adder coupled downstream from the switched capacitor input stage and generating a sum signal based upon the input signal with a signal generated by the switched capacitor input stage. The sigma-delta converter may include a switched capacitor output stage amplifying the sum signal and generating an analog amplified signal, a quantization stage coupled in cascade to the switched capacitor output stage and generating the output signal as a digital replica of the analog amplified signal, and a circuit generating the feedback signal as an analog replica of the output signal.

Abstract: The present invention relates to a delta-sigma-modulator and a delta-sigma-A/D converter. By speeding up the settling time constant of an integrator at the last stage with a simple configuration, the sampling frequency is sped up in the delta-sigma-modulator as a whole. Specifically, in the delta-sigma-modulator including multiple integrators connected in cascade, the integrator positioned at the last stage is a passive integrator not using an amplifier circuit, and one or more integrators positioned at stages preceding the last stage by one or more stages are active SC integrators using amplifier circuits and switched capacitor circuits, respectively. Also, each of the integrators performs integral calculation by alternately repeating a first operation phase to charge a sampling capacitor by sampling an input signal, and a second operation phase to perform a summing integration by transferring an electric charge charged in the sampling capacitor to an integration capacitor.

Abstract: A delta-sigma modulator and corresponding method are disclosed. In one implementation, the delta-sigma modulator includes a multiplexer for receiving an analog input signal and a common mode signal and outputting a multiplexed signal in accordance with a selection signal; a summing circuit for receiving the multiplexed signal and an analog feedback signal and outputting an error signal; a loop filter for receiving the error signal and outputting a filtered signal; a quantizer for receiving the filtered signal and outputting a raw digital output signal; a digital-to-analog converter for receiving the raw digital output signal and outputting the analog feedback signal along with a rotated digital output signal in accordance with a phase indicator and a rotation number; and a calibration logic for receiving the rotated digital output signal and a mode indicator and outputting the selection signal, the phase indicator, the rotation number, and a calibrated digital output signal.

Abstract: A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.

Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; and a resistance component, coupling the gate of the first transistor to a bias voltage level.

Abstract: A Power Line Communication (PLC) device that is resilient to cross-band interference. The PLC device is configured to communicate on AC power wiring in the frequency range of 9 kilohertz to 500 kilohertz and does not use automatic gain control prior to analog-to-digital conversion. The PLC device includes an over-sampled analog-to-digital converter with a sample clock of at least 10 megahertz and includes a loop filter that maintains a noise power spectral density that does not exceed three decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above, and a digital filter and decimator configured to remove quantization noise, where a decimation factor of the decimator is such that it provides an output decimation rate between 350 kilohertz and 1.6 megahertz.

Abstract: A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.

Abstract: An analogue to digital converter comprises an input terminal configured to receive an analogue input signal and an output terminal configured to provide an output digital signal.

Abstract: An arrangement for reading out an analog voltage input signal includes an input applying the input signal thereto, and a reference unit generating an analog reference voltage. To perform online self-calibration, the arrangement includes a superposition unit generating a combined analog signal by superimposing the analog reference voltage onto the input signal, a converting unit converting the combined analog signal into a one-bit serial data stream at a conversion sampling rate, and a decomposition unit, which includes at least two digital filters configured to generate from the serial data stream two corresponding digital signals at different data rates, which can be less than the conversion sampling rate.

Abstract: Provided is an apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, which includes an input line for accepting an input signal, multiple processing branches coupled to the input line, and an adder coupled to outputs of the plurality of processing branches. Each of the processing branches includes a sampling/quantization circuit and a digital bandpass interpolation filter having an input coupled to an output of the sampling/quantization circuit. The digital bandpass interpolation filters in different ones of the processing branches have frequency responses that are centered at different frequencies. The digital bandpass interpolation filter in at least one of the processing branches includes: (i) a quadrature downconverter, (ii) a first lowpass filter and a second lowpass filter, (iii) a first interpolator and a second interpolator, each having an input for inputting a variable interpolant value, and (iv) a quadrature upconverter.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. Each of the processing branches includes a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit.

Abstract: A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

Abstract: An input signal is quantized by a quantizer after being passed through plural loop filters. A last-stage loop filter is formed of an operational amplifier for generating an output signal, a sampling capacitor for sampling the input signal, an integrating capacitor for integrating the signal sampled by the capacitor and plural switches for switching over signal paths. A control circuit controls on/off states of the switches to discharge the sampling capacitor and the integrating capacitor and causes the loop filter to repeat a sampling operation and an integrating operation plural times. The control circuit lastly connects the sampling capacitor and the integrating capacitor to a state, which is opposite to the state of the integrating operation time and turns on a converting switch so that the A/D converter A/D-converts the output signal of the loop filter.

Abstract: A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.

Abstract: An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.

Abstract: A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.

Abstract: A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC.

Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.