Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.

Abstract: A sigma-delta converter, analog-to-digital conversion system, and an Integrated Circuit (IC) chip are disclosed that include a main sigma-delta modulator and an auxiliary sigma-delta modulator. The auxiliary sigma-delta modulator is electrically matched with the main sigma-delta modulator and is configured to generate an output that is incorporated into a feedback loop of the main sigma-delta modulator to enable the main sigma-delta modulator to adjust an offset signal applied at a main analog channel.

Abstract: A digital-to-analog conversion apparatus has a first digital-to-analog converter, at least one second digital-to-analog converter, and a combining circuit. The first digital-to-analog converter is arranged to receive a first sampling clock and a digital input, and convert the digital input into a first analog output according to the first sampling clock. The at least one second digital-to-analog converter is arranged to receive the digital input and at least one second sampling clock different from the first sampling clock, and convert the digital input into at least one second analog output according to the at least one second sampling clock. The combining circuit is arranged to combine the first analog output and the at least one second analog output into a combined analog output of the digital input.

Abstract: A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a signal provided from the latch unit by a predetermined time regardless of the clock signal.

Abstract: Described herein are improved configurations for a wireless power transfer. The parameters of components of the wireless energy transfer system are adjusted to control the power delivered to the load at the device. The power output of the source amplifier is controlled to maintain a substantially 50% duty cycle at the rectifier of the device.

Abstract: An apparatus and method for encoding/decoding a multi-channel signal may be provided. The apparatus of encoding a multi-channel signal may insert information about whether to encode a phase parameter indicating phase information of a plurality of channels, included in the multi-channel signal, in a bitstream of the multi-channel signal. The apparatus of decoding a multi-channel signal may determine whether to up-mix a mono signal using the phase parameter based on the information about whether to encode.

Abstract: A signal combination circuit includes a first decoding block configured to decode a first signal group of an input signal and generate a first decoding signal group according to a first random number signal, a second decoding block configured to decode a second signal group of the input signal and generate a second decoding signal group according to the first random number signal, a first network block configured to randomly mix the first decoding signal group and generate a first preliminary mixed signal group according to a second random number signal, a second network block configured to randomly mix the second decoding signal group and generate a second preliminary mixed signal group according to the second random number signal, and a selection block configured to selectively combine the first preliminary mixed signal group and the second preliminary mixed signal group and generate a mixed signal group according to the first random number signal.

Abstract: Requirements placed on the first integrator of a filter in a continuous-time delta-feedback modulator may be reduced by using circuitry to reduce the speed of a signal provided to the first integrator of the modulator. The reduction in speed applied to the signal received at the first integrator may then be compensated with circuitry elsewhere in the modulator, such that the net effect of the slow down and speed up of signals does not affect the output of the modulator. The sigma-delta modulator may be implemented in converters, such as an analog-to-digital converter (ADC).

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: Provided is a data converter which is provided with a clock signal input part which inputs a clock signal, and an input part which inputs an input signal, a sampling part which, in response to the clock signal input to the clock signal input part, performs sampling of the input signal input to the input part, and a signal processing part which performs signal processing according to the sampling cycle and outputs an output signal, wherein when the cycle of the clock signal input to the clock signal input part becomes longer, the output signals output by the signal processing part are reduced.

Abstract: A method of providing a clock frequency to a processor is described. The method in accordance with the invention comprises the step of providing at least one reference signal and the step of determining a control value which relates to a desired first frequency. A second signal that relates to the control value is then used in a subsequent step as an input signal for a noise shaper. Then, a first signal which has the first frequency is generated by combining the output of the noise shaper with one of the at least one reference signals. The first signal is used as a clock frequency of the processor. In a preferred embodiment, one reference signal with a fixed reference frequency is provided. The reference signal is gated or enabled and hold by the output signal provided by a 1-bit noise shaper, whereby the first frequency is generated which is then used as processor clock frequency.

Abstract: A method for processing a measured-value signal representing a value, determined in analog form, for the output current of a converter, and device for carrying out the method, the measured-value signals acquired by a sensor, especially including a shunt resistor, being supplied to a respective processing channel that has at least one delta-sigma modulator.

Abstract: Provided is a second order loop filter (LF). The second order LF includes: an operational amplifier including a first input, a second input receiving a differential input of the first input, and an output; an inverter inverting a signal output from the output of the operational amplifier to output an inverted signal; a first resistor connected to between the first input and a first node; a second resistor connected to between the output of the operational amplifier and the first node; a third resistor connected to between the first input and an input signal; a first capacitor connected to between the second input and the first node; a second capacitor connected to between the output of the operational amplifier and an output of the inverter; and a third capacitor connected to between the output and the first input of the operational amplifier, wherein the second input is connected to a ground voltage.

Abstract: A Sigma-Delta modulator and an analog-to-digital converter. The Sigma-Delta modulator comprises a quantizer, a correction module and an RC integrator. The correction module comprises a predetermined resistance through which a correction level is generated. The correction module is used to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, so as to generate a digital correction signal, based on which the resistance in a resistance correction array in the RC integrator is corrected. The predetermined resistance is of the same type as the resistance in the resistance correction array in the RC integrator. The Sigma-Delta modulator and the analog-to-digital converter can correct the resistance deviation in the RC integrator.

Abstract: Apparatus and methods are taught for dividing a signal to be processed by a Noise Shaping (Hereafter NS) loop into smaller sections, and applying NS to at least a subset of these smaller sections. The processed signals are then recombined. As noise shaping is performed on smaller sections, the operating speed of each noise shaping loop, and accordingly for the system in general, is faster than if the output signal had been generated by single higher bit NS loop. Embodiments further include a configuration block for configuring the apparatus. For example, the number of sections, the section calculation method, and the NS for each section can each be configurable, and for some embodiments, programmable.

Abstract: An analog-to-digital conversion that converts an input signal to an output signal by using multiple analog-to-digital converting circuits. A first analog-to-digital converting circuit generates a first signal based on the input signal and further outputs a feature signal of a first quantization error of the first analog-to-digital converting circuit. A second analog-to-digital converting circuit generates a second signal based on the input signal and the feature signal. The output combiner combines the first signal and the second signal to generate the output signal and thereby to reduce a quantization error factor in the output signal that is due to the first quantization error.

Abstract: A delta-sigma modulator for a switching amplifier, which achieves a high signal-to-noise ratio (SNR) in the multi-MHz range and keeps the noise-transfer function over the useful frequency range as low and as flat as possible. A series connection of a parallel-serial converter and a downstream swap element for the serial output signal ya2 of the parallel serial converter is connected to the multi-bit output of the delta-sigma-modulator. The swap element swaps, based on the last bit value 0 or 1 of a preceding word in the resulting output signal ya3, the sequence of the binary zeroes and ones of the current word, where present, and then an input signal is fed to the delta-sigma-modulator. The signal is capable of having a frequency range above 25 kHz, and is prepared with a low oversampling ratio and a high SNR. And, 1-0 or 0-1 transitions are largely eliminated at the word boundaries.

Abstract: In the present embodiment, quantizer output values including variation values corresponding to duty errors of pulse width data (PWM output signals) occurring by the difference of the pull-down/pull-up drive characteristics (drive capabilities) of a buffer are stored in advance in a feedback value memory in a quantizer as feedback values FBV0 to FBV4, and a feedback value FBVn read out from the feedback value memory in response to the quantization of a delta-sigma modulation output is inputted into a subtractor by return input. Then, a quantizer output value including a variation value corresponding to a duty error is subtracted from input data Din, and delta-sigma modulation is performed such that the difference is minimized, whereby the duty error of pulse width data (PWM output signal) is compensated.

Abstract: In accordance with embodiments of the present disclosure, a method and apparatus for providing a digitized microphone signal to a digital processing device may include an analog signal path portion, a digital signal path portion, and a control circuit. The analog signal path portion may have an audio input configured to receive an analog input signal indicative of audio sounds incident upon an audio transducer. The digital signal path portion may have an analog-to-digital converter for converting the analog microphone signal to the digitized microphone signal. The control circuit may be configured to control a magnitude of the analog input signal or a derivative thereof in order to reduce audio distortion occurring in either or both of the analog signal path portion and the digital signal path portion.

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract: One or more techniques for buffer offset modulation or buffer offset cancelling are provided herein. In an embodiment, an output for a sigma-delta analog digital converter (ADC) is provided using an output of a first chop-able buffer (FB) and an output of a second chop-able buffer (SB). For example, the output of the FB is associated with a first offset, the output of the SB is associated with a second offset, and the output of the ADC includes an ADC offset associated with the first offset and the second offset. In an embodiment, buffer offset modulation is provided by modulating the ADC offset using an offset rotation. In an example, the offset rotation is based at least in part on a reference clock and the output of the ADC. The buffer offset modulation mitigates the first offset or the second offset, where such offsets are generally undesired.

Abstract: In an ultra-wideband communication system, a 1-trit ternary analog-to-digital converter (“ADC”) having dynamic threshold adaption and providing an output in ternary form [+1, 0, ?1]. The ternary ADC includes a pair of 1-bit binary ADCs, one being configured in a non-inverting form, and one being configured in an inverting form. Each binary ADC includes an feedback network mechanism, thereby allowing for simultaneous and independent adaptation of the pair of thresholds, compensating for the effects of any DC offset that may be present. The use of a trit-based ternary encoding scheme improves system entropy.

Abstract: A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

Abstract: In accordance with the exemplary embodiments of the invention there is at least an apparatus to perform a method including receiving by an analog-to-digital converter a signal; determining whether an in-band blocker is present in the signal; and adjusting a transfer function of the analog-to-digital converter based on whether an in-band blocker is present by configuring a loop filter of the analog-to-digital converter.

Abstract: A signal processing apparatus is described comprising a sampling time control circuit configured to provide a sequence of digital values, each digital value specifying a sampling time of a sequence of sampling times, a sampling circuit configured to sample an input signal according to the sequence of sampling times to generate a sampling value of the input signal for each sampling time of the sequence of sampling times and a processing circuit configured to receive the sampling values and configured to process the sampling values based on the sampling times, wherein the sampling time control circuit is configured to introduce jitter into the sampling times, by varying the time intervals between adjacent sampling times.

Abstract: An object of the invention is to provide a physical quantity sensor capable of producing a highly accurate physical quantity detection signal.

Abstract: There is provided a signal processing device including a first correction processing section that performs first correction on a predetermined signal, an adaptive processing section that performs predetermined adaptive processing on the signal that has been subjected to the first correction, and a second correction processing section that performs second correction, which is reverse correction of the first correction, on the signal that has been subjected to the adaptive processing, in accordance with the amount of delay in the adaptive processing.

Abstract: A continuous-time sigma delta radio frequency modulator is provided, including at least two LC resonators coupled in parallel by a coupling capacitive element, producing an at least 4th-order bandpass filter, a frequency response of the bandpass filter presenting at least two poles that can be brought closer together or moved further apart depending on the capacitive element value; a feedback loop for shaping the quantization noise with a predetermined noise transfer function; and an adder for receiving: at one of its inputs an analog signal; and at its other input a signal provided by the feedback loop; and the output of which is linked to the input of the bandpass filter, the feedback loop including a finite impulse response filter, the coefficients of which being calculated to obtain a noise transfer function which maximizes the signal-to-noise ratio in a signal bandwidth while ensuring the stability of the feedback loop.

Abstract: A selection device includes an acquisition part to acquire digital selection signals, and an output part to output selection signals to respective unit cells, each unit cell capable of being commanded to output the value zero. In the selection device, each selection signal is to command the unit cell to output a value corresponding to that selection signal; the sum of the values to be output as commanded by the respective selection signals, which are output to the respective unit cells, is a value determined in association with the digital selection signal; and if the output corresponding to the digital selection signal is the value zero, then selection signals each commanding to output a non-zero value (N) are output to some of the unit cells.

Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.

Abstract: A circuit includes an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a digital filter configured to filter the digital output and a noise shaper. The noise shaper is configured to truncate the filtered digital output and generate a noise shaper output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC) configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

Abstract: A bandwidth estimator circuit for an analog to digital converter. The bandwidth estimator computes a bandwidth estimate of an analog signal and includes: an amplitude averaging block configured to determine an average change in amplitude of N samples, a delta time block configured to determine a minimum time difference; a peak voltage block configured to determine the maximum magnitude; a peak to root mean square block configured to determine a ratio of a peak voltage to the root mean square of the magnitude; a bandwidth estimator block configured to compute a product of a ratio of the average change in amplitude to the minimum time difference, multiplied by a ratio of the peak voltage to the root mean square, squared, to the peak voltage multiplied by a constant; and a parameter adjustment circuit configured to modify sampler parameters controlling an analog signal sampling rate. Methods are described.

Abstract: An apparatus includes a pulse shaper (120) for receiving signals indicative of detected photons and generating a plurality of pulses therefrom to form a pulse train (200) and a peak detector (150) for sampling the pulse train (200) at an output of the pulse shaper (120). The peak detector (150) includes a circuit (300) for selectively detecting and sampling a maximum (202a, b, c) and a minimum (204a, b) value of the pulse train (200). The maximum (202a, b, c) and minimum (204a, b) values sampled are then converted from analog-to-digital format via an analog-to-digital converter (160).

Abstract: A method is provided for generating a digital signal from an analog signal generated using a frequency converter on the basis of pulse width modulation with a variable period duration, values of the digital signal corresponding to an average value of the analog signal over an associated period duration of the pulse width modulation.

Abstract: A digital, three-level output driver (7) of the H-bridge variety for a hearing aid (20) obtains a reduced capacitive interference by providing a primary voltage (3) and a secondary voltage (8) for the output driver (7) and applying the secondary voltage (8) to both sides of the output driver (7) whenever the middle level of the three-level output driver (7) is present in the input signal for the output driver (7). The output driver (7) may be controlled from a pulse-width modulated signal, a sigma-delta pulse-density modulated signal, or a combination of those signals. The output driver (7) produces a clocked output signal consisting of a positive level, a negative level, and a zero level for driving an acoustic output transducer of the hearing aid (20). The invention provides a hearing aid (20) and a method of driving an output stage (7) of a hearing aid (20).

Abstract: A low pass filter includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential operational amplifier, wherein the first amplifier stage is arranged to process a differential input signal to generate a differential intermediate signal, the differential input signal having a first input signal and a second input signal, and the differential intermediate signal having a first intermediate signal and a second intermediate signal. The second amplifier stage has no common-mode feedback and is arranged to process the differential intermediate signal to generate a differential output signal, wherein the differential output signal has a first output signal corresponding to the first input signal and a second output signal corresponding to the second input signal. Since the noisy common-mode feedback is removed from the second amplifier stage, the overall common-mode noise of the low pass filter can be decreased.

Abstract: A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized.

Abstract: The pulser logic method and system for an ultrasound beamformer is based on using memory blocks instead of ordinary binary counters to accomplish transmit focusing of an ultrasound beam. This method reduces the use count of logic blocks (cost reduction) and facilitates the FPGA floor planner routing, increasing the design overall speed (performance enhancement). The exemplary design disclosed herein is for sixteen channels, but can be adjusted for any number of beamformer channels. The design may use, for example, a Xilinx Spartan-3 field programmable gate array (FPGA).

Abstract: Methods and systems are provided for generating correction estimates. Training signals may be injected into one or more particular spectral regions, and one or more correction estimation parameters may be determined based on the injecting of the training signals, where the one or more correction estimation parameters reduce distortion in at least the one or more particular spectral regions. The particular spectral regions may comprise originally-unoccupied spectral regions. The one or more correction estimation parameters may be applied during correcting of digital signals generated based on processing of received analog signals. The training signals may be generated, such as based on one or more pre-defined characteristics. The one or more correction estimation parameters may then be determined based on the one or more pre-defined characteristics of the training signals and/or changes thereto.

Abstract: A sigma delta analog-to-digital converter includes a sigma delta modulator including a segmented digital-to-analog converter (DAC), the segmented DAC including a coarse DAC and a fine DAC, wherein the sigma delta modulator is configured to generate a coarse quantized signal and a fine quantized signal; recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between the coarse DAC and the fine DAC of the segmented DAC.

Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

Abstract: The systems, methods, and devices disclosed herein relate to a bit-per-stage ADC. The bit-per-stage ADC extracts one or more bits at each stage and creates a residue so that succeeding similar or identical stages can extract more bits. The ADC uses a reflected binary output code so that a bit can be extracted by observing the sign (e.g., polarity) of an input. The residue can be generated by rectifying the input, multiplying it by two, and level-shifting it by half the span. The generation of the residue is achieved using capacitors and switches. This causes the ADC to have low power consumption and a small size.

Abstract: A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that generates a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The first electrical signal is converted to a second electrical signal using a converter coupled between the micro-mechanical structure and the ADC. The first electrical signal is free from being amplified.

Abstract: To provide a D/A converter including a sampling circuit capable of suppressing a high-frequency component in an input signal without obstructing downsizing of electronic equipment. A D/A converter includes a first capacitative element unit including plural sampling capacitors, a second capacitative element unit including plural sampling capacitors, a first switch unit including the plural switches configured to store charges in the plural sampling capacitors of the first capacitative element unit and to transfer the charge, and a second switch unit including the plural switches configured to store charges in the plural sampling capacitors of the second capacitative element unit and to transfer the charge. The first and the second switch units operate alternately.

Abstract: The present disclosure describes a mechanism to digitally correct for the static mismatch of the digital-to-analog converter (DAC) in at least the first-stage of a multi-stage noise shaping (MASH) analog-to-digital converter (ADC). The correction is applicable to continuous-time implementations, and is especially attractive for high-speed applications.

Abstract: An idle tone dispersion device includes n FDSM (1) to FDSM (n), a phase adjustment unit which relatively adjusts a phase between a measured signal and a reference signal such that a phase of an idle tone is completely different, and generates and supplies n sets of output measured signals and output reference signals to each of the n FDSM (1) to FDSM (n), and an adder which adds output data of the n FDSM (1) to FDSM (n) and outputs a frequency delta-sigma modulation signal.

Abstract: Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, a device including: modulation circuitry of a radio frequency transmitter having a local oscillator frequency; a digital power amplifier coupled with the modulation circuitry; and a clock input coupled with the digital power amplifier; wherein the clock input provides a clock signal to the digital amplifier at a sampling clock frequency; and wherein the local oscillator frequency is an integer multiple of the sampling clock frequency.

Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence.

Abstract: The application disclose a sigma-delta analog-to-digital converter.

Abstract: An analog to digital converter is disclosed herein. The analog to digital converter includes a bit conversion module and a control module. The bit conversion module is configured to generate a quantization output in accordance with an input signal. The control module is configured to control the bit conversion module, so as to make the bit conversion module operate in one of a sigma delta mode and a successive approximation mode.