Abstract: In one aspect, an integrated circuit (IC) includes a magnetic-field sensor. The magnetic-field sensor includes digital circuitry that includes a first and second analog-to-digital converter (ADC). The digital circuitry is configured to receive a first and second analog output signals and, using the first and second ADC, configured to convert the first and second analog output signals to a first and second digital signals. The magnetic-field sensor also includes diagnostic circuitry configured to receive, from the digital circuitry, an input signal related to the first and/or the second digital signals and configured to provide a test signal at a pin of the IC. In response to a range parameter, the diagnostic circuitry is further configured to provide the test signal comprising a range of codes from the first and/or the second ADC corresponding to the range parameter.

Abstract: A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.

Abstract: One example includes a superconducting current control system. The system includes an inductive coupler comprising a load inductor and a control inductor. The inductive coupler can be configured to inductively provide a control current from the control inductor to a superconducting circuit device based on a load current being provided through the load inductor. The system also includes a current control element comprising a superconducting quantum interference device (SQUID) array comprising a plurality of SQUIDs. The current control element can be coupled to the inductive coupler to control an amplitude of the load current through the load inductor, and thus to control an amplitude of the control current to the superconducting circuit device.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.

Abstract: Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.

Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.

Abstract: A digital-analog converter of the disclosure converts digital image data to generate analog data signals. The digital-analog converter includes a voltage divider which generates a plurality of gamma reference voltages based on a first reference voltage and a second reference voltage; a global ramp including a plurality of gamma decoders which generates a plurality of global gamma voltages based on the gamma reference voltages; a decoder which selects one of the global gamma voltages according to the digital image data to generate the analog data signals; and a ramp controller which turns off at least some of the gamma decoders based on the digital image data.

Abstract: An electronic device may include digital circuitry to operate via digital signals and analog circuitry to operate via analog signals. The electronic device may also include a fractal digital to analog converter (DAC) to convert a digital signal into an analog signal. The fractal DAC may include a unit cell array having a branching data path and multiple unit cells disposed in a fractal pattern. The fractal DAC may also include multiple decision units disposed within the unit cell array on the branching data path. Each decision unit may receive an incoming signal representative of at least a portion of the digital signal and direct each decision unit output to different branches of the unit cell array. The unit cells may be enabled based at least in part on the decision unit outputs to generate the analog signal.

Abstract: Disclosed herein are a data driving device and a display device using the same. The data driving device includes a selector for sequentially selecting pieces of gamma reference data input from banks in the order of a first color, a second color, and a third color, and a voltage output part for converting the pieces of gamma reference data for each color, which is sequentially input, into gamma reference voltages.

Abstract: A data driving circuit includes a first voltage divider circuit configured to output a gamma compensation voltage for a first color, a second voltage divider circuit configured to output a gamma compensation voltage for a second color, a third voltage divider circuit configured to output a gamma compensation voltage for a third color, a first digital-to-analog converter (DAC) configured to convert input data for the first color using the gamma compensation voltage for the first color to output a data voltage of a first channel, a second DAC configured to convert input data for the second color using the gamma compensation voltage for the second color to output a data voltage of a second channel, and a third DAC configured to convert input data for the third color using the gamma compensation voltage for the third color to output a data voltage of a third channel.

Abstract: A cycle estimation device (10) includes: a candidate cycle extraction unit (11) which extracts a candidate cycle that is a cycle determination target from an input time-series pulse train; a pulse train shape analysis unit (12) which converts arrangement of the time-series pulse train into numerical values on the basis of the extracted candidate cycle and outputs a constant that adjusts a random noise threshold value of pulse repetition interval (PRI) conversion in response to an index indicating a degree of concentration of calculated numerical values; and a cycle detection unit (13) which executes PRI conversion using a value of the candidate cycle and the constant and performs cycle determination and cycle value detection.

Abstract: A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

Abstract: A quad signal generator circuit generates four 2N?1 bit control signals in response to a sampling clock and a 2N?1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N?1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N?1 bit control signals. Outputs of the 2N?1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N?1 bit control signals such that all logic states of bits of the four 2N?1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N?1 bit thermometer coded signal.

Abstract: A successive approximation analog-digital (AD) converter and method performed by the converter are provided. The successive approximation AD converter comprises a digital-analog (DA) converter; a comparator which determines a magnitude relation between an input signal and an output signal of the DA converter; and a successive approximation register which generates a first digital signal based on a determination result. The method comprises: switching an operation selection signal from a first logic to a second logic; performing a logical operation so that a digital signal input to the DA converter has a larger value or a smaller value than the first digital signal, when the operation selection signal has transited to the second logic, based on a portion of the determined first digital signal until transition; and inputting the first digital signal to the DA converter when the operation selection signal is the first logic.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.

Abstract: A system includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g., temperature) and is proportional to the unknown scalar.

Abstract: A grayscale voltage generator circuit that is less likely to be influenced by the offset voltage is provided. The grayscale voltage generator circuit is a semiconductor device that includes a D/A converter circuit, a first Gm amplifier, a second Gm amplifier, a current control circuit, an output buffer, and a selector circuit. The D/A converter circuit generates a first voltage and a second voltage from an upper bit of a digital signal. The current control circuit generates a first current from a lower bit of the digital signal and functions as a current source of the first Gm amplifier. The output buffer generates a third voltage from currents output from the first Gm amplifier and the second Gm amplifier. The third voltage is input to the second Gm amplifier. The selector circuit selects voltages that are to be input to the first Gm amplifier and the second Gm amplifier.

Abstract: A digital to analog converter, a method for driving the same, and a display device are provided. The digital to analog converter includes: a first resistor string, 2m first multiplexers, a first voltage selector, a second resistor string, a second voltage selector, and a second multiplexer, where the 2m first multiplexers, the first voltage selector, and the second voltage selector operate in cooperation with each other so that the entire second resistor string can be connected in series to the first resistor string for further division.

Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.

Abstract: A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2X?1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2X?1) groups of the thermometer encoding current sources into the M sub-arrays, arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.

Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.

Abstract: To perform inter-pixel image processing with lower latency and higher speed. An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: A method includes reading a digital signal from a sensing device in an area of a structure, where the digital signal is configured to be present periodically. A trailing edge of the digital signal is determined. An analog signal from the sensing device is read, where the analog signal includes an output from a sensor included in the sensing device, and where the sensor is configured to detect an aspect of an environment. The analog signal is read after the trailing edge of the digital signal.

Abstract: An ADC includes: a ramp signal selector suitable for selecting a ramp signal selector suitable for selecting a rising half ramp signal or falling half ramp signal according to a ramping direction detection result from a ramping direction detector; a comparator suitable for outputting an initial comparison result signal by initially comparing a half ramp signal and a pixel signal, and outputting a comparison result signal by comparing the rising or falling half ramp signal selected through the ramp signal selector to the pixel signal; the ramping direction detector suitable for detecting a ramping direction according to the initial comparison result signal from the comparator; and a data converter suitable for deciding an initial bit according to the initial comparison result signal from the comparator, and performing data conversion according to the comparison result signal from the comparator.

Abstract: A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12).

Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.

Abstract: A segmented digital-to-analog converter (DAC) circuit includes an interpolation resistor DAC (RDAC) and a buffer amplifier. The interpolation RDAC includes a resistor-two-resistor (R-2R) DAC and a resistor ladder. The R-2R DAC is configured to receive a first subword and generate an analog output signal with a voltage representative of the first subword. The first subword has an integer number M bits that include a most significant bit (MSB) of a digital input signal. The resistor ladder is configured to receive the analog output signal and a second subword and generate an analog interpolated signal. The second subword has an integer number I bits that include an intermediate significant bit (ISB) of the digital input signal The buffer amplifier is configured to receive the analog interpolated signal and generate an output signal for the segmented DAC.

Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method for operating the same are provided. The SAR ADC includes a first capacitor DAC (CDAC), a comparator and a controller. The first CDAC receives and samples an analog input signal to generate a first voltage. The comparator compares the first voltage with a comparison reference voltage to generate a first comparison result. In a k-th iteration of at least two iterations, the controller switches a k-th switching capacitor set from a first state to a second state, such that the first CDAC generates a second voltage, and the comparator compares the second voltage with the comparison reference voltage to generate a second comparison result. The controller determines a window region and determines whether the k-th switching capacitor set is switched back to the first state according to the first comparison result and the second comparison result.

Abstract: A voltage generation circuit having a temperature compensation function includes a first voltage generation circuit, a second voltage generation circuit, an output voltage control circuit, and a voltage selection circuit. The first voltage generation circuit is configured to generate a first voltage having a zero temperature coefficient, determined in response to a first control signal. The second voltage generation circuit is configured to generate a second voltage having a positive temperature coefficient, determined in response to a second control signal. The output voltage control circuit is configured to control an output of one of the first voltage and the second voltage in response to an operating mode. The voltage selection circuit is configured to select the first voltage or the second voltage in response to the output voltage control circuit.

Abstract: A highly granular voltage regulator is disclosed. The voltage regulator circuit includes first and second current mirror circuits coupled to first and second control circuits, respectively. The voltage regulator circuit further includes an amplifier having an inverting input and a non-inverting input. The first current mirror circuit is coupled to the non-inverting input, whereas the second current mirror circuit is coupled to the inverting input. The first control circuit is operable to control a current provided by the first current mirror circuit, while the second control circuit is operable to control a current provided by the second current mirror circuit.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: A digital-to-analog converter includes a first input end for reversely receiving a digital signal, a second input end for receiving multiple reference voltages arranged in a best order, wherein the best order is determined by reordering an initial order several times, multiple first switches coupled to each other stage by stage like a tree for selecting one of the reference voltages to be a first selection result, multiple second switches coupled in series for selecting one of the reference voltages to be a second selection result.

Abstract: Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.

Abstract: A digital modulation device is provided. The digital modulation device includes an input unit; N delta-sigma modulation units; and an output unit. N is an integer greater than or equal to 2, the input unit is configured to: input initial values which differ from each other to the N delta-sigma modulation units; and then, input a same first signal into the N delta-sigma modulation units, each of the N delta-sigma modulation units is configured to: output a second signal by performing delta-sigma modulation processing on the first signal for each first clock cycle, and the output unit is configured to: sequentially output each second signal for each one Nth of the first clock cycle.

Abstract: A headphone driver, a sound processor that incorporates the headphone driver and a computing system that incorporates the headphone driver, wherein the headphone driver includes an amplifier having an input terminal and an output terminal, an R-2R ladder network provided with an input signal and connected to the input terminal of the amplifier, and a feedback resistor group connected to the input terminal and to the output terminal of the amplifier. The R-2R ladder network includes a plurality of resistor branches and a first attenuator that is connected between the plurality of resistor branches.

Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Abstract: In accordance with an embodiment of the present invention, a chip set for a mobile device includes a slave device chip and an interface circuit chip that includes a slave bus interface for controlling the slave device chip through an analog bus. The slave bus interface is coupled to a master bus interface via a digital bus of the mobile device. The slave bus interface is configured to be driven by the master bus interface.

Abstract: In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.

Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with partial constant switching. A digital-to-analog converter (DAC) comprising a plurality of conversion elements may be configured to apply constant switching in only some of the conversion elements. Only conversion elements applying constant switching may incorporate circuitry for providing such the constant switching. Alternatively, each conversion element may incorporate constant switching circuitry and functionality, and the constant switching may then be turned on or off for each conversion element adaptively, such as based on input conditions.

Abstract: The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

Abstract: A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

Abstract: A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

Abstract: Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

Abstract: The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.

Abstract: Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

Abstract: In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.