Coarse And Fine Conversions Patents (Class 341/145)
  • Patent number: 11838031
    Abstract: A digital-to-analog conversion circuit, comprising: an R?2R resistive network (10) configured to be connected between an output end and a ground end; an output voltage selection unit (20) configured to be connected between the output end of the R?2R resistive network (10) and a voltage output terminal; an output voltage trimming unit (30), wherein the output voltage trimming unit (30) is provided between a 2R resistor on at least one branch of the R?2R resistive network (10) and the ground end.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 5, 2023
    Assignee: SHANGHAI ANALOGY SEMICONDUCTOR TECHNOLOGY LTD.
    Inventors: Jun Zhang, Zhian Zhang
  • Patent number: 11804185
    Abstract: Provided is a display device including a display panel configured to display an image, a data driving circuit configured to supply a data voltage to the display panel, and a timing controller configured to control the data driving circuit, in which the data driving circuit includes a first converter configured to divide and output a voltage based on a plurality of resistors, a gain circuit configured to selectively receive at least two different voltages from the first converter, and amplify voltages input through input terminals to output the voltages to at least two output terminals or output the voltages without amplification and without change, and a second converter configured to interpolate and output at least two voltages output from the gain circuit.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: October 31, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Byung Jae Lee, Jung Heo, Da Hye Kwon
  • Patent number: 11800762
    Abstract: An electro-optical device includes a DA conversion circuit to convert 10 bits of data into an analog voltage output to a data line. The DA conversion circuit includes a first DA conversion circuit to convert upper 5 bits into a voltage and outputs converted voltage to the data line, a second DA conversion circuit to convert lower 5 bits into a voltage and outputs converted voltage to a relay line, and a coupling capacitance including one end electrically coupled to the second DA conversion circuit and another end electrically coupled to the data line, wherein the first DA conversion circuit includes a capacitance element corresponding to the upper 5 bits and is arranged in the Y direction along the data line, and the second DA conversion circuit includes a capacitance element corresponding to the lower 5 bits and is arranged in the Y direction along the data line.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: October 24, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hitoshi Ota
  • Patent number: 11700007
    Abstract: A digital-to-analog conversion device and method are provided. The control module is configured to split the input digital signal into n intermediate digital portions, divide the n intermediate digital portions by the corresponding conversion coefficients to obtain n intermediate digital signals and transmit the n intermediate digital signals to the n conversion modules. The n intermediate digital portions increase progressively. The conversion module is configured to perform digital-to-analog conversion on an intermediate digital signal to obtain a result including the conversion coefficient of the conversion module. The adder is configured to add output signals of the n conversion modules to obtain an analog signal. The feedback module is configured to obtain a feedback signal according to the analog signal. The control module is further configured to adjust the allocation of the n intermediate digital portions according to a target digital signal and the feedback signal.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: July 11, 2023
    Inventors: Xi Fang, Gang Du, Min Xu
  • Patent number: 11700012
    Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyeongjoon Ko, Junhan Bae, Hanseok Kim, Byeonggyu Park, Jaehyun Park, Hobin Song, Sooeun Lee
  • Patent number: 11689212
    Abstract: A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+???N with a length ?=?+?, wherein M is a control code with a length ?, including high-order bits of the control code X, and ???N is a control code with a length ?, including lower-order bits of the control code X, wherein ???; performing digital multiplication of the lower-order a??N bits of the control code X by a? times algebraic summing ? of the high-order bits of the control code X and ? of the lower-order bits of a??N of the control code X being a result of multiplication by a? times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y1 to an analog signal Z1, and converting the resulting digital code N from a reference signal Y2 to an analog signal Z2, wherein reference signals Y1 and Y2 are related by a ratio: Y
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: June 27, 2023
    Inventor: Yury Alexandrovich Nikitin
  • Patent number: 11658676
    Abstract: A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: May 23, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hitoshi Ota
  • Patent number: 11648400
    Abstract: The disclosure describes an implementation of a combinational thermometric-R2R that includes a thermometric DAC circuit to output the coarse output steps, an R2R circuit to control the fine output steps, and a resistor in series with the thermometric and R2R circuits. The techniques of this disclosure implement a fine resolution DAC, on the order of two nanoamps per bit, that operates at low current, yet maintains monotonicity throughout the DAC output range.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 16, 2023
    Assignee: MEDTRONIC, INC.
    Inventors: Krishna Pramod Madabhushi, Robert W. Hocken, Jr.
  • Patent number: 11637560
    Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and ?1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 25, 2023
    Assignee: Intel Corporation
    Inventors: Martin Clara, Daniel Gruber, Kameran Azadet
  • Patent number: 11626884
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: April 11, 2023
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 11598655
    Abstract: In one aspect, an integrated circuit (IC) includes a magnetic-field sensor. The magnetic-field sensor includes digital circuitry that includes a first and second analog-to-digital converter (ADC). The digital circuitry is configured to receive a first and second analog output signals and, using the first and second ADC, configured to convert the first and second analog output signals to a first and second digital signals. The magnetic-field sensor also includes diagnostic circuitry configured to receive, from the digital circuitry, an input signal related to the first and/or the second digital signals and configured to provide a test signal at a pin of the IC. In response to a range parameter, the diagnostic circuitry is further configured to provide the test signal comprising a range of codes from the first and/or the second ADC corresponding to the range parameter.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: March 7, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventor: Kevin Maffei
  • Patent number: 11569836
    Abstract: A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.
    Type: Grant
    Filed: June 12, 2021
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byungsuk Woo, Younguk Chang, Yongho Cho
  • Patent number: 11545288
    Abstract: One example includes a superconducting current control system. The system includes an inductive coupler comprising a load inductor and a control inductor. The inductive coupler can be configured to inductively provide a control current from the control inductor to a superconducting circuit device based on a load current being provided through the load inductor. The system also includes a current control element comprising a superconducting quantum interference device (SQUID) array comprising a plurality of SQUIDs. The current control element can be coupled to the inductive coupler to control an amplitude of the load current through the load inductor, and thus to control an amplitude of the control current to the superconducting circuit device.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 3, 2023
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Joel D. Strand
  • Patent number: 11539370
    Abstract: Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.
    Type: Grant
    Filed: February 23, 2020
    Date of Patent: December 27, 2022
    Assignee: TetraMem Inc.
    Inventor: Ning Ge
  • Patent number: 11539371
    Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: December 27, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Zhilong Tang, Dongwon Seo
  • Patent number: 11509217
    Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: November 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anandha Ruban Tiruchengode Tirumurugga Bupathi, Anand Kannan, Dileep Kumar Ramesh Bhat
  • Patent number: 11501718
    Abstract: A digital-analog converter of the disclosure converts digital image data to generate analog data signals. The digital-analog converter includes a voltage divider which generates a plurality of gamma reference voltages based on a first reference voltage and a second reference voltage; a global ramp including a plurality of gamma decoders which generates a plurality of global gamma voltages based on the gamma reference voltages; a decoder which selects one of the global gamma voltages according to the digital image data to generate the analog data signals; and a ramp controller which turns off at least some of the gamma decoders based on the digital image data.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyung Gun Ma, Oh Jo Kwon, Ji Woong Kim, Jun Yong Song, Seong Joo Lee, Sang Hyun Heo
  • Patent number: 11496147
    Abstract: An electronic device may include digital circuitry to operate via digital signals and analog circuitry to operate via analog signals. The electronic device may also include a fractal digital to analog converter (DAC) to convert a digital signal into an analog signal. The fractal DAC may include a unit cell array having a branching data path and multiple unit cells disposed in a fractal pattern. The fractal DAC may also include multiple decision units disposed within the unit cell array on the branching data path. Each decision unit may receive an incoming signal representative of at least a portion of the digital signal and direct each decision unit output to different branches of the unit cell array. The unit cells may be enabled based at least in part on the decision unit outputs to generate the analog signal.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Apple Inc.
    Inventor: Antonio Passamani
  • Patent number: 11430368
    Abstract: Disclosed herein are a data driving device and a display device using the same. The data driving device includes a selector for sequentially selecting pieces of gamma reference data input from banks in the order of a first color, a second color, and a third color, and a voltage output part for converting the pieces of gamma reference data for each color, which is sequentially input, into gamma reference voltages.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: August 30, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Dae Seok Oh, Yong Won Jo
  • Patent number: 11423821
    Abstract: A data driving circuit includes a first voltage divider circuit configured to output a gamma compensation voltage for a first color, a second voltage divider circuit configured to output a gamma compensation voltage for a second color, a third voltage divider circuit configured to output a gamma compensation voltage for a third color, a first digital-to-analog converter (DAC) configured to convert input data for the first color using the gamma compensation voltage for the first color to output a data voltage of a first channel, a second DAC configured to convert input data for the second color using the gamma compensation voltage for the second color to output a data voltage of a second channel, and a third DAC configured to convert input data for the third color using the gamma compensation voltage for the third color to output a data voltage of a third channel.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 23, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Dae Seok Oh, Yong Won Jo, Yong Woo Yun
  • Patent number: 11349634
    Abstract: A cycle estimation device (10) includes: a candidate cycle extraction unit (11) which extracts a candidate cycle that is a cycle determination target from an input time-series pulse train; a pulse train shape analysis unit (12) which converts arrangement of the time-series pulse train into numerical values on the basis of the extracted candidate cycle and outputs a constant that adjusts a random noise threshold value of pulse repetition interval (PRI) conversion in response to an index indicating a degree of concentration of calculated numerical values; and a cycle detection unit (13) which executes PRI conversion using a value of the candidate cycle and the constant and performs cycle determination and cycle value detection.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 31, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Hiroki Nagayama, Shingo Kashima, Masaki Tanikawa
  • Patent number: 11271583
    Abstract: A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 8, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John L. Melanson, Johann G. Gaboriau, Lei Zhu, Wai-Shun Shum, Xiaofan Fei, Leyi Yin
  • Patent number: 11251806
    Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 15, 2022
    Assignee: Microtera Semiconductor (Guanzhou) Co., Ltd.
    Inventors: Franco Maloberti, Alper Akdikmen, Bin Dai, Linsen Shi, Sen Liu
  • Patent number: 11171664
    Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 9, 2021
    Assignee: Ciena Corporation
    Inventors: Mohammad Honarparvar, Sadok Aouini, Jerry Yee-Tung Lam, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida
  • Patent number: 11152951
    Abstract: A quad signal generator circuit generates four 2N?1 bit control signals in response to a sampling clock and a 2N?1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N?1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N?1 bit control signals. Outputs of the 2N?1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N?1 bit control signals such that all logic states of bits of the four 2N?1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N?1 bit thermometer coded signal.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics International N.V.
    Inventor: Vivek Tripathi
  • Patent number: 11128312
    Abstract: A successive approximation analog-digital (AD) converter and method performed by the converter are provided. The successive approximation AD converter comprises a digital-analog (DA) converter; a comparator which determines a magnitude relation between an input signal and an output signal of the DA converter; and a successive approximation register which generates a first digital signal based on a determination result. The method comprises: switching an operation selection signal from a first logic to a second logic; performing a logical operation so that a digital signal input to the DA converter has a larger value or a smaller value than the first digital signal, when the operation selection signal has transited to the second logic, based on a portion of the determined first digital signal until transition; and inputting the first digital signal to the DA converter when the operation selection signal is the first logic.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 21, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Shota Konno
  • Patent number: 10944419
    Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Zhang
  • Patent number: 10873259
    Abstract: An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anandha Ruban Tiruchengode Tirumurugga Bupathi, Anand Kannan, Dileep Kumar Ramesh Bhat
  • Patent number: 10826512
    Abstract: A system includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g., temperature) and is proportional to the unknown scalar.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: November 3, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Cory Jay Peterson, Chandra B. Prakash, Anand Ilango, Ramin Zanbaghi, Dejun Wang
  • Patent number: 10818216
    Abstract: A grayscale voltage generator circuit that is less likely to be influenced by the offset voltage is provided. The grayscale voltage generator circuit is a semiconductor device that includes a D/A converter circuit, a first Gm amplifier, a second Gm amplifier, a current control circuit, an output buffer, and a selector circuit. The D/A converter circuit generates a first voltage and a second voltage from an upper bit of a digital signal. The current control circuit generates a first current from a lower bit of the digital signal and functions as a current source of the first Gm amplifier. The output buffer generates a third voltage from currents output from the first Gm amplifier and the second Gm amplifier. The third voltage is input to the second Gm amplifier. The selector circuit selects voltages that are to be input to the first Gm amplifier and the second Gm amplifier.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 27, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 10797721
    Abstract: A digital to analog converter, a method for driving the same, and a display device are provided. The digital to analog converter includes: a first resistor string, 2m first multiplexers, a first voltage selector, a second resistor string, a second voltage selector, and a second multiplexer, where the 2m first multiplexers, the first voltage selector, and the second voltage selector operate in cooperation with each other so that the entire second resistor string can be connected in series to the first resistor string for further division.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 6, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tangxiang Wang, Chen Song, Zhan Gao
  • Patent number: 10790849
    Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventor: Franz Kuttner
  • Patent number: 10756750
    Abstract: A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2X?1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2X?1) groups of the thermometer encoding current sources into the M sub-arrays, arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 25, 2020
    Assignee: BEIJING UNISOC COMMUNICATIONS TECHNOLOGY CO., LTD.
    Inventors: Te Han, Junshi Qiao, Jiewei Lai
  • Patent number: 10735016
    Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 4, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kunihiko Nakamura, Tomohiro Nezuka
  • Patent number: 10713749
    Abstract: To perform inter-pixel image processing with lower latency and higher speed. An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 14, 2020
    Assignees: Sony Corporation, The University of Tokyo
    Inventors: Yoshinori Muramatsu, Shuji Uehara, Hironobu Katayama, Tomohiro Yamazaki, Masatoshi Ishikawa, Yoshihiro Watanabe
  • Patent number: 10600292
    Abstract: A method includes reading a digital signal from a sensing device in an area of a structure, where the digital signal is configured to be present periodically. A trailing edge of the digital signal is determined. An analog signal from the sensing device is read, where the analog signal includes an output from a sensor included in the sensing device, and where the sensor is configured to detect an aspect of an environment. The analog signal is read after the trailing edge of the digital signal.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: March 24, 2020
    Assignee: ONEEVENT TECHNOLOGIES, INC.
    Inventors: Kurt Joseph Wedig, Daniel Ralph Parent, Anton Vermaak, Scott Holmstrom, Chris Snyder
  • Patent number: 10574919
    Abstract: An ADC includes: a ramp signal selector suitable for selecting a ramp signal selector suitable for selecting a rising half ramp signal or falling half ramp signal according to a ramping direction detection result from a ramping direction detector; a comparator suitable for outputting an initial comparison result signal by initially comparing a half ramp signal and a pixel signal, and outputting a comparison result signal by comparing the rising or falling half ramp signal selected through the ramp signal selector to the pixel signal; the ramping direction detector suitable for detecting a ramping direction according to the initial comparison result signal from the comparator; and a data converter suitable for deciding an initial bit according to the initial comparison result signal from the comparator, and performing data conversion according to the comparison result signal from the comparator.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyeon-June Kim
  • Patent number: 10511321
    Abstract: A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12).
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 17, 2019
    Assignee: ams AG
    Inventor: Gonggui Xu
  • Patent number: 10396815
    Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Franz Kuttner
  • Patent number: 10305505
    Abstract: A segmented digital-to-analog converter (DAC) circuit includes an interpolation resistor DAC (RDAC) and a buffer amplifier. The interpolation RDAC includes a resistor-two-resistor (R-2R) DAC and a resistor ladder. The R-2R DAC is configured to receive a first subword and generate an analog output signal with a voltage representative of the first subword. The first subword has an integer number M bits that include a most significant bit (MSB) of a digital input signal. The resistor ladder is configured to receive the analog output signal and a second subword and generate an analog interpolated signal. The second subword has an integer number I bits that include an intermediate significant bit (ISB) of the digital input signal The buffer amplifier is configured to receive the analog interpolated signal and generate an output signal for the segmented DAC.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Zhang
  • Patent number: 10211847
    Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method for operating the same are provided. The SAR ADC includes a first capacitor DAC (CDAC), a comparator and a controller. The first CDAC receives and samples an analog input signal to generate a first voltage. The comparator compares the first voltage with a comparison reference voltage to generate a first comparison result. In a k-th iteration of at least two iterations, the controller switches a k-th switching capacitor set from a first state to a second state, such that the first CDAC generates a second voltage, and the comparator compares the second voltage with the comparison reference voltage to generate a second comparison result. The controller determines a window region and determines whether the k-th switching capacitor set is switched back to the first state according to the first comparison result and the second comparison result.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: February 19, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Hui Chung, Bo-Wei Chen
  • Patent number: 10198021
    Abstract: A voltage generation circuit having a temperature compensation function includes a first voltage generation circuit, a second voltage generation circuit, an output voltage control circuit, and a voltage selection circuit. The first voltage generation circuit is configured to generate a first voltage having a zero temperature coefficient, determined in response to a first control signal. The second voltage generation circuit is configured to generate a second voltage having a positive temperature coefficient, determined in response to a second control signal. The output voltage control circuit is configured to control an output of one of the first voltage and the second voltage in response to an operating mode. The voltage selection circuit is configured to select the first voltage or the second voltage in response to the output voltage control circuit.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shinichi Iizuka, Jong Ok Ha, Jeong Hoon Kim
  • Patent number: 10088857
    Abstract: A highly granular voltage regulator is disclosed. The voltage regulator circuit includes first and second current mirror circuits coupled to first and second control circuits, respectively. The voltage regulator circuit further includes an amplifier having an inverting input and a non-inverting input. The first current mirror circuit is coupled to the non-inverting input, whereas the second current mirror circuit is coupled to the inverting input. The first control circuit is operable to control a current provided by the first current mirror circuit, while the second control circuit is operable to control a current provided by the second current mirror circuit.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 2, 2018
    Assignee: Apple Inc.
    Inventors: Weibiao Zhang, Daniel J. Fritchman, Jafar Savoj, Venkatesh B Acharya
  • Patent number: 10056924
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 21, 2018
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing Zhao
  • Patent number: 9997127
    Abstract: A digital-to-analog converter includes a first input end for reversely receiving a digital signal, a second input end for receiving multiple reference voltages arranged in a best order, wherein the best order is determined by reordering an initial order several times, multiple first switches coupled to each other stage by stage like a tree for selecting one of the reference voltages to be a first selection result, multiple second switches coupled in series for selecting one of the reference voltages to be a second selection result.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: June 12, 2018
    Assignee: Sitronix Technology Corp.
    Inventors: Yan-Gang Chen, Chia-Chi Cheng
  • Patent number: 9991904
    Abstract: A digital modulation device is provided. The digital modulation device includes an input unit; N delta-sigma modulation units; and an output unit. N is an integer greater than or equal to 2, the input unit is configured to: input initial values which differ from each other to the N delta-sigma modulation units; and then, input a same first signal into the N delta-sigma modulation units, each of the N delta-sigma modulation units is configured to: output a second signal by performing delta-sigma modulation processing on the first signal for each first clock cycle, and the output unit is configured to: sequentially output each second signal for each one Nth of the first clock cycle.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 5, 2018
    Assignee: NEC CORPORATION
    Inventor: Shinichi Hori
  • Patent number: 9991899
    Abstract: Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 5, 2018
    Assignee: MAXLINEAR, INC.
    Inventors: Gaurav Chandra, Tao Zeng, Shantha Murthy Prem Swaroop, Jianyu Zhu
  • Patent number: 9986336
    Abstract: A headphone driver, a sound processor that incorporates the headphone driver and a computing system that incorporates the headphone driver, wherein the headphone driver includes an amplifier having an input terminal and an output terminal, an R-2R ladder network provided with an input signal and connected to the input terminal of the amplifier, and a feedback resistor group connected to the input terminal and to the output terminal of the amplifier. The R-2R ladder network includes a plurality of resistor branches and a first attenuator that is connected between the plurality of resistor branches.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hyub Kang, Sun Woo Kwon, Hyun Sun Shim, Myung Jin Lee
  • Patent number: 9917595
    Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: March 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Aaron L. Frank
  • Patent number: 9886407
    Abstract: In accordance with an embodiment of the present invention, a chip set for a mobile device includes a slave device chip and an interface circuit chip that includes a slave bus interface for controlling the slave device chip through an analog bus. The slave bus interface is coupled to a master bus interface via a digital bus of the mobile device. The slave bus interface is configured to be driven by the master bus interface.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 6, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Daniel Kehrer