Abstract: Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).

Abstract: An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

Abstract: The RFDAC includes: a multi-phase radio-frequency signal generator configured to generate radio-frequency signals that are different in phase; a vector selector configured to select two radio-frequency signals therefrom, cause each of the two radio-frequency signals to pass through at least one transmission path, combine the two radio-frequency signals; a test signal generator configured to output a test signal; a multiplexer configured to select either the test signal or the baseband signal; a vector controller configured to control the vector selector based on the selected signal and a predetermined selection pattern such that the two radio-frequency signals, and transmission paths thereof are selected; a detector configured to detect an output signal from the vector selector; and a calibrator configured to calibrate a phase error between the selected two radio-frequency signals, based on an envelope of the output signal.

Abstract: Digital to analog converter (DAC) with ternary or tri-state current source. A DAC including a number of ternary or tri-state devices operates based upon codewords provided thereto. Generally, each respective codeword bit directs operation of one of the respective ternary or tri-state devices within the DAC. Each ternary or tri-state device operates in at least three respective operational states (e.g., based upon the respective values of +1, ?1, or 0 being provided thereto). In a current source implementation, each respective current source is implemented to deliver current, draw current, or neither delivered or draw current. In a voltage source implementation, each respective voltage source is implemented to provide a positive voltage, a negative voltage, or provide no voltage. A DAC coding table may be designed based upon characterization of codewords provided to one or more DACs (e.g., based upon a distribution, a probability density function (PDF), etc. of such codewords).

Abstract: A digital-to-analog conversion arrangement for converting a digital input signal comprises first and second digital-to-analog converters (DACs) having different signal resolutions and a digital-to-analog converter selector for selecting the first DAC or the second DAC if the digital input signal has a power in a first or a second power range, respectively. The digital-to-analog conversion arrangement further comprises an analog signal merger for merging a first analog signal and a second analog signal, the first analog signal being based on a first analog output signal of the first digital-to-analog converter and the second analog signal being based on a second analog output signal of the second analog-to-digital converter. A corresponding method for digital-to-analog conversion of a digital input signal and a computer readable digital storage medium are also described.

Abstract: A digital-to-analog converter includes a first decoder, a second decoder and a voltage summing buffer. The first decoder receives upper bits of a digital signal and upper reference voltages to output an upper voltage corresponding to the upper bits. The second decoder configured to receive lower bits of the digital signal and lower reference voltages to output a lower differential voltage corresponding to the lower bits. The voltage summing buffer generates an output voltage based on the upper voltage and the lower differential voltage, such that the output voltage corresponds to the digital signal including the upper bits and the lower bits.

Abstract: Enhanced granularity operational parameters adjustment of components and modules in a multi-band, multi-standard communication device. For supporting two-way communications, a communication device includes receiver and transmitter modules. Each module includes various components that are configurable and/or programmable based on a protocol and band pair by which the communication device is operating. The communication device is a multi-protocol and multi-band capable communication device capable to operate in accordance with any one protocol and band at a first time and another protocol and band at a second time. The various components within each of the receiver and transmitter modules can be adjusted using one or more operational parameters. In some instances, a given component can be controlled by more than one operational parameter. Alternatively, certain components are controlled only one operational parameter.

Abstract: A low power consumption DA converter includes a segment type DA converter and an R-2R resistance ladder DA converter. The segment type DA converter is coupled to a power source voltage VDD and outputs a current signal changing in a stepwise manner according to inputted upper bits D[7 to 5]. The R-2R resistance ladder DA converter is coupled to the segment type DA converter in series between the power source voltage VDD and a ground voltage GND, and outputs an output voltage Vout changing in a stepwise manner. The R-2R resistance ladder DA converter changes the output voltage Vout by raising or lowering a reference voltage Vref according to the lower bits D[4 to 0] and the current signal from the segment type DA converter.

Abstract: A power digital to analog converter may include a course-resolution digital to analog converter for converting a first segment of binary digits into a first analog output having a first voltage. The power digital to analog converter may also include a fine-resolution digital to analog converter connected in series with the course-resolution digital to analog converter. The fine-resolution digital to analog converter may be configured for converting a second segment of binary digits into a second analog output having a second voltage. The first voltage and the second voltage may be added together to produce an analog output signal representing the binary digits.

Abstract: A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.

Abstract: The present invention provides a DAC (Digital to Analog Converter) capable of generating a transfer function having a notch for reducing an error signal level in a desired frequency band. The DAC of the present invention includes a switch bank to which at least two reference signals are inputted and which selects any of these signals and outputs the selected signal through a plurality of paths, and an amplitude-phase control section which controls a reference signal selection operation of the switch bank on the basis of an input signal.

Abstract: A device for driving a switch in a digital-to-analog converter (DAC) includes first and second latches, and a logic gate. The first latch is configured to store a digital input data signal according to a clock signal, and to output a first latch signal corresponding to the stored digital input data signal. The second latch is configured to store the first latch signal output by the first latch according to a logical inverse of the clock signal, and to output a second latch signal corresponding to the stored first latch signal. The logic gate is configured to perform an OR logic operation on the first latch signal and the second latch signal, the logic gate outputting a drive signal for driving a switch in the DAC connected to a current source.

Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

Abstract: A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.

Abstract: A digital-to-analog converter of a data driver and a converting method thereof, in which information corresponding to a lower bit is converted into an analog signal through control of current transmission paths and control of a transconductance ratio. Input data corresponding to a lower bit is converted into an analog signal through control of current transmission paths and control of a transconductance ratio between a delta current generation section and an output buffer amplifier. As a consequence, not only the area of a data driver can be significantly reduced, but also the delta current generation section can be realized even without using a common node feedback circuit, whereby an additional increase in area is not caused.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points.

Abstract: A digital potentiometer includes a circuit containing multiple string arrays, each having a plurality of switching devices connected to an array of resistors. Each input terminal receives a separate digital input code enabling the resistance of one of the arms to be varied without changing the other.

Abstract: For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.

Abstract: A system for implementing a cyclic digital to analog converter (c-DAC) is capable of supporting a large size liquid crystal display. The system includes an upper DAC stage configured to output a first voltage between a lower voltage supply (HVDD) and an upper voltage supply (AVDD). The system also includes a lower DAC stage configured to output a second voltage between the lower voltage supply (HVDD) and a ground. The upper DAC stage includes a single PMOS switch and the lower DAC stage includes a single NMOS switch.

Abstract: An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

Abstract: A signal converting system has a multi-segment digital to analog converter coupled to an error shaping loop. A control value is received at a vector processor that indicates a number N of elements that are to be selected from a vector having M elements. The elements of the vector are sorted into a bitonic sequence and separated into a larger value group and a smaller value group using a bitonic split. Only the larger value group is sorted into an ordered sequence with repeated bitonic splits when the control value is less than M/2, and N largest elements are selected from the ordered sequence. Only the smaller value group is sorted into an ordered sequence with repeated bitonic splits when the control value is greater than M/2, and N?M/2 largest elements are selected from the ordered sequence.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive non-linear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g.

Abstract: A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.

Abstract: A digital-to-analog conversion circuit includes a gradation voltage generation circuit, a most-significant-bits decoder circuit, a least-significant-bits decoder circuit and a calculation circuit. The gradation voltage generation circuit generates multiple main voltages corresponding to most significant bits of the inputted data, and multiple sub voltages corresponding to least significant bits of the inputted data. The most-significant-bits decoder circuit selects one of the main voltages in accordance with the most significant bits, and the least-significant-bits decoder circuit selects one of the sub voltages in accordance with the least significant bits. The calculator circuit performs calculation processing by use of a first main voltage selected by the most-significant-bits decoder circuit, a first sub voltage selected by the least-significant-bits decoder circuit, and a reference voltage.

Abstract: For high resolution resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row of the resistor string are fed into a multiplexer, wherein the multiplexer produces an output voltage. A method and apparatus are disclosed for implementing the reflective nature of Gray code to design a DAC such that all the switches in a column of the resistor string may be controlled with only one control signal, thereby reducing extra routing costs, surface area, and dynamic power consumed by the circuit.

Abstract: An active matrix array device has driver circuitry for providing address signals to the matrix elements, including digital to analogue converter circuitry. This has a voltage selector for selecting a pair of voltages based on a first set of bits of the digital matrix element signal, and a converter arrangement for providing an analogue voltage level derived from the pair of voltages and from a second set of bits of the digital matrix element signal. The converter arrangement comprises first and second digital to analogue converter circuits (30, 32) in parallel and which are adapted to provide an analogue voltage level to an output of the converter arrangement alternately. The invention provides a more efficient use of substrate area for given circuit response requirements.

Abstract: The present invention relates to device and method for controlling a reference voltage of a digital-to-analog converter for minimizing variation of output voltages among LED driving chips which drive an LED (Light Emitting Diode) backlight.

Abstract: A cyclic digital-to-analog converter includes a first capacitor and a second capacitor. Switching circuitry is selectively configurable to connect the first and second capacitors is at least two modes of operation, wherein a first mode uses the first capacitor during conversion of a bit as a sampling capacitor and uses the second capacitor during conversion of that bit as a holding capacitor, and wherein a second mode uses the second capacitor during conversion of a bit as a sampling capacitor and uses the first capacitor during conversion of that bit as a holding capacitor. A controller swaps converter operation between the first and second modes based on the bit values of a digital word to be converted. If adjacent bits of the digital word to be converted have different logical values, the converter swaps from the first mode to the second mode (or from the second mode to the first mode). Otherwise, the converted remains in the current first or second mode.

Abstract: A resistor string type D/A converter includes a higher-order decoder to which a digital signal is input, a higher-order resistor string in which a plurality of resistors and a plurality of voltage drawing points are alternately connected between a first reference voltage and a second reference voltage, the higher-order resistor string being configured to output a plurality of first voltages, each from a respective one of the plurality of voltage drawing points, a plurality of first higher-order switches connected to the plurality of voltage drawing points in a one-to-one configuration, conductive states of the first higher-order switches being controlled based on the digital signal, and a conversion unit that outputs a second voltage based on the plurality of the first voltages supplied through the plurality of first higher-order switches. The higher-order decoder brings two first higher-order switches into conduction based on the digital signal.

Abstract: An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide Nth order resistive current cancellation.

Abstract: In one embodiment, a circuit for providing a tail current for a line driver includes an adjustable current source. The adjustable current source includes a number of current source cells coupled together in a parallel configuration, where the current source cells are configured to provide the tail current for the line driver in response to a digital control signal. The circuit can further include a digital core coupled to the adjustable current source, where the digital core provides the digital control signal. The digital control signal provides a number of bits, where each bit controls one of the current source cells. In one embodiment, a current source cell can comprise a number of current source sub-cells. The current source cells can be configured to provide the tail current for the line driver in response to the digital control signal when the line driver is operating in a class AB mode.

Abstract: A video data source system includes a video encoder and an analog back end device. The analog back end device includes a digital to analog converter and a post-stage driving unit. The video data source system adds the post-stage driving unit into the analog back end device and strengthens its driving ability by the post-stage driving unit.

Abstract: A background self-calibrated DAC is presented. A virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized.

Abstract: A signal converting system has a multi-segment digital to analog converter coupled to an error shaping loop. A control value is received at a vector processor that indicates a number N of elements that are to be selected from a vector having M elements. The elements of the vector are sorted into a bitonic sequence and separated into a larger value group and a smaller value group using a bitonic split. Only the larger value group is sorted into an ordered sequence with repeated bitonic splits when the control value is less than M/2, and N largest elements are selected from the ordered sequence. Only the smaller value group is sorted into an ordered sequence with repeated bitonic splits when the control value is greater than M/2, and N?M/2 largest elements are selected from the ordered sequence.

Abstract: A resistor string type D/A converter in accordance with an exemplary aspect of the present invention includes a resistor string, switches, a higher-order decoder, a lower-order decoder, and a conversion unit. The resistor string generates a plurality of analog voltages by dividing a voltage between a first reference voltage and a second reference voltage. Each of the switches is provided for a respective one of a plurality of voltage drawing points. The higher-order decoder generates a higher-order control signal according to the value of higher bits of an input digital signal. The lower-order decoder generates a lower-order control signal corresponding to the value of lower bits of the input digital signal. The conversion unit outputs a voltage between a pair of the analog voltage values obtained through a pair of switches based on the lower-order control signal.

Abstract: For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.

Abstract: A m-bit DAC outputs a voltage that is the result of interpolation from two reference voltages. The two reference voltages are selected, inclusive of redundant selection of the same reference voltage (inclusive also of reference voltages other than adjacent voltages) out of a plurality of reference voltages. The plurality of reference voltages are grouped into first to (3S+1)th groups (where S is a power of 2). An ith group includes [3S(j?1)+i]th reference voltages (where j=1, 2, . . . h, and h is a prescribed integer). The decoder includes (3S+1)th subdecoders, each selecting one voltage responsive to a first MSB group; and a (3S+1)-input and 2-output subdecoder for selecting two voltages, inclusive of redundant selection of the same reference voltage, out of (3S+1) voltages selected by the respective first to (3S+1)th subdecoders, responsive to a LSB group and outputs them to an interpolation amplifier (ratio 1:1).

Abstract: A potentiometer and a method for adjusting an impedance. In accordance with an embodiment, the potentiometer may be a programmable multistage digital potentiometer that has a first stage comprising a non-shunted impedance, a second stage coupled between a reference terminal and the first stage, and a third stage coupled between the first stage and another reference terminal. In accordance with another embodiment, the potentiometer receives a wiper address and parses it into sections such that one section controls the first stage, a second portion controls portions of the second and third stages, and a third portion controls the other portions of the second and third stages to produce a desired impedance between a common wiper terminal and the reference terminals.

Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: A digital-to-analog converter is disclosed. An example digital-to-analog converter circuit includes a reference scaling circuit coupled to receive a first reference current. The reference scaling circuit is coupled to generate a second reference current in response to the first reference current. The digital-to-analog converter circuit also includes a first plurality of binary-weighted current sources coupled to a summing node. A current of a first one of the first plurality of binary-weighted current sources is proportional to the first reference current. The digital-to-analog converter circuit also includes a second plurality of binary-weighted current sources coupled to the summing node. A current of a first one of the second plurality of binary-weighted current sources is proportional to the second reference current.

Abstract: A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

Abstract: A multi-input operational amplifier circuit operable with a high degree of accuracy and in a small area, a D/A converter using the multi-input operational amplifier circuit, and a drive circuit or driver for a display device, using the D/A converter. In embodiments of the multi-input operational amplifier circuit, a constant current source of a third differential amplifier circuit that causes a doubled constant current i×2 to flow with respect to constant current sources of first and second differential amplifier circuits by application of two types of bias voltages thereto is configured using PMOS of the same number and size. Therefore, operations equivalent to those of a conventional circuit may be realized by the three constant current source PMOSs, and a smaller chip size may be required.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A digital-to-analog converter generates a voltage from power supply and ground voltages, generates upper and lower limit reference voltages for a reference width which regards the generated voltage as an intermediate potential, converts a change in an analog input signal with respect to the upper and lower limit reference voltages into a digital code, and performs a control in order to achieve a sample and hold of the analog input signal.

Abstract: A resistor string digital to analog converter formed of polysilicon resistor segments to each of which is applied an electric field. The approach improves the overall accuracy.

Abstract: Embodiments related to echo compensation have been described and depicted.