Using Charge Coupled Devices Or Switched Capacitances Patents (Class 341/150)
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Patent number: 12191896Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.Type: GrantFiled: November 14, 2022Date of Patent: January 7, 2025Assignee: QUALCOMM IncorporatedInventors: Edward Wai Yeung Liu, Vladimir Aparin
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Patent number: 12176910Abstract: In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.Type: GrantFiled: October 17, 2023Date of Patent: December 24, 2024Assignee: Infineon Technologies AGInventors: Matteo Dalla Longa, Francesco Conzatti, Tobias Hofmann, John G. Kauffman, Maurits Ortmanns
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Patent number: 12034327Abstract: Deterioration of a power storage device is reduced. Switches that control the connections of a plurality of power storage devices separately are provided. The switches are controlled with a plurality of control signals, so as to switch between charge and discharge of each of the power storage devices or between serial connection and parallel connection of the plurality of power storage devices. Further, a semiconductor circuit having a function of carrying out arithmetic is provided for the power storage devices, so that a control system of the power storage devices or a power storage system is constructed.Type: GrantFiled: January 15, 2021Date of Patent: July 9, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Minoru Takahashi, Junpei Momo, Yutaka Shionoiri
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Patent number: 11983507Abstract: A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product.Type: GrantFiled: December 31, 2020Date of Patent: May 14, 2024Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Patent number: 11977936Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.Type: GrantFiled: December 31, 2020Date of Patent: May 7, 2024Assignee: Ceremorphic, Inc.Inventors: Martin Kraemer, Ryan Boesch, Wei Xiong
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Patent number: 11949769Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/? and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.Type: GrantFiled: May 2, 2022Date of Patent: April 2, 2024Assignee: Apple Inc.Inventors: Voravit Vorapipat, Morteza Nick, Krishna Chaitanya Reddy Gangavaram, Antonio Passamani
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Patent number: 11929759Abstract: A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.Type: GrantFiled: December 14, 2020Date of Patent: March 12, 2024Assignee: AMS INTERNATIONAL AGInventor: Thomas Fröhlich
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Patent number: 11817874Abstract: In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.Type: GrantFiled: May 31, 2022Date of Patent: November 14, 2023Assignee: Infineon Technologies AGInventors: Matteo Dalla Longa, Francesco Conzatti, Tobias Hofmann, John G. Kauffman, Maurits Ortmanns
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Patent number: 11784612Abstract: A signal detection circuit includes: a first capacitor having a first terminal connected with a first main terminal of a switching element; a second capacitor having a first terminal connected with a second main terminal of the switching element; and a detection circuit having a differential circuit configuration. The detection circuit receives, as input signals, a signal from a second terminal of the first capacitor and a signal from a second terminal of the second capacitor, detects detection target signals based on the input signals. The detection target signals include a signal of the first main terminal of the switching element and a signal of the second main terminal of the switching element.Type: GrantFiled: December 8, 2021Date of Patent: October 10, 2023Assignee: DENSO CORPORATIONInventors: Takasuke Itou, Tomohiro Nezuka, Yasuaki Aoki, Yuuta Nakamura, Takashi Yoshiya
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Patent number: 11757459Abstract: A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.Type: GrantFiled: February 17, 2022Date of Patent: September 12, 2023Assignee: Caelus Technologies LimitedInventor: Chi Fung Lok
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Patent number: 11616509Abstract: A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.Type: GrantFiled: November 24, 2021Date of Patent: March 28, 2023Assignee: Infineon Technologies AGInventors: Francesco Lombardo, Dmytro Cherniak, Luigi Grimaldi, Nicolo Guarducci
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Patent number: 11611349Abstract: Provided are an analog-to-digital (AD) converter, a sensor system, and a test system capable of reducing the time for test processing. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to test controller before first output part outputs the first digital data. In the test mode, test controller determines whether or not sensor system including sensor is in an abnormal state on the basis of the second digital data.Type: GrantFiled: March 13, 2020Date of Patent: March 21, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Koji Obata, Jun'ichi Naka, Junji Nakatsuka, Hiroki Yoshino, Masaaki Nagai
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Patent number: 11587925Abstract: A variable capacitance circuit includes a capacitor array having a first capacitor in which a plurality of MIM capacitors are coupled in parallel and a second capacitor in which a plurality of MIM capacitors are coupled in series, and a switch array having a first switch and a second switch. A shape pattern of at least one of a first electrode of the first capacitor, a first ground shield, a second electrode of the second capacitor, and a second ground shield is set so that a first capacitance difference per 1 LSB between first capacitance values of the first capacitor when the first switch is turned on and off and a second capacitance difference per 1 LSB between second capacitance values of the second capacitor when the second switch is turned on and off are close to each other.Type: GrantFiled: February 2, 2022Date of Patent: February 21, 2023Inventors: Atsushi Tanaka, Teppei Higuchi
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Patent number: 11539374Abstract: A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.Type: GrantFiled: August 30, 2021Date of Patent: December 27, 2022Assignee: Rambus Inc.Inventors: Ravi Shivnaraine, Marcus Van Ierssel
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Patent number: 11532359Abstract: A semiconductor device includes a level conversion circuit. The level conversion circuit includes a first transistor, a second transistor, a current limiting element, and a voltage adjusting circuit. The first transistor includes a gate connected to an input node. A signal corresponding to a first power supply voltage is input to the input node. The second transistor has a source connected to a drain of the first transistor, a drain connected to a second power supply voltage that is higher than the first power supply voltage, and a gate connected to a first node. The current limiting element is electrically connected between the first node and an output node. The voltage adjusting circuit adjusts a voltage of the first node in accordance with the signal input to the input node.Type: GrantFiled: February 16, 2021Date of Patent: December 20, 2022Assignee: KIOXIA CORPORATIONInventor: Osamu Kobayashi
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Patent number: 11462270Abstract: Nonvolatile memory device includes memory cell region including first metal pad, peripheral circuit region including second metal pad, memory cell array, input current generator, operation cell array and analog-to-digital converter. Peripheral circuit region is vertically connected by first and second metal pads. Memory cell array in memory cell region includes NAND strings storing multiplicand data, wherein first ends of NAND strings are connected to bitlines and second ends of NAND strings output multiplication bits corresponding to bitwise multiplication of multiplicand data stored in NAND strings and multiplier data loaded on bitlines. Input current generator generates input currents. Operation cell array in memory cell region includes switching transistors. Gate electrodes of switching transistors are connected to second ends of NAND strings. Switching transistors selectively sum input currents based on multiplication bits to provide output currents.Type: GrantFiled: September 3, 2020Date of Patent: October 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Se-Hwan Park
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Patent number: 11435767Abstract: A voltage regulation loop includes a voltage reference generation block that includes a bandgap voltage reference circuit; a linear voltage regulator block that includes a first and second linear voltage regulators, wherein the first linear voltage regulator provides a first regulated power supply to the bandgap voltage reference circuit in the voltage reference generation block, and the second linear voltage regulator provides a second regulated power supply to a load; and a soft startup circuit connected between the voltage reference generation block and the linear voltage regulator block, wherein a selector functions with a control block to output a selected voltage reference to pass to the soft startup circuit, wherein the soft startup circuit smooths the selected voltage reference and produces a smoothed voltage reference to pass to the linear voltage regulator block to prevent overshoots at startup.Type: GrantFiled: June 19, 2019Date of Patent: September 6, 2022Assignee: Vidatronic, Inc.Inventors: Bishoy Milad Helmy Zaky, Anand Veeravalli Raghupathy
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Patent number: 10985774Abstract: A delta-sigma modulator generates a bitstream signal from a differential input signal including a first input signal and a second input signal by repeating a first operation and a second operation alternately. The delta-sigma modulator includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, an operational amplifier, a first feedback capacitor, a second feedback capacitor, and a quantizer.Type: GrantFiled: July 2, 2020Date of Patent: April 20, 2021Assignee: Gwanak Analog CO., LTD.Inventors: Byunggyu Lee, Youngtae Yang
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Patent number: 10971230Abstract: A nonvolatile memory device includes a memory cell array, an input current generator, an operation cell array and an analog-to-digital converter. The memory cell array includes NAND strings storing multiplicand data, wherein first ends of the NAND strings are connected to bitlines and second ends of the NAND strings output multiplication bits corresponding to bitwise multiplication of the multiplicand data stored in the NAND strings and multiplier data loaded on the bitlines. The input current generator generates input currents. The operation cell array includes switching transistors. Gate electrodes of the switching transistors are connected to the second ends of the NAND strings. The switching transistors selectively sum the input currents based on the multiplication bits to output the output currents. The analog-to-digital converter converts the output currents to digital values.Type: GrantFiled: August 24, 2019Date of Patent: April 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Se-Hwan Park
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Patent number: 10958283Abstract: An AD conversion circuit includes a comparison circuit, a first DA conversion circuit including a plurality of resistance elements, and a first voltage output circuit. A comparator of the comparison circuit outputs a signal that represents a result of comparing a first voltage of a first input terminal with a second voltage of a second input terminal. A first combined resistance value of the first DA conversion circuit and the first voltage output circuit seen from a second terminal of the first capacitance element is a first value when the first capacitance element holds a first signal. The first combined resistance value is a second value when the comparator compares the first voltage with the second voltage. The first value is less than the second value.Type: GrantFiled: June 9, 2020Date of Patent: March 23, 2021Assignee: OLYMPUS CORPORATIONInventor: Yoshio Hagihara
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Patent number: 10951227Abstract: A multiplying digital to analog converter (MDAC) includes a first resistor configured to be selectively connected to a current output node based on a first bit of a first portion of an input digital code and a second resistor configured to be selectively connected to the current output node based on a second bit of the first portion of the input digital code. A resistance of the second resistor is a resistance of the first resistor scaled by a factor. The MDAC further includes a first capacitor configured to be selectively connected to the current output node based on the first bit of the first portion and a second capacitor configured to be selectively connected to the current output node based on the second bit of the first portion. A capacitance of the second capacitor is a capacitance of the first capacitor scaled by an inverse of the factor.Type: GrantFiled: December 23, 2019Date of Patent: March 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Rajavelu Thinakaran
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Patent number: 10848171Abstract: Apparatus and associated methods relate to providing a regulation loop using a digital representation of a loop error signal along with a flexible multiplying capacitive digital-to-analog converter (MC-DAC) circuit to control one or more power switches (e.g., transistors) delivering required power (including voltage and/or current) to a load circuit. In an illustrative example, the MC-DAC circuit may include a digital-to-analog converter (DAC) configured to selectively couple to two different reference voltages in response to switch control signals generated by a digital filter. A capacitive level shifter may be coupled to the output of the DAC. A re-sampling circuit may be coupled to the output of the capacitive level shifter to generate a gate control signal to control the one or more power switches. The regulation loop may advantageously generate the gate control signal using a substantially reduced die area.Type: GrantFiled: January 16, 2020Date of Patent: November 24, 2020Assignee: XILINX, INC.Inventors: Declan Carey, Frantz Stephane Florent Ngankem Ngankem, Pedro W. Neto, Ronan Casey
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Patent number: 10790843Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, successive approximation register (SAR) circuitries, and noise shaping circuitries. The capacitor arrays sample an input signal by turns, in order to provide a sampled input signal. The SAR circuitries perform an analog-to-digital conversion by turns according to a combination of the sampled input signal, a first residue signal, and a second residue signal, in order to generate digital outputs. The noise shaping circuitries receive a corresponding residue signal of the first residue signal the second residue signal in response to the analog-to-digital conversion, and to shape and transmit the corresponding residue signal to the SAR circuitries.Type: GrantFiled: November 1, 2019Date of Patent: September 29, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Shih-Hsiung Huang
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Patent number: 10727857Abstract: An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.Type: GrantFiled: September 4, 2019Date of Patent: July 28, 2020Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
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Patent number: 10600349Abstract: The present invention relates to a display apparatus which drives a display panel to display an image, and a driving circuit thereof. The display apparatus includes a timing controller configured to provide a control option having a value for compensating for pixel data and a gray scale, and a driving circuit configured to combines the control option and the pixel data and output an output voltage.Type: GrantFiled: May 5, 2016Date of Patent: March 24, 2020Assignee: Silicon Works Co., Ltd.Inventors: Hyun Ho Cho, Yong Ik Jung
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Patent number: 10587282Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.Type: GrantFiled: May 10, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
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Patent number: 10521035Abstract: A touch display device and a driving circuit are disclosed in which the driving circuit is included in the touch display device. The driving circuit may be capable of reducing a chip size and power consumption by configuring an amplifier disposed in an output terminal of a data voltage to be electrically coupled with a feedback capacitor through a switch, and enabling both display driving and touch sensing to be performed through ON/OFF control of the switch. Further, the accuracy and performance of touch sensing may be improved by adjusting an ON/OFF operation of a switch and the number of amplifiers electrically coupled with the feedback capacitor, and a circuit structure for touch driving may be further simplified by generating a load-free driving voltage output in a touch driving period using the amplifiers and a digital-to-analog converter within the driving circuit.Type: GrantFiled: October 25, 2017Date of Patent: December 31, 2019Assignee: LG Display Co., Ltd.Inventors: HyeongWon Kang, Beom-Jin Kim, HongJu Lee
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Patent number: 10461765Abstract: A successive approximation type AD converter includes an in-phase voltage detection and supply circuit that supplies an in-phase voltage obtained by impedance voltage division of a first input analog signal and a second input analog signal to a first capacitance DA converter and a second capacitance DA converter. The first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage, and the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage. After the sampling period ends, a comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of a successive approximation logic unit on the basis of a comparison result, and comparison processing is repeated.Type: GrantFiled: January 23, 2019Date of Patent: October 29, 2019Assignee: Hitachi, Ltd.Inventors: Yuki Furubayashi, Takashi Oshima
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Patent number: 10444929Abstract: The present disclosure provides a laser touch panel, a laser touch method for a laser touch panel, a laser touch display device, a laser touch display system and a laser touch panel. The laser touch panel includes a first conductive layer, a second conductive layer, and a light-induced resistance change material layer. The light-induced resistance change material layer is disposed between the first conductive layer and the second conductive layer and is electrically connected to the first conductive layer and the second conductive layer. The light-induced resistance change material layer is configured to generate a resistance change at a touch position subjected to laser irradiation.Type: GrantFiled: April 1, 2017Date of Patent: October 15, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE MULTIMEDIA TECHNOLOGY CO., LTD.Inventors: Bo Ban, Jianting Wang, Haiyan Wan, Naijia Guo
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Patent number: 10425097Abstract: A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample-and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.Type: GrantFiled: October 12, 2018Date of Patent: September 24, 2019Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Shih-Hsiung Huang, Chih-Lung Chen, Jie-Fan Lai, Chien-Ming Wu
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Patent number: 10411722Abstract: Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.Type: GrantFiled: October 23, 2018Date of Patent: September 10, 2019Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUSInventor: Hayun Cecillia Chung
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Patent number: 10348320Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)* a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.Type: GrantFiled: June 26, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
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Patent number: 10340939Abstract: A successive approximation register analog-to-digital converter with improved kick-back linearization includes a signal input terminal, a capacitive digital-to-analog converter, a first switch, and a second switch. The signal input terminal is configured to receive a signal to be digitized. The capacitive digital-to-analog converter includes a first capacitor array, a second capacitor array, and a coupling capacitor. The first capacitor array includes a plurality of capacitors. The second capacitor array includes a plurality of capacitors. The coupling capacitor connects the first capacitor array to the second capacitor array. The first switch is configured to switchably connect a bottom plate of each of the capacitors of the first capacitor array to the signal input terminal. The second switch is configured to conduct a voltage on the bottom plate of the coupling capacitor to the signal input terminal.Type: GrantFiled: May 9, 2018Date of Patent: July 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sabu Paul, Raghu Nandan Srinivasa
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Patent number: 10305452Abstract: A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.Type: GrantFiled: September 21, 2018Date of Patent: May 28, 2019Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Vincent Quiquempoix, Fabien Vaucher
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Patent number: 10097198Abstract: Disclosed is a successive-approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a capacitor-resistor hybrid digital-to-analog converter (DAC), and apply a low-power switching method and an input signal range scaling method to the DAC, thereby significantly reducing surface area and power consumption.Type: GrantFiled: November 16, 2017Date of Patent: October 9, 2018Assignees: SK Hynix Inc., SOGANG UNIVERSITY RESEARCH FOUNDATIONInventors: Seung Hoon Lee, Hee Wook Shin, Eun Chang Lee
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Patent number: 9979419Abstract: A front-end circuit includes a multiplexer, a circulator, reception ports, and variable filters. A port in the multiplexer is connected to an antenna. A port in the circulator is connected to a port in the multiplexer. The reception ports are connected to a port in the circulator with the variable filters interposed therebetween. The multiplexer outputs a communication signal having a frequency in a low band to the port and outputs a communication signal having a frequency in a middle band to a port. Each of the low band and the middle band includes a plurality of frequency bands. The middle band is a range of frequencies higher than those in the low band and does not overlap the low band.Type: GrantFiled: January 12, 2016Date of Patent: May 22, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hisao Hayafuji, Hidenori Obiya, Shinya Mizoguchi
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Patent number: 9893739Abstract: A SAR ADC is disclosed. The SAR ADC includes a plurality of SAR-capacitors. For each of the SAR-capacitors, a sampling-switching-block is configured to connect a first plate of the associated SAR-capacitor to either: v-ref-low, v-ref-high or an input-voltage. The SAR ADC also includes an offset-capacitor and an offset-switching-block configured to connect a first plate of the offset-capacitor to either: v-ref-low, or v-ref-high. The SAR ADC further includes a SAR machine configured to provide signals to the sampling-switching-blocks and the offset-switching-block in order to define a calibration-sampling-mode-of-operation, a calibration-conversion-mode-of-operation, a sampling-mode-of-operation and a conversion-mode-of-operation. A code converter is also includes and is configured to subtract the offset-value from the raw-digital-word in order to provide a digital-output-signal.Type: GrantFiled: May 23, 2017Date of Patent: February 13, 2018Assignee: NXP USA, INC.Inventor: Hubert Martin Bode
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Patent number: 9887703Abstract: A digital-to-analog converter (DAC) for converting an M bit digital value to an analog signal includes a capacitive DAC and a resistive DAC. The capacitive DAC is configured to convert N most significant bits of the digital value to an analog signal. The resistive DAC is configured to covert M-N least significant bits (LSBs) of the digital value to an analog signal. The resistive DAC includes a coarse DAC and a fine DAC. The coarse DAC is configured to convert a most significant R bits of the M-N least significant bits to an analog signal. An output of the coarse DAC is switchably coupled to a first capacitor of the capacitive DAC. The fine DAC is configured to convert M-N-R least significant bits of the M-N least significant bits to an analog signal. An output of the fine DAC is switchably coupled to a second capacitor of the capacitive DAC.Type: GrantFiled: May 19, 2017Date of Patent: February 6, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jun Zhang, Xuan Wang
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Patent number: 9712181Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.Type: GrantFiled: September 23, 2016Date of Patent: July 18, 2017Assignee: Analog Devices, Inc.Inventors: Baozhen Chen, Edward C. Guthrie, Michael C. W. Coln, Mark D. Maddox
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Patent number: 9667266Abstract: A voltage sampling circuit is provided that may directly connect a non-zero power supply voltage VDD to switching circuits during input voltage sampling, setting a common mode voltage without using reference voltages produced by a reference voltage generator circuit, and without requiring a common mode buffer circuit. The voltage sampling circuit may be used in an operational amplifier input stage such as for a pipelined ADC circuit, or in a comparator circuit. A SAR ADC circuit is also provided, comprising a control circuit, the voltage sampling circuit, a capacitor array, and a comparator circuit for comparing outputs occurring from charge redistributions. The voltage sampling circuit may enable increased power efficiency, avoid leakage concerns, and increase maximum input voltage swing. Reference plate switches in the voltage sampling circuit may include gate-boosted devices or thicker-oxide I/O devices.Type: GrantFiled: February 19, 2016Date of Patent: May 30, 2017Assignee: Analog Devices, Inc.Inventors: Junhua Shen, Michael C. W. Coln
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Patent number: 9641201Abstract: In accordance with an embodiment, a radio frequency integrated circuit (RFIC) includes an adjustable capacitance coupled to an input terminal of the RFIC, and a first single-pole multiple-throw (SPMT) radio frequency (RF) switch having an input coupled to the adjustable capacitance and a plurality of output nodes coupled to a corresponding plurality of second output terminals of the RFIC.Type: GrantFiled: April 29, 2014Date of Patent: May 2, 2017Assignee: Infineon Technologies AGInventors: Winfried Bakalski, Werner Simbuerger
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Patent number: 9484898Abstract: The system has: a set of at least two electric current generators, at least one capacitor and activation/deactivation devices for the electric current generators; the electric current generator being connected in parallel with one another and the capacitor being connected in series with the electric current generators, the activation/deactivation devices controlling the generators by a digital stream allowing control of the intensity of the electric current entering the capacitor and generating a trapezoidal voltage signal at the terminals of the capacitor, the analog signal being reconstructed through interpolation of the trapezoidal signal.Type: GrantFiled: May 19, 2014Date of Patent: November 1, 2016Assignees: THALES, CENTRE NATIONAL DE LA RECHERCE SCIENTIFIQUE, INSTITUT POLYTECHNIQUE DE BORDEAUX, UNIVERSITE DE BORDEAUXInventors: Patrick Garrec, Richard Montigny, Nicolas Regimbal, Yann Deval, François Rivet
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Patent number: 9397687Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.Type: GrantFiled: January 8, 2016Date of Patent: July 19, 2016Assignee: Cisco Technology, Inc.Inventors: Kadaba Lakshmikumar, Mark Y. Tse
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Patent number: 9276596Abstract: An analog to digital converting apparatus and an initial method thereof are provided. The analog to digital converting apparatus includes a first and a second switching capacitor units, a circuit unit, a first and a second initialization switches, a third and a fourth capacitors and a logic buffer. The first and the second switching capacitor units respectively couple first capacitors and second capacitors to a first logic voltage, a second logic voltage or a first or a second input voltage according to a first control signal, and respectively generate a first and a second voltage. The circuit unit compares the first voltage and the second voltage to generate the first control signal. The first and the second initialization switches are respectively connected in series between the first and the second voltage and a common-mode endpoint. The logic buffer outputs the first or the second logic voltage to the common-mode endpoint.Type: GrantFiled: June 1, 2015Date of Patent: March 1, 2016Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.Inventors: Xingbo Ding, Feng Xu, Min-Yuan Wu
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Patent number: 9258010Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.Type: GrantFiled: August 29, 2014Date of Patent: February 9, 2016Assignee: Cisco Technology, Inc.Inventors: Kadaba Lakshmikumar, Mark Y. Tse
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Patent number: 9252792Abstract: A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.Type: GrantFiled: May 12, 2014Date of Patent: February 2, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Rajavelu Thinakaran
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Patent number: 9218514Abstract: Provided is a switched-capacitor integrator, a method of operating the switched-capacitor integrator, and apparatuses including the switched-capacitor integrator. The switched-capacitor integrator including an amplifier including a first input terminal, a second input terminal, and an output terminal, a first capacitor disposed between the first input terminal and the output terminal, and a switched capacitor circuit configured to sample an input signal in response to control signals, and to integrate a difference between a feedback signal and the input signal while sampling the input signal.Type: GrantFiled: November 3, 2014Date of Patent: December 22, 2015Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation Hanyang University, Erica CampusInventors: Jong Jin Kim, Jeong Jin Roh, Young Hyun Yoon, Jun Whon Uhm, Dong Wook Kim
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Patent number: 9184623Abstract: A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described.Type: GrantFiled: April 23, 2015Date of Patent: November 10, 2015Assignee: XILINX, INC.Inventors: Ionut C. Cical, John K. Jennings
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Patent number: 9184763Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.Type: GrantFiled: August 12, 2014Date of Patent: November 10, 2015Assignee: Intel Deutschland GmbHInventors: Franz Kuttner, Michael Fulde
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Publication number: 20150138182Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.Type: ApplicationFiled: January 23, 2015Publication date: May 21, 2015Inventor: Nang-Ping TU