Using Charge Coupled Devices Or Switched Capacitances Patents (Class 341/150)
  • Patent number: 10848171
    Abstract: Apparatus and associated methods relate to providing a regulation loop using a digital representation of a loop error signal along with a flexible multiplying capacitive digital-to-analog converter (MC-DAC) circuit to control one or more power switches (e.g., transistors) delivering required power (including voltage and/or current) to a load circuit. In an illustrative example, the MC-DAC circuit may include a digital-to-analog converter (DAC) configured to selectively couple to two different reference voltages in response to switch control signals generated by a digital filter. A capacitive level shifter may be coupled to the output of the DAC. A re-sampling circuit may be coupled to the output of the capacitive level shifter to generate a gate control signal to control the one or more power switches. The regulation loop may advantageously generate the gate control signal using a substantially reduced die area.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 24, 2020
    Assignee: XILINX, INC.
    Inventors: Declan Carey, Frantz Stephane Florent Ngankem Ngankem, Pedro W. Neto, Ronan Casey
  • Patent number: 10790843
    Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, successive approximation register (SAR) circuitries, and noise shaping circuitries. The capacitor arrays sample an input signal by turns, in order to provide a sampled input signal. The SAR circuitries perform an analog-to-digital conversion by turns according to a combination of the sampled input signal, a first residue signal, and a second residue signal, in order to generate digital outputs. The noise shaping circuitries receive a corresponding residue signal of the first residue signal the second residue signal in response to the analog-to-digital conversion, and to shape and transmit the corresponding residue signal to the SAR circuitries.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 29, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 10727857
    Abstract: An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 28, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
  • Patent number: 10600349
    Abstract: The present invention relates to a display apparatus which drives a display panel to display an image, and a driving circuit thereof. The display apparatus includes a timing controller configured to provide a control option having a value for compensating for pixel data and a gray scale, and a driving circuit configured to combines the control option and the pixel data and output an output voltage.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: March 24, 2020
    Assignee: Silicon Works Co., Ltd.
    Inventors: Hyun Ho Cho, Yong Ik Jung
  • Patent number: 10587282
    Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10521035
    Abstract: A touch display device and a driving circuit are disclosed in which the driving circuit is included in the touch display device. The driving circuit may be capable of reducing a chip size and power consumption by configuring an amplifier disposed in an output terminal of a data voltage to be electrically coupled with a feedback capacitor through a switch, and enabling both display driving and touch sensing to be performed through ON/OFF control of the switch. Further, the accuracy and performance of touch sensing may be improved by adjusting an ON/OFF operation of a switch and the number of amplifiers electrically coupled with the feedback capacitor, and a circuit structure for touch driving may be further simplified by generating a load-free driving voltage output in a touch driving period using the amplifiers and a digital-to-analog converter within the driving circuit.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 31, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: HyeongWon Kang, Beom-Jin Kim, HongJu Lee
  • Patent number: 10461765
    Abstract: A successive approximation type AD converter includes an in-phase voltage detection and supply circuit that supplies an in-phase voltage obtained by impedance voltage division of a first input analog signal and a second input analog signal to a first capacitance DA converter and a second capacitance DA converter. The first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage, and the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage. After the sampling period ends, a comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of a successive approximation logic unit on the basis of a comparison result, and comparison processing is repeated.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 29, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Furubayashi, Takashi Oshima
  • Patent number: 10444929
    Abstract: The present disclosure provides a laser touch panel, a laser touch method for a laser touch panel, a laser touch display device, a laser touch display system and a laser touch panel. The laser touch panel includes a first conductive layer, a second conductive layer, and a light-induced resistance change material layer. The light-induced resistance change material layer is disposed between the first conductive layer and the second conductive layer and is electrically connected to the first conductive layer and the second conductive layer. The light-induced resistance change material layer is configured to generate a resistance change at a touch position subjected to laser irradiation.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 15, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE MULTIMEDIA TECHNOLOGY CO., LTD.
    Inventors: Bo Ban, Jianting Wang, Haiyan Wan, Naijia Guo
  • Patent number: 10425097
    Abstract: A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample-and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 24, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shih-Hsiung Huang, Chih-Lung Chen, Jie-Fan Lai, Chien-Ming Wu
  • Patent number: 10411722
    Abstract: Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 10, 2019
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUS
    Inventor: Hayun Cecillia Chung
  • Patent number: 10348320
    Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)* a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10340939
    Abstract: A successive approximation register analog-to-digital converter with improved kick-back linearization includes a signal input terminal, a capacitive digital-to-analog converter, a first switch, and a second switch. The signal input terminal is configured to receive a signal to be digitized. The capacitive digital-to-analog converter includes a first capacitor array, a second capacitor array, and a coupling capacitor. The first capacitor array includes a plurality of capacitors. The second capacitor array includes a plurality of capacitors. The coupling capacitor connects the first capacitor array to the second capacitor array. The first switch is configured to switchably connect a bottom plate of each of the capacitors of the first capacitor array to the signal input terminal. The second switch is configured to conduct a voltage on the bottom plate of the coupling capacitor to the signal input terminal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sabu Paul, Raghu Nandan Srinivasa
  • Patent number: 10305452
    Abstract: A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 28, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Vincent Quiquempoix, Fabien Vaucher
  • Patent number: 10097198
    Abstract: Disclosed is a successive-approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a capacitor-resistor hybrid digital-to-analog converter (DAC), and apply a low-power switching method and an input signal range scaling method to the DAC, thereby significantly reducing surface area and power consumption.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: October 9, 2018
    Assignees: SK Hynix Inc., SOGANG UNIVERSITY RESEARCH FOUNDATION
    Inventors: Seung Hoon Lee, Hee Wook Shin, Eun Chang Lee
  • Patent number: 9979419
    Abstract: A front-end circuit includes a multiplexer, a circulator, reception ports, and variable filters. A port in the multiplexer is connected to an antenna. A port in the circulator is connected to a port in the multiplexer. The reception ports are connected to a port in the circulator with the variable filters interposed therebetween. The multiplexer outputs a communication signal having a frequency in a low band to the port and outputs a communication signal having a frequency in a middle band to a port. Each of the low band and the middle band includes a plurality of frequency bands. The middle band is a range of frequencies higher than those in the low band and does not overlap the low band.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 22, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hisao Hayafuji, Hidenori Obiya, Shinya Mizoguchi
  • Patent number: 9893739
    Abstract: A SAR ADC is disclosed. The SAR ADC includes a plurality of SAR-capacitors. For each of the SAR-capacitors, a sampling-switching-block is configured to connect a first plate of the associated SAR-capacitor to either: v-ref-low, v-ref-high or an input-voltage. The SAR ADC also includes an offset-capacitor and an offset-switching-block configured to connect a first plate of the offset-capacitor to either: v-ref-low, or v-ref-high. The SAR ADC further includes a SAR machine configured to provide signals to the sampling-switching-blocks and the offset-switching-block in order to define a calibration-sampling-mode-of-operation, a calibration-conversion-mode-of-operation, a sampling-mode-of-operation and a conversion-mode-of-operation. A code converter is also includes and is configured to subtract the offset-value from the raw-digital-word in order to provide a digital-output-signal.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 13, 2018
    Assignee: NXP USA, INC.
    Inventor: Hubert Martin Bode
  • Patent number: 9887703
    Abstract: A digital-to-analog converter (DAC) for converting an M bit digital value to an analog signal includes a capacitive DAC and a resistive DAC. The capacitive DAC is configured to convert N most significant bits of the digital value to an analog signal. The resistive DAC is configured to covert M-N least significant bits (LSBs) of the digital value to an analog signal. The resistive DAC includes a coarse DAC and a fine DAC. The coarse DAC is configured to convert a most significant R bits of the M-N least significant bits to an analog signal. An output of the coarse DAC is switchably coupled to a first capacitor of the capacitive DAC. The fine DAC is configured to convert M-N-R least significant bits of the M-N least significant bits to an analog signal. An output of the fine DAC is switchably coupled to a second capacitor of the capacitive DAC.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jun Zhang, Xuan Wang
  • Patent number: 9712181
    Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 18, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Baozhen Chen, Edward C. Guthrie, Michael C. W. Coln, Mark D. Maddox
  • Patent number: 9667266
    Abstract: A voltage sampling circuit is provided that may directly connect a non-zero power supply voltage VDD to switching circuits during input voltage sampling, setting a common mode voltage without using reference voltages produced by a reference voltage generator circuit, and without requiring a common mode buffer circuit. The voltage sampling circuit may be used in an operational amplifier input stage such as for a pipelined ADC circuit, or in a comparator circuit. A SAR ADC circuit is also provided, comprising a control circuit, the voltage sampling circuit, a capacitor array, and a comparator circuit for comparing outputs occurring from charge redistributions. The voltage sampling circuit may enable increased power efficiency, avoid leakage concerns, and increase maximum input voltage swing. Reference plate switches in the voltage sampling circuit may include gate-boosted devices or thicker-oxide I/O devices.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 30, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Junhua Shen, Michael C. W. Coln
  • Patent number: 9641201
    Abstract: In accordance with an embodiment, a radio frequency integrated circuit (RFIC) includes an adjustable capacitance coupled to an input terminal of the RFIC, and a first single-pole multiple-throw (SPMT) radio frequency (RF) switch having an input coupled to the adjustable capacitance and a plurality of output nodes coupled to a corresponding plurality of second output terminals of the RFIC.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Werner Simbuerger
  • Patent number: 9484898
    Abstract: The system has: a set of at least two electric current generators, at least one capacitor and activation/deactivation devices for the electric current generators; the electric current generator being connected in parallel with one another and the capacitor being connected in series with the electric current generators, the activation/deactivation devices controlling the generators by a digital stream allowing control of the intensity of the electric current entering the capacitor and generating a trapezoidal voltage signal at the terminals of the capacitor, the analog signal being reconstructed through interpolation of the trapezoidal signal.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: November 1, 2016
    Assignees: THALES, CENTRE NATIONAL DE LA RECHERCE SCIENTIFIQUE, INSTITUT POLYTECHNIQUE DE BORDEAUX, UNIVERSITE DE BORDEAUX
    Inventors: Patrick Garrec, Richard Montigny, Nicolas Regimbal, Yann Deval, François Rivet
  • Patent number: 9397687
    Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 19, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Kadaba Lakshmikumar, Mark Y. Tse
  • Patent number: 9276596
    Abstract: An analog to digital converting apparatus and an initial method thereof are provided. The analog to digital converting apparatus includes a first and a second switching capacitor units, a circuit unit, a first and a second initialization switches, a third and a fourth capacitors and a logic buffer. The first and the second switching capacitor units respectively couple first capacitors and second capacitors to a first logic voltage, a second logic voltage or a first or a second input voltage according to a first control signal, and respectively generate a first and a second voltage. The circuit unit compares the first voltage and the second voltage to generate the first control signal. The first and the second initialization switches are respectively connected in series between the first and the second voltage and a common-mode endpoint. The logic buffer outputs the first or the second logic voltage to the common-mode endpoint.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: March 1, 2016
    Assignees: FARADAY TECHNOLOGY CORPORATION, Faraday Technology Corp.
    Inventors: Xingbo Ding, Feng Xu, Min-Yuan Wu
  • Patent number: 9258010
    Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: February 9, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Kadaba Lakshmikumar, Mark Y. Tse
  • Patent number: 9252792
    Abstract: A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: February 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajavelu Thinakaran
  • Patent number: 9218514
    Abstract: Provided is a switched-capacitor integrator, a method of operating the switched-capacitor integrator, and apparatuses including the switched-capacitor integrator. The switched-capacitor integrator including an amplifier including a first input terminal, a second input terminal, and an output terminal, a first capacitor disposed between the first input terminal and the output terminal, and a switched capacitor circuit configured to sample an input signal in response to control signals, and to integrate a difference between a feedback signal and the input signal while sampling the input signal.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: December 22, 2015
    Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation Hanyang University, Erica Campus
    Inventors: Jong Jin Kim, Jeong Jin Roh, Young Hyun Yoon, Jun Whon Uhm, Dong Wook Kim
  • Patent number: 9184763
    Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 10, 2015
    Assignee: Intel Deutschland GmbH
    Inventors: Franz Kuttner, Michael Fulde
  • Patent number: 9184623
    Abstract: A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: November 10, 2015
    Assignee: XILINX, INC.
    Inventors: Ionut C. Cical, John K. Jennings
  • Publication number: 20150138182
    Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 21, 2015
    Inventor: Nang-Ping TU
  • Patent number: 9019137
    Abstract: A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 28, 2015
    Assignee: IQ-Analog Corporation
    Inventors: Mikko Waltari, Michael Kappes
  • Patent number: 8994567
    Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 31, 2015
    Assignee: Broadcom Europe Limited
    Inventors: Jonathan Ephraim David Hurwitz, Steven Collins
  • Patent number: 8976051
    Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ljudmil Anastasov, Jens Barrenscheen
  • Publication number: 20150054666
    Abstract: A current memory cell includes an amplifier, transistor, first and second capacitors, and first to third switching units. The amplifier includes first to third terminals. The transistor is coupled to first and second nodes, and ground. The first capacitor is coupled between the second node and ground. The second capacitor is coupled between a third node and ground. The first unit couples a current source to the first node during a first period and an output line to the first node during a second period. The second unit couples the first node to the second node during the first period. The third unit couples the first terminal to the second node and couples the second and third terminals to the third node during the first period, and couples the first terminal to the third node and couples the second and third terminals to the second node during the second period.
    Type: Application
    Filed: March 13, 2014
    Publication date: February 26, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Bo-Yeon Kim, Oh-Jo Kwon, Hee-Sun Ahn, Won-Tae Choi
  • Patent number: 8964074
    Abstract: An amplification circuit includes an amplifier, a first capacitor including a first terminal connected to an input terminal of the amplifier, a second capacitor including a first terminal connected to the input terminal of the amplifier and a second terminal connected to an output terminal of the amplifier, and a correction unit configured to correct a difference in bias dependency between capacitance values of the first and second capacitors.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Masanori Ogura
  • Patent number: 8957799
    Abstract: A current memory cell includes an amplifier, transistor, first and second capacitors, and first to third switching units. The amplifier includes first to third terminals. The transistor is coupled to first and second nodes, and ground. The first capacitor is coupled between the second node and ground. The second capacitor is coupled between a third node and ground. The first unit couples a current source to the first node during a first period and an output line to the first node during a second period. The second unit couples the first node to the second node during the first period. The third unit couples the first terminal to the second node and couples the second and third terminals to the third node during the first period, and couples the first terminal to the third node and couples the second and third terminals to the second node during the second period.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 17, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo-Yeon Kim, Oh-Jo Kwon, Hee-Sun Ahn, Won-Tae Choi
  • Patent number: 8928506
    Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: January 6, 2015
    Assignee: MaxLinear, Inc.
    Inventors: Raja Pullela, Curtis Ling
  • Publication number: 20140347203
    Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Franz Kuttner, Michael Fulde
  • Patent number: 8884797
    Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chow Peng, Jui-Cheng Huang, Ching-Ho Chang, Nang Ping Tu
  • Publication number: 20140328429
    Abstract: One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of unit cells arranged in rows and columns. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the unit cells to an output of the DAC. The number of unit cells which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventors: Franz Kuttner, Michael Fulde
  • Patent number: 8872691
    Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Keysight Technologies, Inc.
    Inventor: Dusan Stepanovic
  • Patent number: 8872686
    Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Yu Chou, Wei Lun Tao, Shang-Fu Yeh, Yi-Che Chen, Calvin Yi-Ping Chao
  • Patent number: 8860597
    Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Matthew D. Sienko
  • Patent number: 8860600
    Abstract: Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Jun Yang
  • Patent number: 8836559
    Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Franz Kuttner, Michael Fulde
  • Publication number: 20140253355
    Abstract: A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 11, 2014
    Inventor: Vincent Quiquempoix
  • Publication number: 20140253354
    Abstract: A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Inventor: Vincent Quiquempoix
  • Patent number: 8830100
    Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Seiko Nakamoto, Junya Nakanishi
  • Patent number: 8830101
    Abstract: According to some embodiments, a digital to analog converter comprises an array of input data streams. An array of differential MOS switches are all biased by a common tail current source. A data stream combiner combines and selects at each clock cycle the correct bit. Only one transistor from the switches conducts current at any time. The duration during which a switch conducts current is independent upon the fronts of the bits from the input data streams, thus rendering the switching code independent.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: September 9, 2014
    Inventor: Ion E. Opris
  • Patent number: 8803721
    Abstract: A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 12, 2014
    Assignee: Analog Devices, Inc.
    Inventors: William T. Boles, Michael R. Elliott
  • Patent number: 8773297
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The hybrid finite impulse response filter/digital to analog converter uses N-taps implemented digitally and N-tap weights implemented in analog using switched capacitors.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen