Abstract: A digital-to-analog converter circuit is configured to convert an m-bit digital signal into an analog signal. The circuit includes a bit voltage generator convert each bit of segmented n-bit units of the digital signal into a first voltage or a second voltage, first capacitors each configured to store the voltage for each bit output from the bit voltage generator, switches connected to the first capacitors, a second capacitor connected to the switches, an output unit configured to output the voltage stored in the second capacitor as an analog signal, and a control unit configured to control the switches, connect in parallel the first capacitors with the second capacitor, and adjust the voltage stored in the second capacitor.

Abstract: An analog-to-digital (AD) converter device, includes: a capacitive digital-to-analog converter (DAC) including a reference capacitor group having capacitors which are weighted with a ratio, one terminal of each of the capacitors being coupled to a common signal line, the other terminal of each of the capacitors being coupled to one of reference power supplies via one of switches; a comparator to compare a voltage of the common signal line with a reference voltage; a successive approximation routine circuit to control the switches based on a comparison result of the comparator; an offset correction circuit to correct an offset of the comparator; and a DAC correction circuit to correct an error in a voltage change of the common signal line, the offset correction circuit and the DAC correction circuit performing a correction so that a residual offset of the comparator and a residual error of the capacitive DAC cancel.

Abstract: A multiplying digital-to-analog converter (MDAC) is provided. The MDAC includes a sub DAC decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit. The capacitor-switch circuit includes at least two sampling capacitor sets which are coupled in parallel. The number of sampling capacitors in one of the sampling capacitor sets is larger than or equal to two. Each sampling capacitor set is coupled to an analog-signal input quantity through a sampling switch and to a corresponding output terminal of the sub DAC decoding circuit through a decoding switch. The sub DAC decoding circuit decodes a digital quantity and outputs a corresponding analog signal at each output terminal, such that the corresponding analog signals are applied to the respective sampling capacitor sets through the decoding switches and summed by the respective sampling capacitor sets to obtain an analog-signal quantity corresponding to the digital quantity.

Abstract: An A/D converter includes a capacitive DAC configured to perform conversion of high-order bits by receiving a differential signal, a resistive DAC configured to perform conversion of low-order bits, a resistive correction DAC configured to operate to correct the capacitive DAC, and a comparator. The capacitive DAC includes a positive-side capacitive DAC and a negative-side capacitive DAC operating in a complementary fashion, and the comparator, which includes a plurality of differential circuits, is configured to compare output potentials of the positive-side capacitive DAC and the negative-side capacitive DAC. The positive-side capacitive DAC and the negative-side capacitive DAC include first capacitive elements each formed from interconnect layers excluding an uppermost interconnect layer, and the comparator includes second capacitive elements each provided between adjacent ones of the differential circuits and formed from interconnect layers including the uppermost interconnect layer.

Abstract: A digital signal power amplification apparatus with multiple digital amplification cells connected in series, each amplification cell processing a separate bit of the digital signal. The apparatus additively combines the output from each amplifier into a single amplified signal without the use of separate signal combining circuitry. The apparatus has high linearity, high efficiency, high bandwidth and high power.

Abstract: A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.

Abstract: A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.

Abstract: A digital-to-analog converter (DAC) uses thermometer coding over a certain code range. A switch array for the certain code range is implemented into a smaller area of the integrated circuit die so as to take advantage of the lower gradient inherent in the smaller area. By implementing the certain input code range into the smaller switch array area, further improved linearity in that input code range is achieved at the expense of worse linearity in the other input code ranges, but without increasing power consumption and/or chip-area of the integrated circuit die.

Abstract: A class D amplifier is configured to accept a digital input signal wherein the control loop of the class D amplifier employs a hybrid filter merged with the front-end of a sigma-delta ADC converter. The term hybrid refers to the filter using both digital and analog components in which the digital delay elements serve as shift registers while the filter coefficients are analog. The filter converts the digital PDM data into a step-wise sinusoidal signal. The sigma-delta ADC receiving a feedback signal subtracts the step-wise sinusoidal signal from the continuous sinusoidal signal and converts the result to a digital PDM signal, without decimation, which passes through a digital filter, a PWM generator, and a pre-driver, to provide power to the load.

Abstract: A switchable capacitive element having an adjustable capacitance and an improved quality factor is specified. To this end, the characteristic variables of the switchable capacitive element are optimized in accordance with the equations cited in the description.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.

Abstract: A cyclic digital-to-analog converter includes a first capacitor and a second capacitor. Switching circuitry is selectively configurable to connect the first and second capacitors is at least two modes of operation, wherein a first mode uses the first capacitor during conversion of a bit as a sampling capacitor and uses the second capacitor during conversion of that bit as a holding capacitor, and wherein a second mode uses the second capacitor during conversion of a bit as a sampling capacitor and uses the first capacitor during conversion of that bit as a holding capacitor. A controller swaps converter operation between the first and second modes based on the bit values of a digital word to be converted. If adjacent bits of the digital word to be converted have different logical values, the converter swaps from the first mode to the second mode (or from the second mode to the first mode). Otherwise, the converted remains in the current first or second mode.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Abstract: A digital-to-analog converter includes a current source cell that converts an input digital signal into an analog signal and outputs the analog signal. The digital-to-analog converter includes a first output terminal at which a first analog signal is output. The digital-to-analog converter includes a second output terminal at which a second analog signal is output, the second analog signal being complementary to the first analog signal. The digital-to-analog converter includes a first load resistor connected between a second potential and the first output terminal, the second potential being different from a first potential. The digital-to-analog converter includes a second load resistor connected between the second potential and the second output terminal.

Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.

Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: Some embodiments include apparatus and methods having an amplifier, a capacitor network coupled to the amplifier, and switching circuitry coupled to the amplifier and the capacitor network. The switching circuit is configured to successively apply a selected reference voltage selected from among a first reference voltage, a second reference voltage, and a third reference voltage to the capacitor network in response to a digital input code to generate an output voltage. Additional embodiments are disclosed.

Abstract: The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.

Abstract: A digital-to-analog conversion device is disclosed. The digital-to-analog conversion device comprises a variable delay buffer circuit and a plurality of synchronization circuits. The buffer circuit receives a digital signal with a plurality of bits and sequentially outputs a plurality of first complementary digital signal sets delayed according to the order of from MSB to LSB. Each synchronization circuit receives the first complementary digital signal set and a clock signal, uses the clock signal as the timing reference of the first complementary digital signal set, and outputs a second complementary digital signal set corresponding to the first complementary digital signal set to a digital-to-analog conversion unit, so as to convert the second complementary digital signal sets into an analog signal. The present invention uses the delays respectively corresponding to different input bits to control the timing of current switches, whereby the transient glitches are reduced.

Abstract: An analog-to-digital converter that uses a comparator based asynchronous binary search is described. The architecture includes a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator only, for example to the first or root comparator. The at least one comparator is further arranged for controlling at least one other comparator of the plurality of comparators.

Abstract: Provided is an output apparatus comprising a plurality of current sources; a plurality of holding sections that correspond respectively to the current sources and that each hold a designated voltage that designates a current flowing through the corresponding current source; a setting DAC that sequentially generates the designated voltage to be held by each holding section; and a supply section that sequentially switches a supply of the designated voltage generated by the setting DAC among corresponding holding sections.

Abstract: Provided are a capacitor digital-to-analog (DAC), an analog-to-digital converter (ADC) including the capacitor DAC, and a semiconductor device. The DAC includes at least one dummy capacitor configured to cause capacitors included in a capacitor array to have a capacitance that is an integer multiple of the capacitance of a unit capacitor.

Abstract: A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates to form the capacitor. Each of the plurality of metal plates includes a driven plate and a common plate. The method also includes generating a plurality of interconnects in the common plate and extending the driven plate over the plurality of interconnects. Further, the method includes shielding the common plate by the driven plate. The system includes an analog to digital converter. The analog to digital converter also includes capacitor based digital to analog converter and digital logic for controlling digital operations in the analog to digital converter. The capacitor based digital to analog converter includes a plurality of capacitors, and a comparator for comparing the analog output from the digital to analog converter with a ground potential.

Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.

Abstract: Traditionally, successive approximation register (SAR) analog-to-digital converters (ADCs) using binary search algorithms have consumed power by performing unnecessary switching of a capacitive digital-to-analog converter (CDAC) when a CDAC voltage is relatively close to a sampling analog input signal. Here, a SAR ADC is provided that reduces the number of switching events. To accomplish this, a multi-stage comparator is provided that generates multiple output signals for SAR logic. Based on these outputs, the SAR logic can more efficiently switch its CDAC using a ternary search algorithm to reduce power consumption and improve efficiency.

Abstract: For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors.

Abstract: A D/A converter comprises a first switch unit for performing switching to provide connection and disconnection between one terminals of the plurality of sampling capacitive elements and the corresponding plurality of input terminals, and to provide connection and disconnection between the other terminals of the plurality of sampling capacitive elements and a reference voltage source for generating a reference voltage; a second switch unit for performing switching to provide connection and disconnection between the other terminals and an inverting input terminal of the operational amplifier, to provide connection and disconnection between one terminals of the sampling capacitive elements and to close and open an electric path through which a voltage according to a voltage of the sampling capacitive elements, is output to an output terminal of the operational amplifier, in accordance with the switching of the first switch unit; and a resistive element provided on the electric path.

Abstract: A DAC circuit using a charge subtraction method and a change transfer interpolation method includes resistor cells configured to divide a voltage of data of total K bits (=upper M bits+lower N bits) by resistance dividers; a decoder group configured to receive digital data of the M bits and the N bits divided in the resistor cells, process the digital data by the unit of 2 bits, and output respective corresponding voltages; a capacitor group configured to receive the voltages outputted from the decoder group and realize charge charging by a charge subtraction method and charge transferring by a charge transfer interpolation method; and an operational amplifier having a first input terminal which receives a reference voltage and a second input terminal which receives an interpolation voltage corresponding to an amount of charges transferred from the capacitor group, and configured to generate an output voltage.

Abstract: Provided is a DA conversion apparatus comprising a capacitor array DA converter that outputs to an output line an output voltage corresponding to a digital value input thereto; and a load changing section that changes a size of a load capacitance connected to the output line. The load changing section may set gain of the DA conversion apparatus with the size of the load capacitance connected to the output line being a constant capacitance unaffected by the digital value. The load changing section may include a load capacitor connected between the output line and a standard potential; a load-side switch connected in series with the load capacitor between the output line and the standard potential; and a load capacitance control section that controls the load-side switch.

Abstract: A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized.

Abstract: Systems and methods for a digital-to-charge converter (“DQC”) are disclosed. A DQC may include a converting circuit configured to receive a first digital signal indicative of a voltage across a capacitor coupled to an output pin of the digital-to-charge converter and to determine a present charge of the capacitor based at least in part on the first digital signal. The DQC may also include an error determining circuit coupled to the converting circuit, wherein the error determining circuit is configured to receive a second digital signal indicative of a target charge via an input pin of the digital-to-charge converter and to determine a difference between the target charge and the present charge. The DQC may further include a correction circuit coupled to the error determining circuit and configured to control a programmable current source to produce an analog signal at the output pin in response to the determined difference.

Abstract: A digital-to-analog converter generates a voltage from power supply and ground voltages, generates upper and lower limit reference voltages for a reference width which regards the generated voltage as an intermediate potential, converts a change in an analog input signal with respect to the upper and lower limit reference voltages into a digital code, and performs a control in order to achieve a sample and hold of the analog input signal.

Abstract: A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Abstract: This invention provides a digital-analog converter circuit capable of appropriately correcting the optical characteristics of the liquid crystals according to the change in design or the preference of the user, and achieving goals of miniaturization, cost-lowering, as well as wide design suitability. The digital-analog converter circuit includes a storage device for storing a voltage characteristic curve, a modulating device for generating a frequency signal in accordance with a data from the voltage characteristic curve stored in the storage device in response to a selected data, a variable resistance device connected between a first power source and a second power source, in which the resistance value of the variable resistance device is changed in accordance with the frequency signal from the modulating device, a holding device for holding a voltage generated at the variable resistance device, and an output device for outputting the voltage to a desired output end.

Abstract: A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N?n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.

Abstract: A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.

Abstract: In one embodiment, the DAC includes an analog gray voltage generation unit configured to generate a plurality of analog gray voltages, and a first decoder configured to select two different voltages of the plurality of the gray voltages as a first level voltage and a second level voltage, respectively, in response to an upper K-bits of N-bit input image data. Here, N may be an integer not less than two, and K may be an integer less than N. A second decoder may be configured to repeatedly distribute the first level voltage and the second level voltage to output a plurality of distributed voltages in response to a lower L-bits of the N-bit input image data. Here, L may be equal to N subtracted by K, and L may be less than K. An interpolated voltage generation unit may be configured to generate an interpolated voltage based on the plurality of distributed voltages.

Abstract: A digital-to-analog upconverter directly converts a baseband digital value comprising a plurality of bits to an RF analog signal to combine digital-to-analog operations with frequency upconversion operations. One exemplary digital-to-analog upconverter comprises a plurality of conversion units, one for each of the plurality of bits in the baseband digital value, and an output node coupled to each of the conversion units. Each conversion unit generates a weighted analog signal at a low frequency or at a radio frequency responsive to the corresponding input bit and an oscillator signal at RF. The weighting factor of each conversion unit corresponds to a relative weighting of the corresponding bit. The output node combines the weighted analog signals to generate a combined RF analog signal representative of the baseband digital value.

Abstract: A digital-to-analog converter includes an operational amplifying circuit, a switched capacitor circuit, an R-string sub-circuit, and a direct-charge transfer circuit. The operational amplifying circuit has a pair of differential input ends and a pair of differential output ends. The switched capacitor circuit is coupled to the pair of differential input ends of the operational amplifying circuit. The R-string sub-circuit is coupled to the switched capacitor circuit and the pair of differential input ends of the operational amplifying circuit. The direct-charge transfer circuit is coupled to the pair of differential input ends and the pair of differential output ends of the operational amplifying circuit.

Abstract: A D/A converter includes plus-side and minus-side input terminals; plus-side and minus-side D/A converters each including plural plus-side or minus-side capacitors having capacitance values weighted by the powers of two, a plus-side or minus-side output terminals connected to first electrodes of the plus-side or minus-side capacitors, and plural plus-side or minus-side switches for connecting each second electrode of the plus-side or minus-side capacitors to either the plus-side or minus-side input terminal, a plus-side reference voltage terminal or a minus-side reference voltage terminal according to plus-side or minus-side control digital signals; and plural short-circuit switches provided between identically weighted plus-side and minus-side capacitors respectively.

Abstract: A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.

Abstract: Provided is a signal generating apparatus that outputs from an output end thereof an output voltage corresponding to input data supplied thereto, comprising: a DA converter that outputs a voltage corresponding to data supplied thereto; a capacitor section that is provided between the output end and a standard potential; a transmission switch that provides a connection or a disconnect between a voltage generating end of the DA converter and the output end; and a control section that causes the DA converter to charge the capacitor section with a voltage corresponding to the input data by repeatedly connecting and disconnecting the transmission switch, thereby causing the voltage of the capacitor section to gradually approach the output voltage corresponding to the input data.

Abstract: A digital-to-analog converter includes an operational amplifying circuit, a switched capacitor circuit, an R-string sub-circuit, and a direct-charge transfer circuit. The operational amplifying circuit has a pair of differential input ends and a pair of differential output ends. The switched capacitor circuit is coupled to the pair of differential input ends of the operational amplifying circuit. The R-string sub-circuit is coupled to the switched capacitor circuit and the pair of differential input ends of the operational amplifying circuit. The direct-charge transfer circuit is coupled to the pair of differential input ends and the pair of differential output ends of the operational amplifying circuit.

Abstract: A receiver supporting a plurality of radio communication systems having different specifications includes a setting unit, a clock generation circuit, a voltage-current conversion amplifier, a switch, integrators, an AD conversion circuit, and a feedback circuit. The setting unit sets a value suitable for a carrier frequency used in one selected radio communication system. The clock generation circuit generates a first clock having a first frequency and a second clock having a second frequency. The conversion amplifier converts an input voltage signal into a current signal. The switch switches between connection and disconnection modes in accordance with the first clock to output the current signal. Each integrator operates in accordance with the second clock and includes two or more switched capacitor circuits and an operational amplifier. The AD conversion circuit converts a signal supplied from the preceding integrator into digital form. The feedback circuit operates in accordance with the second clock.

Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.

Abstract: A method of providing a value for each element of a sequence of elements in a converter, the values being for a present conversion cycle in operation of the converter, wherein a pointer position identifies an element in the sequence of elements for a conversion cycle.