Abstract: A modified lossy integrator digital-to-analog converter includes an amplifier (46) that receives an input on a summing node (48) and provides an output on a node (52). A feedback capacitor (50) is disposed across the input and output and has an output switched-capacitor (54) disposed in parallel therewith to passively distribute the charge thereacross. Switches (60) and (66) are operable to control the switching operation of the capacitor (54). Two input switched capacitors (70) and (94) are controlled by associated switches to switch charge onto the summing node (48) in a first clock cycle .phi..sub.2. A one-bit data stream modulates the operation such that either the charge from the capacitor (78) is dumped onto the summing node (48) or the charge from the capacitor (94) is dumped onto the summing node (48). This operation during the .phi..sub.2 cycle provides an integrated output that is slew-limited.

Abstract: In a DA converting circuit using a PAM circuit and low pass filters, an analogue signal of high quality can be obtained by removing ringing due to the cut-off frequency of the filters. A PAM signal outputted by the PAM circuit is switched on and off by a plurality of electronic switches arranged in parallel. Further outputs thereof are combined by an adding circuit through a plurality of LPFs to obtain a synthesized analogue signal. The inputs and the outputs of the LPFs described above are turned on and off by a plurality of electronic switches linked with each other. The different switches are driven by pulses produced from a clock signal, corresponding to a sampling frequency for the PAM circuit.

Abstract: A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node.

Abstract: A switched capacitor one-bit digital-to-analog converter is preferably utilized in the feedback path of a sigma delta modulator. The one-bit digital-to-analog converter includes first and second capacitors, a first switching circuit for coupling charge from a reference source to the capacitors, and a second switching circuit for coupling charge from the capacitors to positive and negative outputs, such as the summing junction of an operational amplifier. The switches in the second switching circuit have a cross-coupled configuration and are controlled by data dependent control signals. The data dependent control signals are structured such that charge is coupled from the capacitors to the summing junction on both clock phases, regardless of the state of the data. As a result, the sizes of the capacitors can be reduced by a factor of two for the same charge transfer.

Abstract: A programmable PD servo compensator has the transfer function of the combination of a standard PD compensator in tandem with a second order low pass filter. The programmable PD servo compensator consists simply of a biquad filter having a single complex zero and a pair of conjugate complex poles. This servo compensator is comprised of two tandem connected operational amplifiers, each with a capacitor connected output to input across it. The tandem connection is effected by one switched-capacitor resistor between the output of the first amplifier to the input of the second. Another switched-capacitor resistor is connected between the PD compensator input and the input of the first amplifier. Yet another switched capacitor is connected between the PD compensator output and the input of the first amplifier.

Abstract: A multi-mode digital to analog converter for converting a digital input into an analog voltage according to a linear or a companding transfer function. The converter comprises a charge redistribution device for creating an analog voltage at a node and switching circuitry for controlling the charge redistribution device. The switching circuitry is operable to effect either transfer function responsive to its inputs.

Abstract: The present invention provides a compact and robust architecture and a corresponding method to implement a monotonic algorithmic D/A converter that processes the bits of the digital input in the order from MSB to LSB, and a successive approximation A/D converter employing the intermediate conversion results of this D/A converter. The invention is aimed at applications requiring a dense integration in general VLSI technologies of multiple D/A and A/D converters, where individual trimming of components to compensate for component offsets and mismatches is virtually impossible. The architecture comprises four charge holding components, one switch for charge sharing, two bi-directional replication elements for charge storage and recall, and one comparator. Also described is an efficient way of performing pseudo-logarithmic compression of conversion values merely by adjusting the relative sizes of two of the charge holding components.

Abstract: A digital-to-analog converter includes a delta-sigma modulator (10) that receives a digital input and converts it to a one-bit digital output stream. A fourth order switched-capacitor filter (12) is operable to receive the one-bit digital stream and convert it to an analog value int he sampled data domain. This is input to a switched-capacitor/continuous time buffer (14) which is then filtered by an active low pass filter (18) to provide an analog output. The switched-capacitor filter (12) includes four stages of integration (24), (30), (34) and (38). A one-bit DAC (20) is provided for converting the one-bit digital stream to an analog value. The one-bit DAC (20) is integral with the first stage of integration and is summed by a summing junction (22) with the output of the forth stage of integration (38).

Abstract: A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.

Abstract: An electronic filter for filtering an electrical signal. Signal processing circuitry therein includes a logarithmic filter having a series of filter stages with inputs and outputs in cascade and respective circuits associated with the filter stages for storing electrical representations of filter parameters. The filter stages include circuits for respectively adding the electrical representations of the filter parameters to the electrical signal to be filtered thereby producing a set of filter sum signals. At least one of the filter stages includes circuitry for producing a filter signal in substantially logarithmic form at its output by combining a filter sum signal for that filter stage with a signal from an output of another filter stage.

Abstract: In an oversampling digital-to-analog converter, an input 16-bit word digital signal is oversampled and quantized by a delta-sigma modulator into one of discrete values of +1, 0 and -1. A leaky integrator is coupled between the input and output terminals of an operational amplifier. A capacitor is charged by drawing a unit charge from a reference voltage source during a first half of the sample period of the +1 discrete value and discharged by injecting a unit charge to the input terminal of the operational amplifier during a second half of the sample period of the +1 discrete value. The capacitor is discharged during a first half of the sample period of the -1 discrete value and charged by drawing a unit charge from the input terminal of the operational amplifier during a second half of the sample period of the -1 discrete value.

Abstract: A low-noise switched-capacitor DAC converts an integer number from an N-bit digital format into an analog voltage level by transferring charge between two appropriately ratioed capacitors using a plurality of switches. The switches select only an appropriate one of a plurality of capacitors to connect to an operational amplifier in accordance with any digital input. The sampled kT/C noise and switch charge injection from an N-bit DAC is thus beneficially reduced.

Abstract: The capacitance of an unknown capacitor is measured with multimeter instrumentation employing a dual slope analog-to-digital converter. The initial voltage across the capacitor is measured and the capacitor is cyclically charged until the capacitor reaches a predetermined proportion of possible charge. The final voltage is measured. The voltage across the charging resistance is integrated over successive charging cycles to provide a value proportional to the charge delivered to the capacitor and this value is divided by the difference between the initial and final voltages.

Abstract: Apparatus converts into an analog value signals representing digital values. Sub-sets of switches are provided, the number of switches in each sub-set being directly related to the digital significance of the switches in such sub-set. The switches in each sub-set may be paired to provide for a conductivity of one switch in each pair. The signals representing individual digital values are introduced to the associated sub-sets to provide for the conductivity of an individual one of the switches in each pair in accordance with the digital value represented by such signals. The switches are connected in a recursive relationship defined by repetitions of a basic block. Each basic block is in turn defined by a pair of basic sub-blocks. A plurality of capacitors are also provided as output members. The capacitors are connected to the recursive relationship of the switches to charge the capacitors through paths defined by the conductive ones of the switches.

Abstract: This digital-analog conversion system comprises a digital modulator (1) having several quantification levels formed by a second order Delta-Sigma modulator and a digital-analog converter and switched capacitors filter set (3) whose law of progression between the different analog levels is independent of the absolute and relative values of the constituent components of the said assembly.

Abstract: A plurality of segment groups constituting a D/A converter, and decoders for decoding digital signals and selecting segments constituting the segment groups are arranged on a semiconductor chip. The segments constituting the plurality of segment groups are mingled and two-dimensionally arranged. The positions of the centers of gravity of the respective segment groups are substantially matched with the center of the arranged segments.

Abstract: An output pulse signal can be fabricated in an integrated circuit from an input signal. The output signal retains the desired pulse shape unaffected by jitter. A switched capacitor FIR filter is used to form the pulse shape, and then the clocking of the digital signals used to operate the pulse shaper is controlled to control the timing of different segments. The result is an output signal which has jitter but retains the desired pulse shape. Since a phase corrector which senses jitter can control the clocking, the output pulse shape is unaffected by jitter. The output pulse signal can be produced in an integrated circuit since switched capacitor pulse shapers are used, rather than a continuous time filter.

Abstract: Digital-analog converter intended to convert into analog signals digital signals formed of sign bits, of step bits and of segment bits, particularly signals coded by data compression according to law A, the said converter comprising a sign generator (4), intended to receive the sign bit of the said digital signal, a step generator (7), connected to the output of the sign generator and intended to receive the step bits of the said digital signal and to a segment generator (8) connected to the step generator and intended to receive the segment bits of the said digital signal, characterized in that the segment generator (8) is connected to the sign generator by means of the step generator (7) only.

Abstract: An analog-to-digital inverter includes successive approximation control logic for generating ten-bit binary numbers, a digital-to-analog converter (DAC) having a resistor string and a weighted-capacitor array for converting the ten-bit binary output of the control logic to a known analog voltage, and an analog comparator for comparing the output of the DAC to a reference voltage provided via a tap to the mid-point of the DAC resistor string. The unknown analog voltage input to the ADC and the reference voltage are provided to the capacitor array to precharge the array to a voltage equal to the reference voltage minus the unknown analog voltage. The output of the DAC is therefore equal to the known analog voltage plus the reference voltage minus the unknown analog voltage.

Abstract: A technique for compensating for variations in a resistor set overall gain switched-capacitor circuits, such as high accuracy digital-to-analog converters. The variation in overall gain from the desired gain is due to the variation in the total capacitance of the capacitors, compared to the variation in the resistance of the resistor, in the circuit during manufacture. A bias circuit, with two reference voltage outputs, is adapted to have a capacitor and a fixed resistor vary one of the voltage references depending on the capacitance thereof. The voltage difference between the two voltage references varies the overall gain of the switched capacitor circuit to compensate for variations in the overall gain. Also, a switched-capacitor digital-to-analog converter utilizing the above technique is presented.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: An absolute encoder for detecting the absolute (as opposed to the relative) rotational displacement of an encoder shaft includes a pair of pitch signals recorded on tracks and an associated signal processing circuit. The pair of pitch signals have different periods (wave lengths) which are such that they have no common factors. The signal processing circuit includes magnetic sensors for producing absolute position data indicative of the degree of displacement of the encoder shaft, on the basis of the pitch signals. Through the use of a pair of pitch signals having periods with no common factor, a high degree of resolution is obtained, without having no significantly increase the number of pitch signal tracks.

Abstract: A combined finite impulse response filter and digital-to-analog converter for converting sigma-delta over-sampled data into analog form. The filter removes out-of-band noise energy from the reconstructed analog signal resulting from the sigma-delta encoding process. The filter/converter is implemented in switched-capacitor technology. Further, a method of designing the optimum number of taps and the tap weight coefficients of the filter is given.

Abstract: The converter incorporates a transversal filter. The filter delays are implemented in digital form prior to conversion into analog signals (preferably using switched capacitor techniques). One form of switched capacitor converter (with or without filtering) employs a single capacitor, common to a plurality of bits, appropriate weighting of the bits being achieved by controlling the switching.

Abstract: A self-calibrating A/D and D/A converter operating according to the principle of charge redistribution includes a weighted capacitive primary converter network for most significant bits, a subsidiary converter network for bits of lesser significance, and a calibration and correction network. Each of the networks have capacitors. A comparator has an input connected to a node point. The capacitors of the primary converter network are each connected to the node point. A coupling capacitor is connected between the capacitors of the subsidiary converter network and the node point. Another coupling capacitor is connected between the capacitors of the calibration and correction network and the node point.

Abstract: A generator capable of forming an analog signal having a waveform determined from a sequence of digital control words applied at a high frequency, each word representing an increment of the analog signal to be produced at the output. For this type of generator, the accuracy of the increment value is an essential parameter. If several increments having a different value are generated as a function of the control word, their ratio has to be very accurate. The diclosed circuit is of the switched-capacitor type; it comprises several input capacitors (C1, C2, C3) that are theoretically identical. In order to take into account the dispersion due to manufacturing, a procedure for choosing the best input capacitor is previously established for obtaining a precise ratio between the increments (+V, +3V, -V, -3V) that can be supplied at the output. This procedure consists in comparing capacitors by pairs to sequence them and select the median capacitor.

Abstract: The output of a digital-to-analog (D/A) converter is coupled to the input of a filter. The D/A converter is initialized each time a new digital word is applied to the D/A converter for conversion, whereby each data conversion cycle (T.sub.D) includes an initialization interval (T.sub.I) followed by a conversion interval (T.sub.C). During T.sub.I the output of the D/A converter is driven to a reference level and during T.sub.C to the output of the D/A converter corresponds to the value of the input signal. The input section of the filter stores the D/A output just prior to initialization and, for during T.sub.I, coupling the stored value within the filter for processing while inhibiting the coupling to the filter of the reference level present at the D/A output.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of the "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: A highly accurate, inexpensive digital to analog converter requiring minimal accuracy in component values. A digital word is received serially, the least significant bit first. A voltage is stored on a capacitor at each bit, the value of the voltage being halfway between a reference voltage and the previously stored voltage, the reference voltage value depending on whether the bit is a logic "1" or "0". In each case, the halfway point of the voltage difference is determined by coupling to the midpoint of a pair of resistive components having essentially the same value. The value of the stored voltage represents the analog value of the digital word. The process is preferably repeated for the same word and the two resulting final voltages is averaged to eliminate any effect of a slight difference in component values in a pair.

Abstract: A digital-to-analog (D/A) converter for converting a n-bit digital 2's complement signal to an analog signal. The D/A converter consists of a controller, a capacitor array, and a switch array. The controller operates to convert a 2's complement digital input signal into a 1's complement digital signal. The capacitor array consists of (n-1) capacitors each being connected at one electrode to a common output terminal. The switch array consists of (n-1) switches each connected individually to the remaining electrodes of the (n-1) capacitors. The switch array applies either one of a first or a second reference voltage to the (n-1) capacitors in response a second controller signal. An additional capacitor and switch are connected to the capacitor and switch arrays which serve to convert a digital signal from 2's complement to 1's complement.

Abstract: In digital-to-analog converters with "rotating" current sources for converting an n-bit binary signal to an analog output signal, a single cyclic shift register is replaced by m cyclic shift register portions each having p=(2.sup.n -1)/m inputs, and the n-digit binary signal to be converted is changed into the thermometer code by means of a code converter. The middle output of the code converter and equal numbers of code converter outputs on both sides thereof are connected to one of the shift register portions. According to the same rule, the code converter outputs located further from the middle are connected to the other shift register portions. Thus, a clock signal serving as a shift signal for the shift register portions only needs to have a frequency which is p times that of the sampling signal with which an, e.g., analog, audio signal is digitized.

Abstract: In a digital-to-analog conversion circuit, a level detector is used to determine when the digital signal is lower than a predetermined value. When a predetermined time has expired, after the level detection, an inversion detector detects an inversion in polarity of the digital signal. As a result, a control signal is produced to shift the digital signal input to the digital-to-analog (D/A) converter and to attenuate the output analog signal.

Abstract: A semiconductor capacitor for use in an analog-to-digital converter includes two parallel connected capacitors with separate lower plates (44) and (46) fabricated of polycrystalline silicon and upper plates (52) and (54) also fabricated of polysilicon. The plates are separated by capacitive oxide dielectric structures (48) and (50). They are interconnected such that the lower plate (44) of one capacitor is connected to the upper plate (54) of the other capacitor and the lower plate (46) of the other capacitor is connected to the upper plate (52) of the first capacitor. With such a configuration, the odd ordered non-linearities contributing to the voltage coefficient errors are cancelled.

Abstract: An analog-to-digital and digital-to-analog converter includes an array of capacitors each being differently weighed from the others, one electrode of each of the capacitors being connected to a common node. Switches are provided for selectively applying, in response to a first control signal, an analog input applied to an analog input terminal and a plurality of reference voltages to the other electrode of the capacitors. A comparator has a pair of input terminals whose inverting and non-inverting inputs are selectively switched over with respect to polarity in response to a second control signal. The comparator compares a voltage appearing on the node and applied to one of the input terminals and one of the reference voltages applied to the other input terminal. An analog output terminal is connected to the output of the comparator. A successive comparison register sequentially takes in outputs of the comparator in response to a third control signal.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal comprises a series arrangement of at least two integrating circuits (1,2) and a control unit (18) for supplying a first and a second control signal (S1, S2) to the first and the second integrating circuit. The integrating circuits are adapted to perform an integration step under the influence of the first and the second control signal. The control unit is adapted to generate, in this order, the first control signal M1 times, the second control signal M2 times, the first control signal M3 times and the second control signal M4 times. For converting arbitrary digital signals M2+M4 is equal to a constant (k). Due to this measure an offset voltage which is independent of the value of the n-bit digital signal to be converted is produced at the output (8) of the converter. For converting n-bit digital signal the constant k is preferably taken to be equal to 2.sup.p in which p.ltoreq.n.

Abstract: The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scaled resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense.

Abstract: A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values.

Abstract: A digital-to-analog converter includes a group of resistors serially connected between a power source potential supply terminal and a reference potential supply terminal. First group switches are connected between a first circuit point and given serial connection nodes of the resistor group, and between the first circuit point and the reference potential supply terminal. Each of these switches is controlled so as to be selectively turned on according to the result obtained from decoding upper bits of a digital signal. Further, second group switches are connected between a second circuit point and other serial connection nodes of the resistor group, and between the second circuit point and the reference potential supply terminal. Each of these switches is controlled so as to be selectively turned on according to the result obtained from decoding lower bits of the digital signal.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal. The converter includes at least two switched capacitor integrators (1, 2) arranged in series and a control unit (18) for applying control signals to the integrators which perform an integration step under the influence of the control signal. Each integrator is provided with a capacitor network (11, 12) having at least two capacitors (27.1, 27.2, . . . ; 28.1, 28.2, . . . ) coupled between the input (13; 4) of the integrator and the inverting input (-) of an associated amplifier stage (5; 6). A capacitor (9; 10) is coupled between the inverting input (-) and the output (7; 8) of this amplifier stage. The control unit is adapted to apply, in this order, a first control signal to the first integrator (1), a second control signal to the second integrator (2), a third control signal to the first integrator and a fourth control signal to the second integrator.

Abstract: A true average peak detector includes an input capacitor having a capacitance C and an output capacitor having a capacitance nC. N voltage samples are successively stored on the input capacitor and are transferred to the output capacitor without discharging the latter. The output voltage from the accumulated charge on the output capacitor is equal to a true average of the voltages of the n samples.

Abstract: A switched capacitor array (20) for use in a digital-to-analog converter (10), an analog-to-digital converter (60), or other digitally controlled circuit is disclosed. The array includes a plurality of switched capacitors (C(0) through C(15)) of substantially identical value, each having a switched terminal. Logic circuitry (17) responsive to a digital input signal (A) having a value N provides a logic output signal indicative of the digital input signal. Gating circuitry (40) responsive to the logic output signal switches the switched terminal of a selected switched capacitor to an analog signal provided by a digital-to-analog converter stage of lesser weight, and sequentially switches the switched terminals of a predetermined number of the switched capacitors to a predetermined voltage. The selected capacitor and such predetermined number of capacitors are determined by the value N of the digital input signal.

Abstract: In a process of digital to analog conversion, use is made of a network comprising capacitors (C through C'/16) which are binary-stepped in their capacitance, and whose lower terminals, depending upon the binary value of the allocated bit of a digital signal to be converted, are switchable to a reference voltage source (V.sub.ref) or to ground potential and thus either codetermine or do not codetermine the value of the network output voltage representing the analog signal. In order to achieve a monotonic and possibly linear converter characteristic when converting into bipolar signals, the network is so switched that, when generating positive and negative analog values of the same order, it always involves the same capacitors, and no additional capacitor is required for change redistribution.

Abstract: There are provided a current-voltage converting means (22) for converting a constant current from a constant current supplying circuit into a voltage, an integration circuit (26), a switched capacitor (23) arranged between the current-voltage converting means (22) and the integration circuit (26) for controlling the charge amount supplied to the integration circuit, and first and second control signal generating circuits (28, 31) respectively having counters (29, 32) and comparators (30, 33) and supplied with first and second digital input signals for controlling switching frequency of the switched capacitor (23) to thereby generate, at an output of the integration circuit (26), an analog signal proportional to a product of the first and second digital input signals, to thereby simplify the circuit configuration and reduce the production cost.

Abstract: A D/A converter includes a first stage capacitor ladder, a second stage capacitor ladder, a coupling capacitor, (l+m) switches, and a short-circuiting switch. The first stage capacitor ladder includes l capacitors having one side electrodes commonly connected to a first point and capacitances binary-increased from 2.sup.0.C to 2.sup.l-1.C (l is a natural number and C is a unit capacitance). The second stage capacitor ladder includes m capacitors having one side electrodes commonly connected to a second point and capacitances binary-increased from 2.sup.0.C to 2.sup.m-1.C (m is a natural number). The coupling capacitor has a capacitance of 1.C and is connected between the first and second points. The (l+m) switches selectively connects another side electrodes of the (l+m) capacitors to a first or second reference voltage in response to an (l+m)-bit digital input signal. The short-circuiting switch is connected between the first reference voltage and the first point of the first stage capacitor ladder.

Abstract: An ultra-fast high resolution digital-to-analog converter (DAC) converts a digital input code into a corresponding analog output voltage. The DAC has an inherent low impedance bipolar output.In one embodiment, the DAC includes a resistor network coupled to a voltage source for providing a plurality of reference voltages. The DAC comprises a chain of capacitor/switch links each coupled via a pair of terminals, wherein the DAC output voltage appears across the chain. Each capacitor/switch link includes a capacitor, is responsive to a respective bit of the DAC input code and operates to couple the capacitor across the terminals when the bit is high, and connect the terminals when the bit is low. The respective reference voltages are also applied to the capacitors which are discharged only due to parasitic effects. The on-resistances of all individual switches and values of the capacitors employed in the DAC are insignificant.

Abstract: The dielectric absorbtion of capacitors in a filter that removes the AC component from a precision digital-to-analog converter (DAC) is effectively eliminated by operating the normally grounded end of the filter at a DC voltage that approximates the DC output voltage from the precision DAC. This prevents the capacitors in the filter from becoming charged to a DC voltage, and has the further benefit of reducing the number of time constants otherwise spent in charging and discharging those capacitors to within some specified percentage of the output DC voltage. The result is greatly reduced settling time for the filter. The filter may be of any convenient type. The precision DAC may be of the type that switches between ground and a precision reference voltage with a precisely controlled duty cycle, and the approximating voltage may be obtained from any conventional DAC.

Abstract: An adaptive delta modulation circuit having an analog adaptation circuit and an integrator circuit. The adaptation circuit exponentially converts a voltage which is proportional to the average of a time duration of an overload control signal to an adaptation current which is averaged and converted to an adaptation voltage. An integrator circuit includes a sole switch which shorts to ground a circuit point for generating an analog signal formed of line segments; each segment has a slope magnitude controllable by the adaptation voltage.

Abstract: A charge redistribution analog-to-digital converter is described that permits their ncorporation of offset voltage correction to provide an accurate reflection in the digitalized output signal of the analog input signal. In a distributed capacitor successive approximation device, additional capacitors are added both to a most significant bit array group of capacitors and to a least significant array group of capacitors that are used in conjunction with the offset voltage. The value of the offset voltage is stored in a register and the register determines various switch positions that determine the value of the offset voltage incorporated in the final output voltage.

Abstract: A switched capacitor circuit for use in a digital-to-analog converter, an analog-to-digital converter, or other digitally controlled circuit is disclosed. The switched capacitor circuit includes first and second arrays (30, 40) of switched capacitors of substantially identical value, each capacitor having a switched terminal. The switched capacitor circuit further includes a decoding circuit (20) responsive to a digital input having a decimal value N for providing control signals for each of the capacitor arrays. Logic circuitry (33, 43, GC(I)) responsive to the control signals is included for sequentially switching the switched terminals of L and M capacitors respectively of the first and second switched capacitor arrays in a predetermined sequence so as to maintain the geometrical centroid of the switched capacitors at a substantially constant location, where the sum of L and M is equal to N.