Abstract: A capacitance-to-digital (CD) modulator converts capacitance of a differential pressure sensor to a pulse code modulation output signal. The first stage of the CD modulator is a sigma-delta integrator having an auto-zero capacitor connected between an integrator input node and an amplifier input. During an auto-zero phase, a feedback capacitor is connected between the amplifier input and output, and the auto-zero capacitor stores a voltage that is a function of leakage resistance of the sensor capacitor connected to the integrator input node. During an integration phase, the feedback capacitor is connected to the integrator input node. If an overpressure/short circuit condition exists, the stored voltage on the auto-zero capacitor induces a current to flow to the feedback capacitor to drive the integrator to saturation and suppress foldback anomaly.

Abstract: Disclosed herein is a divide-add circuit and a high-resolution Digital-to-Analog Converter (DAC) using the same. The DAC includes a plurality of DAC units and one or more divide-add circuit units. The plurality of DAC units performs Digital-Analog (DA) conversion on two or more segmented codes, into which an input digital code is segmented. The one or more divide-add circuit units is configured to be each composed only of capacitors and switches and to generate a final DA conversion output for the entire input digital code based on the voltages of the DAC units. Accordingly, a high resolution of more than ten bits can be implemented.

Abstract: A digital-to-analog converter (DAC) compatible with CMOS technology and operable in low voltage applications. An input capacitor stores a charge sample according to a digital input signal and a previous output analog signal. An analog output circuit has a feedback capacitor to share the charge sample and accordingly generate a current output analog signal from an output node. The output node may be continually connected to the input capacitor through a pass resistor.

Abstract: Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.

Abstract: An error averaging comparator based switch capacitor (CBSC) circuit cyclically operates through a sampling phase, a first transfer phase, and a second transfer phase. During the sampling phase, an input voltage is sampled. During the first transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to a first load. During the second transfer phase, the sampled input voltage is amplified by the same fixed ratio and transferred to a second load. The circuit configuration during the second transfer phase is substantially the same as that during the first transfer phase, except that the at least one of its circuit elements is connected in a reverse polarity. Due to the reverse polarity, the respective errors due to circuit non-idealities during the two transfer phases are exactly opposite. By combining the outputs taken at the first load and at the second load, the errors are averaged out.

Abstract: A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests disclosed in the present invention provides the digital input interfaces, which are comprised of capacitors, analog switches and digital circuits, for the usage of testing the mixed-signal circuits. The present invention provides a low-priced testing platform to accomplish the testing of circuits and to solve the problems of high-cost mixed mode tester and of utmost restrictions against the surrounding condition. Therefore, the present invention improves the testability, reduces the test cost, shorten the processes of designation and efficiently seize on the time-to-market.

Abstract: A pressure transmitter having a capacitance-to-digital modulator produces an output as a function of sensor capacitance and a reference capacitance. Transmitter also includes a sensor failure mode detector produces an output signal and identifies failure modes of the sensor capacitance and reference capacitance.

Abstract: In a digital/analog converter of a switched capacitor circuit type including at least one capacitor, at least one power supply terminal, and at least one output terminal, a switch circuit is adapted to carry out a charging operation upon the capacitor so that a charge is stored in the capacitor and then carry out a discharging operation upon the capacitor to discharge the charge to one of the power supply terminal and the output terminal in accordance with a digital input data signal.

Abstract: A method of operating a digital to analog converter comprising the steps of operating the converter in a first mode to obtain a first conversion result, operating the converter in a correction mode in which one or more correction conversions are made, and wherein each correction conversion takes the result of a preceding result as a valid starting point.

Abstract: A system and method including a DAC that receives a multi-bit digital signal and outputs at least two analog signals including a first analog signal and a second analog signal, the first analog signal being indicative of a sum of values of bits in the multi-bit digital signal, the second analog signal also being indicative of said sum of values of said bits in the multi-bit digital signal. The first and second analog signals may be substantially equal or they may be different from each other.

Abstract: A digital to analog converter (DAC) circuit operates least significant bit (LSB) first.

Abstract: A digital-to-analogue converter (DAC) (1) comprises a digital processing circuit (2) having an input register (10) to which data samples of a digital input signal are written at a data sampling rate (fs). A delay register (14) holds each data sample for one clock cycle of the data sampling rate (fs), and a subtracting circuit (15) sequentially produces difference values between consecutive ones of the data samples by subtracting the data sample in the delay register (14) from the input register (12) on each clock cycle of the data sampling rate (fs).

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.

Abstract: A method of sampling an input signal in a delta-sigma modulator having at least an integrator stage and a feedback digital-to-analog converter (DAC) stage includes sampling an input signal at a sampling rate by alternately utilizing the two sampling capacitors during two sampling cycles such that the two sampling capacitors are each being utilized at half the rate of the sampling rate. Samples from the two sampling capacitors are summed at the sampling rate at an intermediate node with a feedback samples provided by the feedback DAC stage at the sampling rate to generate output samples which are output from integrator stage at the sampling rate.

Abstract: A shared voltage reference circuit for a codec is shown that includes a voltage reference circuit for producing a reference voltage. A first sample and hold circuit has a first capacitor coupled to an output of the voltage reference circuit through a first switch controlled by a first phase of a sample clock signal for the codec. A second sample and hold circuit has a second capacitor coupled to the output of the voltage reference circuit through a second switch controlled by a second phase of the sample clock signal. A clock generator circuit generates the first and second phases of the sample clock signal, where the first and second phases are non-overlapping.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence, according to digital input. A switching network charges a capacitor according to the difference between the two selected reference voltages, then connects another capacitor to the first capacitor to generate a voltage intermediate between the two selected reference voltages by redistributing charge between the capacitors. The switching network also selects one of the selected reference voltages or the intermediate voltage as the analog output voltage. This conversion scheme saves space with little or no increase in current consumption.

Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Abstract: A charge transfer system includes a current-based input device for generating an input current signal, a temporary energy storage device, and an amplification device. A switching device couples the temporary energy storage device to the current-based input device during a first portion of a time period and to the amplification device during a second portion of a time period. The input current signal charges the temporary energy storage device, during the first portion of the time period, to generate an input voltage signal. The amplification device receives the input voltage signal during the second portion of the time period.

Abstract: The present invention relates to digital to analog converters, and especially but not exclusively to switched capacitor digital to analog converters (DACs) for digital audio signals. The present invention provides a switched capacitor DAC for converting a digital signal and comprising a feedback capacitor coupled between an input and an output of an operational amplifier; a charging capacitor and a switching arrangement arranged during a charging period to couple a first side of said charging capacitor to a first reference voltage or a second reference voltage dependent on said digital signal, the switching arrangement further arranged during said charging period to couple a second side of the charging capacitor to the second reference voltage or the first reference voltage in anti-phase to the reference voltage coupled to said first side of the charging capacitor; the switching arrangement further arranged during a settling period to couple said charging capacitor to said feedback capacitor.

Abstract: A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*VREF, C*VREF/2, 0, ?C*VREF/2 and ?C*VREF. When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN?VREF/2 and A*VIN?VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

Abstract: Simplifying the design of buffer amplifier circuits to provide reference voltages of desired characteristics on a path. Two separate circuits may be used to provide the necessary charging (of a load connected to the path) in non-overlapping time durations. In an embodiment in which the load comprises sampling capacitors of a stage of an analog to digital converter (ADC), each of the two circuits contains a corresponding charging capacitor, with the charging capacitors charging the load in non-overlapping time durations of a hold phase. The first charging capacitor may be charged using a coarse buffer with a high drive strength and the second charging capacitor may be charged using a fine buffer with high accuracy.

Abstract: A DA converter circuit is provided for use in a ?? AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.

Abstract: A first amplifier circuit samples and amplifies an input analog signal by a gain of 0.8 and outputs the amplified signal to a first subtracter circuit. A first analog-digital converter circuit converts the input analog signal into a digital value so as to retrieve the higher 4 bits. A first digital-analog converter circuit converts the digital value produced by conversion by the first analog-digital converter circuit into an analog value. The first subtracter circuit subtracts an output analog signal from the first digital-analog converter circuit from an output analog signal from the first amplifier circuit. The output analog signal from the first digital-analog converter circuit is amplified by a gain of 0.8. By setting the gain of the first amplifier circuit to be below 1, an input voltage range is extended.

Abstract: An n-bit digital/analog converter is provided for converting an n-bit digital word to a corresponding voltage. The converter comprises an (n?1) bit bufferless switched capacitor digital/analog converter (10) having an output (Vout) for direct connection to a capacitive load (CLOAD). The (n?1) bit converter (10) also has first and second reference voltage inputs (V1, V2) and an (n?1) bit digital input. An (n?1) bit selective inverter (131, . . . , 13n?1, 141, . . . , 14n?1) supplies the (n?1) least significant bits to the digital input and inverts them if the most significant bit has a certain value. A switching arrangement (11, 12) connects the first and second reference voltage inputs (V1, V2) to receive first and second or second and first reference voltages depending on the value of the most significant bit.

Abstract: A direct charge transfer digital to analog converter comprising a single reference voltage linked through a switching structure to a charge accumulation device. An accumulated charge of the charge accumulation system represents the analog output voltage. Use of the single reference voltage in conjunction with the switching structure and charge accumulation system allows for a digital signal to be converted to an analog signal with lower power consumption. Use of a single reference voltage consumes less power and space thereby making it superior to prior art digital to analog conversion systems.

Abstract: Improved methods for the calibration, in particular for self-calibration, of an A/D or D/A converter with weighted network (CN) are proposed. Only a relevant part of the weights (C0, C1, C2, Cn) is calibrated by measurement. In addition, by iterative repetition of measurements used for the calibration a noise is used for increasing a resolution. Finally, possibilities for dealing with the offset are illustrated. Complementary equations are set up and the offset is eliminated by subtraction. If an equation necessary for calibration cannot be directly set up because of an overflow, this is resolved by using special binary codes which indicate which weights are enabled and/or disenabled, and their conversion.

Abstract: A switched capacitor circuit includes an amplifier, a first switched capacitor network, and a second switched capacitor network. Either the first or second switched capacitor network is switched in a sampling configuration or a gain configuration according to connection states of the switches thereof. The amplifier includes a first transistor and a second transistor coupled to the first switched capacitor network, and a third transistor and a fourth transistor coupled to the second switched capacitor network. A first switch is coupled to a first connection point of the first and second transistors, and a second switch is coupled to a second connection point of the third and fourth transistors.

Abstract: Segmented mixed signal circuitry comprising a plurality of analog segments is disclosed. Each analog segment is operable to perform a series of switching operations dependent on an input data signal. The circuitry is arranged to receive shaped clock signals provided in common for all segments, and to perform each switching operation in a manner determined by the shape of the common shaped clock signals. The circuitry is suitable for use in digital to analog converters (DACs).

Abstract: In a digital-to-analog converter including an integrated test circuit, a digital input and an analog output, a comparator (5) capable of being connected with the analog output (4) and including a connection (7) for a reference voltage source, a digital test connection (11) and a logic element is provided, the logic element being connected with the test connection (11) for emitting the digital value 0 or 1 as a function of the difference between the voltage at the analog output (4) and the reference voltage.

Abstract: A flash analog-to-digital converter (ADC). Each comparator of the flash ADC has an OFF-ON-OFF transfer function. For each analog value to be converted, only one comparator is in the ON condition, and the other comparators are in the OFF condition. In this way, the average power consumption of the flash ADC is much less than the average power consumption of prior similar devices.

Abstract: A circuit dynamically biases switching elements in a current-steering digital-to-analog converter (DAC), The DAC includes, in each cell, a current source coupled to a current node, a first switching element coupled between the current node and a first DAC output node, and a second switching element coupled between the current node and a second DAC output node. The circuit includes first and second inputs coupled to the first and second DAC output nodes, respectively, first and second outputs coupled to the first and second switching elements, respectively, and a third output coupled to the first and second switching elements. The first and second outputs provide a first ON bias voltage and a second ON bias voltage to control the first and second switching elements, respectively, such that a voltage at the current node is maintained at a predetermined voltage. The third output provides a common OFF bias voltage.

Abstract: An improved circuit for a delta-sigma digital-to-analog converter comprises integrating operational amplifier, sampling capacitors, integrating capacitor, and a voltage divider consisting of a plurality of sampling capacitors. Three trigger signals of different phases are designed to control three sets of switches, a first trigger signal only turns on and off a first set of switches, so as to charge the plurality of sampling capacitors, a second trigger signal only turns on and off a second set of switches, so as to enable the charge on one of the sampling capacitor and the charge on the integrating capacitor to be averaged, a third trigger signal only turns on and off a third set of switches, to enable the plurality of sampling capacitors to be discharged.

Abstract: A variable gain amplifier circuit using a variable impedance circuit, includes an input terminal, an operational amplifier, a first variable impedance connected with the input terminal and the operational amplifier, a second variable impedance connected with a reverse input terminal of the operational amplifier and an output terminal of the operational amplifier, a third variable impedance whose first end is connected with the reverse input terminal of the operational amplifier, a fourth variable impedance whose first end is connected with the input terminal and second end is connected with a second end of the third variable impedance, and a fifth variable impedance whose first end is connected with the second end of the third variable impedance and second end is connected with the output terminal of the operational amplifier, wherein the first variable impedance, the second variable impedance, and the third variable impedance are controlled in accordance with an upper bit group, and the fourth variable imped

Abstract: An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

Abstract: A switched capacitor circuit of a pipeline analog to digital converter. The pipeline ADC includes a clock generator, a signal reference circuit, and a plurality of switched capacitor circuit. Each switched capacitor includes an operational amplifier, a first sampling capacitor, a first signal input switch, a first reference input switch, a first reference reset switch, and a first feedback network. A method for operating the switched capacitor circuit includes after the first reference input switch turning off, turning on the first signal input switch to transmit a first input signal to the first sampling capacitor and turning on the first reference reset switch to transmit a common signal to a second terminal of the first reference input switch, turning off the first reference rest switch then turning off the first signal input switch, and after the first signal input switch turning off, turning on the first reference input switch.

Abstract: A digital to analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital to analog converter augmented with DCT and CDS techniques. A digital to analog converter augmented with Postfilter Droop Compensation.

Abstract: To provide a current generating circuit capable of generating an analog current having non-linear characteristic from linearly-instructed grayscale data with a small number of elements and a simple circuit structure, and an electro-optical device and an electronic apparatus employing the current generating circuit. A digital-to-analog conversion circuit section 25 can perform time-sharing processing by selectively turning on and off first to third selection signals S1 to S3. In the first processing, electric charges corresponding to a first output current obtained by binary-weighting a reference current corresponding to a reference voltage Vref is stored in a storage capacitor Ch. In the second processing, by inputting a second output voltage Vout2 corresponding to the electric charges stored in the storage capacitor Ch to the respective gates of the first to fourth driving transistors Qd1 to Qd4, the digital-to-analog conversion is further performed using the first output current as the reference current.

Abstract: This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters. A differential switched capacitor digital-to-analogue (DAC) circuit (500) comprises first and second differential signal circuit portions (500a,b) for providing respective positive and negative signal outputs with respect to a reference level, and has first and second reference voltage inputs (112,114) for receiving respective positive and negative references. Each of said first and second circuit portions comprises an amplifier (102a,b) with a feedback capacitor (104a,b), a second capacitor (106a,b), and a switch (108a,b, 110a,b) to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor.

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin?) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Abstract: An linear optical sensor charged-coupled topology using single-stage inverting charge-coupled amplifier driving an analog-to-digital converter which uses the converter full-scale reference as a precharge level. Since an offset in the range of 100–200 mV is introduced in the charge amplifier, a corresponding offset is also introduced into the ADC to allow the amplifier to more quickly drive the amplifier output to a low level. The converter offset is proportional to the converter reference to ensure that it is controlled and tracks the reference.

Abstract: An analog signal outputting circuit comprises two unit analog circuits for outputting an analog signal, corresponding to levels “?1” or “1”, and a low-pass filter for smoothing the analog signal output from the two unit analog circuits, as selected by codes output from the four-valued delta-sigma modulator. In case the input signal is ?2 or +2, outputs of the unit analog circuits are summed together to output an analog signal corresponding to ?2 or +2. In case the input signal is ?1 or +1, outputs of the unit analog circuits are alternately used to output an analog signal corresponding to ?1 or +1 to reduce the non-linearity error resulting from variations in the analog devices.

Abstract: A method and circuit for gain and/or offset correction in a CDAC circuit are provided. The gain and/or offset correction can be realized by adjusting the sampling capacitance of a capacitor array, with a positive array of the CDAC circuit being trimmed for gain correction, and a negative array of the CDAC circuit being trimmed for offset correction. Accordingly, corrections to variations in gain and/or offset caused by process variations can be suitably addressed. To facilitate gain correction, an exemplary CDAC circuit comprising an N-bit capacitor array includes on the positive side of the capacitor array an additional capacitor configured to capture the sampling voltage. An exemplary CDAC circuit can also be configured to have one or more capacitors shifted out of the total capacitance of the capacitor array, and thus reduce the amount of charge stored during sampling.

Abstract: Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

Abstract: Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer coding. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs, wherein the capacitors are switched according to a thermometer code to reduce differential converter non-linearity.

Abstract: D/A converter of this invention including n+1 capacitors in total consisting of one terminating capacitor (C0) and n binary-weighted capacitors (C1-4) that are subjected to binary weighting ratio of 1:2:4: . . . :2(n?1), and, an inverting amplifier (INV1), further comprising: a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1); a switching means for terminating operation (SWR0) supplies one of two main reference voltages (VB,VT) to the terminating capacitor (C0), and then, makes connection of the terminating capacitor (C0) to the output of the inverting amplifier (INV1); a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the n binary-weighted capacitors (C1-4) depending on digital data (D1-4), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1).

Abstract: An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.

Abstract: With a layout method for voltage division resistors, employing a photolithographic system, resistors which are required to have relative accuracy are disposed in the center of a layout area so as to be adjacent with each other, and another resistor is divided, so that divided portions thereof are disposed on the outer side of the resistors maintaining high accuracy, respectively, ends of the divided portions, positioned on the opposite sides of the voltage division resistors, respectively, being connected with each other.

Abstract: An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

Abstract: Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals Indicative of the digital signals to a signal conditioning stage at an output data rate different the input data mute.

Abstract: A tree-structured dynamic encoder generates an N-bit encoder output word in response to each encoder input word of a sequence of encoder input words, such that the number of encoder output word bits of value 1 equals a value of the encoder input word and such that positions bits of value 1 within the N-bit encoder output word for each give value of encoder word varies with time. Some or all of the switching blocks produce more than two block output words in response to each block input word. The dynamic encoder includes a tree of switching blocks, each dynamically encoding a block input word into more than one block output words, each having fewer bits than the block input word. A sum of values of the output words of each switching block always equals a value of that block's input word.