Abstract: In a D/A conversion apparatus capable of achieving high accuracy formation of output voltage of an analog signal, when data D7 through D0 of 8 bits are inputted to a decoder 4, by a control signal from the decoder 4, a pair of switches connected to both ends of predetermined resistor R0 are selected from respective switches S0A through S255A, S0B through S255B of respective switch groups 3A, 3B of a voltage selecting circuit 3 and simultaneously operated to make ON and the other respective switches are operated to make OFF. Further, voltage across both sides of resistor R0 of a voltage generating circuit 2 connected with the pair of switches operated to make ON is inputted to a differential amplifier 5 and average voltage of the voltage across the both ends of the resistor R0 connected with the switches operated to make ON is outputted from an output terminal 6 as an analog signal.

Abstract: A digital-to-analog converter system [150] based on a symmetrical circuit [152] comprising matched capacitors [104][106] for pseudo-passive, serial D/A conversion of a digital input signal x(n). Each bit x(n, k) of x(n) is converted by selecting one of the two capacitors in each capacitor pair [104][106] as the driving one, and charging it to plus/minus the reference voltage according to the value of x(n, k). The other capacitor in each capacitor pair [104][106] stores the previously generated voltage signal representing the bits of x(n) less significant than the bit x(n, k) being processed in the considered cycle k of the serial conversion process. After the driving capacitor has been charged according to x(n, k), the capacitors in each capacitor pair [104][106] are connected in parallel.

Abstract: To minimize the number of positions to be altered in a transition from one output data word to the next in a scrambler for scrambling successive, thermometer coded binary input data words comprising N bits into corresponding successive output data words also comprising N bits, the scrambler is adapted, if the number of bits of one binary value has increased from one input data word to the next, to maintain bits of said one binary value in positions in the corresponding output data word where the previous output data word had bits of said one binary value, and to randomize the remaining bits of said one binary value to positions in the corresponding output data word where the previous output data word had bits of the other binary value.

Abstract: A method is disclosed to operate a sigma-delta modulator of a type that includes a quantizer. The method has steps of (a) sampling an amplitude of an input signal to the sigma-delta modulator; and (b) controlling the switching of a capacitance bank in accordance with the sampled amplitude of the input signal for generating a dither signal at an input of the quantizer. The dither signal is generated to have a pseudorandom amplitude that is inversely proportional to the sampled amplitude of the input signal. The step of controlling and generating operates a linear feedback shift register to switch individual ones of a plurality of capacitances of the bank of capacitances in and out of a capacitance network. In one embodiment the step of operating the at least one linear feedback shift register turns a linear feedback shift register clock signal on and off as a function of the amplitude of the input signal.

Abstract: The present invention provides a digital-analog converting circuit capable of shortening time necessary to digital-analog conversion.

Abstract: A CDAC circuit is provided that can operate at low supply voltages, for example, at supply voltages of 2.5 volts or less. To accomplish low voltage operation, switches in the CDAC circuit, such as sampling bit switches, mid-point switches or auto-zero switches, are gate-boosted to permit the voltage at the transmission gates to exceed the threshold voltage and thus permit the transmission gates to effectively operate. As a result, the CDAC can continue to operate, even with the existence of lower power supply voltages. In accordance with an exemplary embodiment, a gate-boosting circuit comprises a pair of N-channel transistor devices and a charging capacitor configured to provide a gate-boosting voltage to the transmission gates. In addition, the gate boosting circuit can comprise conventional CMOS devices, rather than more expensive low threshold MOSFET devices.

Abstract: Mixed-signal circuitry (20), comprising digital circuitry and analog circuitry, is operative to perform a series of operation cycles. The analog circuitry has a plurality of circuitry segments (2, 4) which together produce an output signal having a frequency in a predetermined desired range of frequencies. The digital circuitry comprises a digital signal generating portion (6) operable in each cycle to generate a set of digital signals (T1-Tn) for application to respective ones of said segments, and a segment rotation section (22) operable to rotate by r segments the digital signals (T1-Tn) applied to the segments in each cycle as compared to those applied in the preceding cycle, where r is a rotation amount for the cycle concerned.

Abstract: An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.

Abstract: A switched capacitor circuit includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array. A first plurality of switches selectively couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch samples the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node. A second plurality of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected onto the node.

Abstract: A pipelined digital-to-analog converter (DAC) converts a digital input to an analog output. The pipelined DAC has a plurality of stages. A first of the plurality of stages is coupled to an initialization capacitor and ground. Each of the remainder of the plurality of stages is coupled to a respective previous stage. Each of the plurality of stages includes a capacitor, a first switch and a second switch. The capacitor has first and second plates. The capacitor receives a charge at the first plate in accordance with an associated bit of the digital input. The first switch couples the first plate of the capacitor to ground when the capacitor is not receiving the charge. The second switch couples the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC, improving its performance.

Abstract: Digital/analog converter for converting a binary coded data word into an analog output signal, having a capacitor cell Iratrix (9) comprising capacitor cells (13ij) which are arranged in matrix form in columns and rows and are driven by thermometer-coded control signals via control lines; a first coding device (6) for recoding the n more significant data bits of the data word D to be converted into a thermometer-coded column control signal which has a width of 2n bits and is applied to the capacitor cell matrix (9) via column control lines (8), a second coding device (11) for recoding the m less significant data bits of the data word D to be converted' into a thermometer-coded row control signal which has a width of 2 bits and is applied to the capacitor cell matrix (9) via row control lines (12), each capacitor cell (13ij) of the capacitor cell matrix (9) in each cast having an associated local decoding circuit (1911) which drives switches (34, 35, 36, 37) in a manner dependent on the thermometer-coded row c

Abstract: Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index cor

Abstract: A digital-to-analog conversion circuit (105) includes a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.

Abstract: A switched capacitor low-pass filter incorporates a plurality of integrator stages cascade connected together. The filter includes at least one stage that includes a circuit device for cancelling out glitch pulses. This device is a deglitching circuit provided within the filter. Preferably, each stage in the filter is formed of a deglitching device which acts as a smoothing integrator.

Abstract: A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

Abstract: A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

Abstract: First, when a switch portion is in an off-state, the first charging portion C1 charges parasitic capacitance CS. Second, a second charging portion C2 charges internal capacitance CD during the switch portion SW remains in the off-state. Third, the switch portion SW is turned on. Then, electric charges flow into the parasitic capacitance CS from the internal capacitance CD. Finally, the value of the voltage of the internal capacitance CD becomes equal to that of the voltage of the parasitic capacitance CS. Fourth, the switch portion SW is turned off. Then, the second charging portion C2 charges the internal capacitance CD again. Thence, the third step and the fourth step are repeated. Consequently, the voltage of the parasitic capacitance CS can be set at a desired value.

Abstract: A D/A converter circuit capable of handling a high bit number digital signal, having good linearity, and having a small occupied surface area is provided. The D/A converter circuit has n−m+1 capacitors (where m is a natural number, and smaller than n), and the supply and discharge of electric charge to one of the capacitors from among the n−m+1 capacitors are controlled by the lower m bits of a digital video signal. The supply and discharge of electric charge to the remaining n−m capacitors, from among the n−m+1 capacitors, are controlled by the upper n−m bits, from among the n bits, of the digital video signal.

Abstract: A capacitor array is configured to negate or cancel the voltage coefficient of the capacitors within the array, and thus reduce and/or eliminate the voltage coefficient non-linearities present within the A/D converter. In the capacitor array, a first capacitor is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient non-linearities of the first capacitor can be suitably canceled by the inverse voltage coefficient non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.

Abstract: In a digital/analog converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)-th capacitor has a unit capacitance, and a 2k-th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)-th capacitor is connected to a first terminal of the 2k-th capacitor. Also, if m is 1, 2, . . . , n−1, an m-th coupling capacitor is connected between the first terminal of the 2m-th capacitor and the first terminal of the (2m+t)-th capacitor, while an (n−1)-th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . . , n−1, the first coupling capacitor has the unit capacitance, and an m′-th one of coupling capacitor has a capacitance of the unit capacitance plus a quarter of the capacitance of an (m′−1)-th coupling capacitors.

Abstract: Quasi-differential successive-approximation methods and structures are provided for converting analog signals into corresponding digital signals. These methods and structures realize the signal-to-noise improvements of fully-differential SAR ADCs and the calibration accuracy improvements of pseudo-differential SAR ADCs. Structures of the invention operate in a fully-differential mode to establish more-significant bits of the corresponding digital signals and in a pseudo-differential mode to establish the less-significant bits.

Abstract: A digital-to-analog conversion circuit of charge distribution type includes a plurality of capacitors having respective capacitances that increase in a sequential order, one end of the capacitors being commonly connected electrically. The circuit also includes a plurality of analog switches each for electrically connecting a reference potential corresponding to a digital signal inputted from outside to the other end of the corresponding capacitor. These analog switches have respective driving capacities that increase in a sequential order.

Abstract: A pair of internal signals are generated by halving a 3-bit 5-valued input signal, neglecting the least significant bit LSB. If the input signal shows the value of an odd number, 1 is added to either of the pair of internal signals to generate first and second signals. “1” is added to either of the pair of internal signals in an alternating way each time an input signal having the value of an odd number. Signal processing circuits selects a number of output terminals corresponding to the value of the first signal or the second signal out of a plurality of output terminals. All the output terminals are selected with a same probability.

Abstract: In a capacitor-array D/A converter which includes a thermometer decoder (103) for thermometer-decoding a decoder input signal having first through m-th (m is an integer not less than two) input bits to produce an output signal having first through n-th (n=2m−1) output bits, where m is an integer not less than two and where n is equal to (2m −1), first through n-th switches (SU1 to SU31) corresponding to the first through the n-th output bits of the thermometer decoder, and a capacitor array (104) including first through n-th capacitors (8C1 through 8C31) corresponding to the first through the n-th switches, the first through the n-th capacitors are arranged in a main area of the capacitor array and in a row direction of the capacitor array consecutively from the center outward to the left and the right to be symmetrical. Each of the first through the n-th switches are supplied with a corresponding bit of the first through the n-th output bits from the thermometer decoder.

Abstract: The present invention is related to an analog/digital converter which includes a multitude of integrating circuits, a 1 bit analog/digital converter and a 1 bit digital/analog converter. The multitude of analog integrating circuits are connected in series and the 1 bit digital/analog converter is connected downstream from the last analog integrating circuit of the series. An output signal of the 1 bit analog/digital converter is transmitted to the 1 bit digital/analog converter, and an output signal of the 1 bit digital/analog converter is subtracted from an input signal of each analog integrating circuit. A multitude of input signals is transmitted via a multiplexer to the first analog integrating circuit of the series-connected analog integrating circuits.

Abstract: A digital-analog current converter receives, at input, a succession of bits of a binary signal and delivers, at output, sampled by a clock signal, a positive or negative current depending on the state of the input bit. The converter comprises at least one circuit to control the build-up time of the output current of the converter, comprising a capacitor and a circuit to charge this capacitor controlled by the clock signal. The build-up time is controlled by the charging of a capacitor at a constant current up to a reference voltage. The circuit to control the build-up time of the output current may comprise at least two reference voltages, the capacitor being charged and then discharged between these two voltages. The build-up time of the output current is then the sum of the time taken to charge the capacitor and the time taken to discharge the capacitor.

Abstract: A switched capacitor low-pass filter incorporates a plurality of integrator stages cascade connected together. The filter includes at least one stage that includes a circuit device for cancelling out glitch pulses. This device is a deglitching circuit provided within the filter. Preferably, each stage in the filter is formed of a deglitching device which acts as a smoothing integrator.

Abstract: A switched capacitor type digital-analog converter is provided with an input capacitor group, a first switch group (3-1 to 3-n) a second switch group, a reference voltage switch (6) , a comparator (9), an output capacitor (2) and a short-circuit switch (7). The input capacitor group is composed of an input capacitor (1-0) and a plurality of shared input capacitors (1-1 to 1-n). The first switch group (3-1 to 3-n) applies a first voltage (V1) to the plurality of shared input capacitors (1-1 to 1-n). The second switch group applies a second voltage (V2) to the input capacitor group. The reference voltage switch (6) applies a reference voltage (Vr) to the input capacitor group. The comparator (9) compares an output of the input capacitor group with the reference voltage. An input of the output capacitor (2) is connected to an output of the input capacitor group, and an output thereof is connected to an output of the comparator (9). The short-circuit switch (7) is coupled to the output capacitor (2) in parallel.

Abstract: A method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface. An active continuous time summation circuit is used at the output of the switched-capacitor stage to derive the common mode level that is at the output of the switched-capacitor stage. This derived signal is filtered to remove any noise component remaining in it, and is then used as the reference common mode signal in the continuous time stage. This forces the output common mode, and hence the input common mode of the unity gain amplifier stage, to track the common mode output of the switched-capacitor stage. This adaptive tracking eliminates the common mode interface error, which could be present and could vary from die to die (due to parasitic variations). This technique ensures proper tracking of the DC levels between the negative and the positive terminals of the unity gain amplifier, which is essential for low distortion operation of the amplifier.

Abstract: In accordance with a specific embodiment of the present invention, a system is disclosed having an analog to digital converter and control module. The analog-to-digital converter includes an analog input, digital output, and control input. The control input of the analog-to-digital converter is connected to a pulse width modulated output of the control module which provides an offset pulse width modulated signal. During a first portion of the offset pulse width modulated signal a sampling capacitor is charged. During a second portion of the offset pulse width modulated signal an integration capacitor is charged.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.

Abstract: A successive approximation AD converter is provided which can produce an (m+n)-bit digital signal having high AD conversion accuracy, by using a series resistor network having m-bit resolution. A successive approximation AD converter has: a switch 4 which switches a reference voltage from a series resistor network 1 either to be supplied to an input node of a comparator or not to be supplied to the input node; a switch group 7 consisting of an n number of switches which selectively connect an n number of capacitors of a capacitor group 8 to the input node 6 of the comparator 5; and a control circuit 9 which controls on/off operations of the switch 4 and the n number of switches of the switch group 7.

Abstract: A digital-to-analog converter (DAC) includes separate converter segments for converting the most significant bits (MSB's) and next-most-significant bits (NSB's) of a digital input word. The MSB's are converted in a thermometer-encoded capacitive DAC (CDAC), in which the MSB's are decoded and used to control the state of CDAC switches, which connect any of a plurality of CADC reference voltages, through respective unit capacitors, to the DAC output. The NSB's are converted in a preferably binary encoded resistive DAC (RDAC), in which two separate sets (“A” and “B”) of RDAC switches selectively connect a plurality of RDAC reference voltages to respective A and B RDAC output buses. Control circuitry is included to decode and apply the MSB's as state control signals to the CDAC switches on each clock cycle. The NSB's are also decoded and applied as control signals, but on alternate clock cycles, to the A and B RDAC switch sets.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: This invention relates to semiconductor apparatus capable of multiple stable electronic states allowing higher order mathematical radix analysis of analog and digital signals. The device accomplishes direct A/D signal conversion with increased circuit speed while decreasing electronic component density compared to computational circuits based on binary conversion. In particular the invention relates to semiconductor apparatus and devices for analog-to-digital conversion and waveform differentiation or integration of electronic signals by use of higher order number systems. In addition the invention relates to novel construction of charge-coupled devices finding applications especially with respect to detection and manipulation of electronic signals for A/D conversion, mathematical differentiation, integration, and encryption of electronic waveform signals.

Abstract: The invention provides a method and apparatus for generating a precise and stable voltage at a high speed. More specifically, there is provided a D/A converter constructed using capacitors having capacitance values which are properly deviated from binary-weighted (2n) capacitance values. This D/A converter has the feature that even if the ratios among a plurality of actual capacitances having weighted values are different from the designed values to an extreme degree, the capacitance value of the jth capacitor is always greater than the sum of the capacitance values of the first through (j-1)th capacitors. This ensures that an unwanted reverse change in the output signal of the D/A converter is prevented from occurring. Furthermore, this technique of the invention can be accomplished without having to use an additional circuit such as a compensation circuit, and therefore this technique is easy and inexpensive.

Abstract: An A/D converter having a plurality of thresholding circuits corresponding to bits of output digital data, each of which includes odd number of inverters serially connected from a first stage to a last stage. The first stage inverter of the thresholding circuits have thresholds equal to a weights of the bits. The inverters of the last stage are of thresholds different from those of the first stage.

Abstract: A digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which integrates the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors store a binary representation of the digital input signal. The output circuit includes a zeroth order sample-and-hold circuit having first and second stages with respective first and second operational amplifiers. The first and second stages are cascaded together during a sample phase so that the analog output signal is stored in a capacitor in a feedback path between the output of the second stage and the input of the first stage, and are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.

Abstract: The present invention relates to a digital-to-analog converter for converting a parallel digital input signal to a corresponding analogue output voltage, the digital-to-analogue comprising: an input arranged to receive said digital input signal; an output for outputting said corresponding analogue output voltage; and conversion means, operatively coupled to said input and said output, for moving said output voltage from a reference value to a first value and then subsequently back to said reference value, wherein the magnitude of said first value corresponds with the value of the said digital input signal, said output voltage is moved from said reference value to said first value in at least two steps via one or more intermediate values, and said output voltage is moved from said first value back to said reference value in at least two steps via one or more intermediate values.

Abstract: A multi-bit DAC (109) is provided as part of a digital-to-analog data converter (DAC). The multi-bit DAC is comprised of a plurality of single-bit DACs (503) which have the values thereof selected through a digital encoder (505). The digital encoder (505) performs dynamic element matching (DEM) on an input data value. The sequence of selection is performed such that the element mismatch noise response of the DAC (109) is shaped. The outputs are summed at a summing junction (507) and then filtered with a low pass filter (113). In the noise shaping response, a cyclical second order response is provided with a Data Weighted Averaging (DWA) technique wherein the outputs of the DACs are restricted to one of two states. To achieve this, select ones of the output values are changed in order to comply with this restriction, thus deviating from a uniform element selection algorithm. This provides a constrained second order response which accounts for mismatching of the DAC elements (503).

Abstract: Multiplying Digital-to-Analog Converters (MDAC) multiply an analog input signal at an analog input terminal and a digital input signal at a digital input terminal to produce an analog output signal at an output terminal. The MDACs include unit capacitors and a feedback capacitor. The unit capacitors are connected to the analog input terminal during a first time interval and the unit capacitors are selectively connected to a first reference voltage, a second reference voltage or the output terminal during a second time interval in response to the digital input signal at the digital input terminal. The feedback capacitor is connected to the second reference voltage during the first time interval and to the output terminal during the second time interval.

Abstract: In a digital/analog converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)−th capacitor has a unit capacitance, and a 2k−th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)−th capacitor is connected to a first terminal of the 2k−th capacitor. Also, if m is 1, 2, . . . , n−1, an m−th coupling capacitor is connected between the first terminal of the 2m−th capacitor and the first terminal of the (2m+t)−th capacitor, while an (n−1)−th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . .

Abstract: A reconstruction filter is described. An input is configured to receive an output signal from a digital to analog converter. An input sampling circuit is operative to store a sample of the output signal from the digital to analog converter. An input pulse generating switch that generates a pulse, the energy of the pulse being determined by the sample of the output signal from the digital to analog converter. An amplifier receives the pulse at an amplifier input and provides an output signal at an amplifier output so that an output signal is produced that reduces distortion caused by imperfections in digital to analog converter.

Abstract: An oversampling digital/analog (D/A) converter is provided that has a reduced circuit area and an improved dynamic range of a converted voltage signal. The oversampling D/A converter includes an interpolation filter that receives a digital signal and oversamples the digital signal to provide a multibit digital signal. A digital noise shaper quantizes a noise contained in the digital signal passed through the interpolation filter, and an IFIR (Interpolated Finite Impulse Response) reconstruction filter converts a noise shaped digital signal in an analog signal corresponding to the noise shaped digital signal.

Abstract: A hybrid FIR/IIR analog filter for filtering the coarsely quantized output of a sigma-delta modulator for digital-to-analog conversion. The functions of an FIR and IIR filter are combined into one circuit to gain the benefits of both, while requiring fewer taps than the present FIR approach, and requiring less area as an IIR filter.

Abstract: Disclosed is a switched capacitor type D/A converter, which comprises: an operational amplifier; a plurality of capacitors; a plurality of first switches which alternatively change connection thereof dependently on whether the filter is in an output mode or a reset mode so that the filter realizes an offset canceling function; a voltage source; and a second switch for directly connecting an output of said operational amplifier with said voltage source at a beginning of the reset mode.

Abstract: A digital to analogue converter includes at least one capacitor for storing an analogue output voltage resulting from the digital to analogue conversion. The converter further includes an output switch arrangement coupling the at least one capacitor to an output of the converter. The output switch arrangement is operated a plurality of times for each digital to analogue conversion, so that the analogue output voltage is switched to the output of the converter a plurality of times for each digital to analogue conversion. Each switching operation reduces the influence of an output load capacitance on the output signal. As a result smaller components can be used in the converter to achieve a given output signal resolution.

Abstract: A digital-to-analog converter (DAC) uses switched capacitors summed, to an op amp to generate the analog output voltage. Least-significant-bits (LSBs) of the digital input switch a reference voltage to binary-weighted capacitors. The most-significant-bits (MSBs) are thermometer-coded and switch the reference voltage to capacitors that have a same size, double the size of the maximum LSB's capacitor. The thermometer-coded MSB's are scrambled before switching the same-size capacitors so that the assignment of a digital input bit to a capacitor varies from sample to sample. Any variation in capacitances for the same-size capacitors is thus spread to different digital values so that errors do not occur consistently for the same digital values. The scrambler uses radix-2 butterflies to swap bit assignments and thus outputs an even number of signals to the capacitors. Since the thermometer code is an odd number of signals, an extra signal is present that is always driven high or low.