Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

Abstract: A method for operating an ADC includes storing a sampled input charge on a capacitance of a sample-and-hold circuit including a DAC. The sampled input charge is stored using a first reference signal coupled to the DAC and a second signal. The sampled input charge has a value based on a first digital code. The method includes converting a second digital code to an analog signal on the first node using the DAC, the sampled input charge, and the first reference signal. The second digital code is one least-significant bit different from the first digital code. The method includes generating a monotonicity indicator indicating whether an output analog signal of the DAC is monotonic in response to a transition of a digital input of the DAC from the first digital code to the second digital code based on a comparison of the analog signal to the second signal.

Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

Abstract: A device for noise suppression and distortion correction of analog-to-digital converters based on deep learning that realizes effect of correcting noise and distortion of analog to digital converters. The method is applied to electronic ADCs or photonic ADCs. It utilizes the learning ability of the deep network to perform system response learning on ADCs which need noise suppression and distortion correction, establishes a computational model in the deep network that can suppress the reconstruction of noises and distorted signals, performs noise suppression and distortion correction on the signals obtained by ADCs, and thereby improves performance of the learned ADCs. The device improves the performance of the microwave photon system with high sampling precision of microwave photon radar and optical communication system.

Abstract: A closed-loop control device to control a system to be controlled includes a front node, back node, external tapping point, controller and compensating circuit. The compensating circuit has an inner node, frequency filter, front buffer and back buffer. The front node determines a difference; the back node supplies an external sum signal. A setting device automatically suppresses use of the output signal of the front buffer, supplies the back buffer and the back node with a first excitation signal as the compensation signal and detects a first result signal produced by the first excitation signal. The first result signal is one of the control difference, internal sum signal, output filtered signal of the frequency filter or output signal of the front buffer. The setting device evaluates the first excitation signal and the first result signal, sets a parameter of the frequency filter and the second propagation delay.

Abstract: An apparatus is disclosed that includes a transmit chain, a duplexer, a receive chain and a control circuit. The transmit chain is configured to generate a transmit signal at a transmit frequency. The duplexer is configured to pass the transmit signal to an antenna that generates a transmit leakage current into a received signal. The receive chain is configured to obtain the received signal and measure the leakage current from the transmit chain. The control circuit is configured to determine reduced performance parameters for the transmit chain based on the determined leakage signal, wherein the transmit leakage signal is inversely proportional to the reduced performance parameters.

Abstract: Apparatus for use in a system, including a microcontroller for controlling the system, where the microcontroller includes at least one internal module capable of generating a periodic pulse signal. The microcontroller is programmed and operated so that the internal module generates a periodic pulse signal that is a pseudo-random spread spectrum oscillator signal. A switching mode power supply is responsive to the pseudo-random spread spectrum oscillator signal. The switching mode power supply comprises a solid state switch and a modulator for driving the solid state switch with a drive signal related to the periodic pulse signal generated by the internal module of the microcontroller.

Abstract: A shift register (10), a gate driving circuit and a repairing method therefor, and a display device.

Abstract: A transmitter includes: a digital modulator configured to modulate a base-band signal in a digital domain into a modulated signal; a synchronization module configured to synchronize the modulated signal with a clock signal; and an analog output stage configured to convert the modulated signal into an analog signal for transmission.

Abstract: The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion. The converter includes a dual switching circuit for the currents of the differential branches: a first switching circuit enables the transmission of the currents of the differential branches toward the loads for 70% to 95% of the clock period and shunts these currents outside the loads for the rest of the time; a second switching circuit alternately and symmetrically makes a direct link followed by a cross link between the differential branches and the loads.

Abstract: There is provided A DA converter in which the N current switch cells each include: a current source having one end connected to a first power source; and first and second switch transistors differentially operating each other, each having a control terminal receiving a digital signal, the first combining node combines a current output from the first switch transistor in each current switch cell, the second combining node combines a current output from the second switch transistor in each current switch cell, the first output impedance element has ends connected to the first combining node and a second power source, the second output impedance element has ends connected to the second combining node and the second power source, the controller controls the current source in each current switch cell to reduce variation in amount of a current flowing from the first power source.

Abstract: Systems and methods provide for the control of a fully-segmented digital-to-analog converter. The selected lead-most current cell of an array in the digital-to-analog converter is addressed individually using a row/column scheme and a decoder. The remaining current cells behind the lead-most current cell are enabled via a ripple enable signal that propagates backwards from the lead-most current cell. The ripple enable signal snakes through the array to enable all the current cells behind the lead-most current cell in a cell-by-cell fashion. The current cells in front of the lead-most current cell are not enabled.

Abstract: A current controller includes impedance elements coupled to form at least one impedance ladder circuit which exhibits a fixed impedance at an input and current divider steps each differing in a current magnitude by a multiple of three with respect to the current magnitude in an adjacent less significant step. Single pole triple throw (SPTT) switchably couple an associated step in the impedance ladder circuit to one of three outputs. Three discrete current sources or sinks are each coupled to a corresponding one of the outputs of each of the SPTT switches. The digital driver is coupled to each control input of each SPTT switch to additively deliver selected ones of the stepped currents from each step of the impedance ladder circuit to a corresponding selected one of the current sources or sinks.

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

Abstract: A digital to analog converter and a method for controlling a current source array in a digital to analog converter relate to the field of electronics technologies, and are used to reduce a system error. The digital to analog converter includes: a decoding module, a switch array, and a current source array, where the decoding module is configured to generate a 2n?1-bit first temperature code by using high n bits of an input 2n-bit binary digital signal, generate a 2n?1-bit second temperature code by using low n bits of the 2n-bit binary digital signal, and control, by using the 2n?1-bit first temperature code and the 2n?1-bit second temperature code, a working sequence of 2n×2n?1 unit switches.

Abstract: An apparatus relating generally to digital-to-analog conversion is disclosed. In such an apparatus, a digital-to-analog converter (“DAC”) device includes a source DAC and a sink DAC selectively coupled to one another. The source DAC provides a first bias to the sink DAC in a sink mode, and the sink DAC provides a second bias to the source DAC in a source mode.

Abstract: A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.

Abstract: An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal.

Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.

Abstract: A D/A conversion circuit includes: current generation circuits each including a constant current source configured to generate a current, a first MOSFET connected to the constant current source and configured to control a supply destination of the current, a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET, and a first discharge switch connected to the first gate control section and the gate of the first MOSFET, controlled to be turned on at the same time as the first gate control section supplies the second voltage and controlled to be turned off before the first gate control section supplies the first voltage; a first current addition line; a discharge line; a first resistor connected to the first current addition line; and a voltage source configured to supply the second voltage to the first gate control sections.

Abstract: A digital to analog converter (DAC) includes: first and second nodes; a first switching device; a second switching device; and a switch control module. The switch control module selectively configures the first and second switching devices such that: in a first configuration, the first switching device connects a first current to the first node and the second switching device connects a second current to the second node; in a second configuration, the first switching device connects the first current to the second node and the second switching device connects the second current to the first node; and in a third configuration, the first and second switching devices disconnect the first current and the second current from the first and second nodes.

Abstract: An example digital-to-analog converter includes a reference scaling circuit receiving a first reference current and generating a second reference current. A first plurality of current sources is coupled to a summing node with a current of a first one of the first plurality of current sources proportional to the first reference current. A current of a second one of the first plurality of current sources is substantially equal to twice the current of the first one of the first plurality of current sources. A second plurality of current sources is coupled to the summing node. A current of a first one of the second plurality of current sources is proportional to the second reference current. A current of a second one of the second plurality of current sources is substantially equal to twice the current of the first one of the second plurality of current sources.

Abstract: A dynamically selectable resistor network is provided in a star configuration for producing a weighted sum of input values, without attenuation from near zero contributions. Each branch of the star connected network comprises sets of impedance components, preferably resistors, that are actively selectable to produce permutated combinations of effective weighting values. The resistors code digital control bits and the outputs of sets of resistors in respective branches that correspond to the least significant control bits provide their outputs to the summing output node independently of the sets of resistors corresponding to control bits of other significance.

Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.

Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.

Abstract: One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

Abstract: A “multiple return-to-zero” (MRZ) current switching DAC. In operation, the outputs of respective current sources are selectively directed to respective intermediate nodes in response to respective control signals which vary with a digital input word, and in synchronization with a clock CK1. A plurality of MRZ current switches are connected between respective intermediate nodes and the DAC's analog output. The MRZ switches are driven with a clock CK2 which toggles in synchronization with CK1 at a frequency fCK2=N*fCK1. The MRZ switches are operated such that switching noise that arises when CK1 is asserted is prevented from appearing on the analog output. When properly arranged, the DAC can generate a direct digital waveform at RF frequencies, with N chosen to produce an output spectrum such that the DAC's output power is relatively high within the desired frequency range.

Abstract: In a method for improving resolution and for correcting distortions for a sigma-delta modulator, a modulator converts an analog input signal into a secondary output digital signal sampled at a frequency fe and coded on NB bits, a second main output digital signal s?(t) is represented on NMSB bits also being available at the output. At least three processings are applied successively to the outputs, a first processing carrying out a demodulation by a frequency f0 and a decimation of factor N in an independent manner, z second processing carrying out an improvement of the resolution and a third processing carrying out a correction of the distortions. These three processings are carried out after decimation. A sigma-delta modulator implements the method.

Abstract: Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.

Abstract: A digital-to-analogue converter, with application to electronic circuits with neuromorphic architecture, comprises: transistors of identical nominal geometrical characteristics, but of dispersed current-voltage characteristics, wherein when a constant gate-source voltage is applied to the different transistors, a current varying as a function of the dispersion circulates in the transistor; a digital table receiving a digital word and having a selection output selecting, as a function of the word to be converted, a transistor or transistors supplying a current of desired value representing this word in analogue form. The look-up table is loaded as a function of real measured current-voltage characteristics of different transistors of the set, to establish a look-up between words and current values.

Abstract: A digital-to-analog converter (DAC) uses thermometer coding over a certain code range. A switch array for the certain code range is implemented into a smaller area of the integrated circuit die so as to take advantage of the lower gradient inherent in the smaller area. By implementing the certain input code range into the smaller switch array area, further improved linearity in that input code range is achieved at the expense of worse linearity in the other input code ranges, but without increasing power consumption and/or chip-area of the integrated circuit die.

Abstract: A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2n control bits normally required can be reduced to 2(n-1) by jointly controlling pairs of the current sources with one of the 2(n-1) current control bits and inverses of two other ones of the 2(n-1) current control bits.

Abstract: A current digital-to-analog converter (DAC) is disclosed. The current DAC includes a current reference circuit coupled between a voltage source terminal and a voltage node, wherein the current reference circuit includes a feedback node. A switchable resistor network is communicably coupled to the feedback node of the current reference circuit via a first feedback network that is adapted to equalize a first voltage across the switchable resistor network voltage with a second voltage between the feedback node and the voltage node. A current mirror includes an output node communicably coupled to the switchable resistor network via a second feedback network that is adapted to equalize an output current that flows from the output node with an input current that flows into the switchable resistor network.

Abstract: A dynamically selectable resistor network is provided in a star configuration for producing a weighted sum of input values, without attenuation from near zero contributions. Each branch of the star connected network comprises sets of impedance components, preferably resistors, that are actively selectable to produce permutated combinations of effective weighting values. The resistors code digital control bits and the outputs of sets of resistors in respective branches that correspond to the least significant control bits provide their outputs to the summing output node independently of the sets of resistors corresponding to control bits of other significance.

Abstract: An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

Abstract: [Means for Solving the Problem] In a current switch circuit A used for a current steering D/A converter, a current switch basic circuit 1 includes first and second transistors Tr121 and Tr122 included in a differential switch 12. A threshold voltage control circuit 5 has an output terminal Vbout controlling the substrate voltage to be outputted to the substrate terminal of each of the two transistors Tr121 and Tr122 included in the differential switch 12 for controlling the threshold voltage of the two transistors of the differential switch. Accordingly, the present invention improves the decrease in the dynamic range of the current switch basic circuit 1 dependent on the threshold of each of the two transistors in the differential switch 12 and realizes a wider output voltage range without causing deterioration in properties even in a case that the power voltage is reduced in the current switch basic circuit 1.

Abstract: A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits.

Abstract: An example digital-to-analog converter includes a reference scaling circuit receiving a first reference current and generating a second reference current. A first plurality of current sources is coupled to a summing node with a current of a first one of the first plurality of current sources proportional to the first reference current. A current of a second one of the first plurality of current sources is substantially equal to twice the current of the first one of the first plurality of current sources. A second plurality of current sources is coupled to the summing node. A current of a first one of the second plurality of current sources is proportional to the second reference current. A current of a second one of the second plurality of current sources is substantially equal to twice the current of the first one of the second plurality of current sources.

Abstract: A current digital-to-analog converter (DAC) is disclosed. The current DAC includes a current reference circuit coupled between a voltage source terminal and a voltage node, wherein the current reference circuit includes a feedback node. A switchable resistor network is communicably coupled to the feedback node of the current reference circuit via a first feedback network that is adapted to equalize a first voltage across the switchable resistor network voltage with a second voltage between the feedback node and the voltage node. A current mirror includes an output node communicably coupled to the switchable resistor network via a second feedback network that is adapted to equalize an output current that flows from the output node with an input current that flows into the switchable resistor network.

Abstract: A digital-to-analog converter is disclosed. An example digital-to-analog converter circuit includes a reference scaling circuit coupled to receive a first reference current. The reference scaling circuit is coupled to generate a second reference current in response to the first reference current. The digital-to-analog converter circuit also includes a first plurality of binary-weighted current sources coupled to a summing node. A current of a first one of the first plurality of binary-weighted current sources is proportional to the first reference current. The digital-to-analog converter circuit also includes a second plurality of binary-weighted current sources coupled to the summing node. A current of a first one of the second plurality of binary-weighted current sources is proportional to the second reference current.

Abstract: Circuits, methods, and apparatus that provide highly accurate DCPs. One example provides a DCP that includes a resistor string having taps that may be selected by a corresponding number of switches under the control of a digital word. To compensate for parasitic switch resistances and for variations in the values of the resistor sting caused by processing tolerances, a voltage-controlled resistor (VCR) is placed in parallel with the resistor string and switches. A control voltage generated using a control loop adjusts the parallel VCR such that the resistance seen across the DCP is the desired value. The control loop compares a reference resistor to loop components that are scaled to the resistor string, switches, and VCR. The reference resistor may be an external resistor or an internal resistor. If the resistor is internal, it may be trimmed, for example with lasers or fuses.

Abstract: A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

Abstract: Provided is a resistive digital-to-analog converter capable of reducing a digital-to-analog conversion error caused by a change of the on-resistance of a transistor. On-resistance correcting PMOS transistors Q2 to Q2N?1 or on-resistance correcting NMOS transistors Q2? to Q2N?1? are respectively connected in parallel to at least one of switching MOS transistors Q1 and Q1? in each of switch circuits S1 to S2N?1. Each of the on-resistance correcting PMOS transistors and the on-resistance correcting NMOS transistors is connected to correct the change of the on-resistance occurring with a change of an analog signal caused by a change of a multi-bit digital input signal. The on-resistance correcting PMOS transistors Q2 to Q2N?1 or the on-resistance correcting NMOS transistors Q2? to Q2N?1? are switched on or off in conjunction with switching of the switching MOS transistors Q1 and Q1? according to the change of the digital input signal.

Abstract: The disclosed embodiments provide method and apparatus for digital to analog conversion of a signal that may be limited to a bandpass frequency. In an exemplary embodiment, a bandpass DAC is disclosed which includes a plurality of gates. Each gate receives a carrier signal and one of a plurality of input bits of a digital data. A combiner network is provided which includes a plurality of lossless elements corresponding to each of the plurality of gates. The combiner network receives the gate outputs and provides a digitally weighted signal. A resonating element connected to the combiner network resonates the combiner network and provides a filtered output signal which is linearly combined.

Abstract: A circuit configured to generate an analog signal having a pre-determined pattern. The circuit includes a plurality of digital-to-analog converters. Each of the plurality of digital-to-analog converters includes a plurality of current sources configured to generate a plurality of square waveforms and a summer configured to sum the plurality of square waveforms to generate the analog signal having the pre-determined pattern. Each square waveform is delayed by a pre-determined amount delay relative to another square waveform of the plurality of square waveforms. The pre-determined amount of delay between each square waveform of the plurality of waveforms is adjustable to adjust the pre-determined pattern of the analog signal. The pre-determined amount of delay is non-uniform throughout the circuit.

Abstract: The disclosed embodiments provide method and apparatus for digital to analog conversion of a signal that may be limited to a bandpass frequency. In an exemplary embodiment, a bandpass DAC is disclosed which includes a plurality of gates. Each gate receives a carrier signal and one of a plurality of input bits of a digital data. A combiner network is provided which includes a plurality of lossless elements corresponding to each of the plurality of gates. The combiner network receives the gate outputs and provides a digitally weighted signal. A resonating element connected to the combiner network resonates the combiner network and provides a filtered output signal which is linearly combined.

Abstract: Provided is an output apparatus for outputting a current from an output end, including: a plurality of current sources; a plurality of switches provided in association with the plurality of current sources respectively, and switching whether to supply a current of a corresponding current source to the output end; a time changing section that changes a propagation time of each of a plurality of control signals for controlling switching states of the plurality of switches respectively; and an adjusting section that adjusts the propagation time of each of the plurality of control signals to reduce glitch noise contained in a current supplied to the output end.

Abstract: An example digital-to-analog converter (DAC) for a power supply controller includes a first node, a second node, a current source, and a switch. The first node is to be coupled to provide a first analog signal to a variable oscillator of the power supply controller. The second node is to be coupled to provide a second analog signal to the variable oscillator of the power supply controller. The switch is coupled to the current source and configured to couple the current source to the first node to provide current to the first analog signal in response to a binary digit received by the DAC, where the switch is further configured to couple the current source to the second node to provide current to the second analog signal in response to a complement of the binary digit.